By Ed Sperling
Standards groups are beginning to look at power and other physical effects much more seriously in the wake of the dueling power formats—UPF and CPF—that have caused angst across the design industry.

To put it in perspective, when CPF and UPF were first introduced power was something of an afterthought in design. At 65nm it ceased to be something that could be dealt with later in the design process, and at 28nm it has become an essential part of the architecture. But as battery life, mobility, and energy costs even for plugged-in devices become overriding concerns, power now needs to be considered at full system level, which could mean everything from a rack of servers to an automobile.

Much of this is being driven from the chip level, and in the software that manages chips and interactions between chips. There are at least a half dozen new standards efforts under way or on the drawing board. Most heavily leverage the expertise of chipmaker and where they have encountered or expect to encounter pain in designs, most notably in stacked die or in planar SoCs below 20nm, or from tools vendors that have gained expertise in a specific area.

Si2 currently has one standard in legal review for system-level power modeling. The standard is called “atomic” power modeling, based on the assumption that the model cannot be broken down into smaller pieces, although it can be used at various levels of abstraction.

Also in the works is a standard for co-design, which is one of the most difficult challenges facing design today. While hardware engineers are well versed in how to build an energy-efficient chip, that engineering effort can be wasted if the software running on an SoC isn’t energy-efficient, as well.

“The first step is to get there with the architectural ESL level,” said Steve Schulz, president and CEO of Si2. “Then, we will look at how the software runs and develop a bridge. You will never get the software community to adopt the hardware approach to design. That community is 20 to 30 times larger than hardware engineers and they have their own tool flows. We have to think about a minimally intrusive solution. We’ve called it a bridge to the software world, and if it’s not intrusive then the software teams will use it. Most of them will never understand concurrency and how to get to a GDS II stream, but there are characteristics that are reasonable proxies of the details. You don’t simulate all the code, but you do generate enough discrete choices so everyone can get on the right track for power.”

A first step in that direction is finding data objects that can be passed back and forth between the software and hardware teams. From there a power model will need to be created across both. The power-flow group within Si2 has been reactivated to develop a source for the power model. “The focus this year will be hardware,” said Schulz. “In 2013 we will turn our attention to understand the data objects stored.”

That puts the likely adoption timeframe a of a co-design framework for power in the 2015 time frame—roughly at the 14nm process node and at a time when 2.5D stacking is expected to be mainstream and 3D stacking will become more commonplace.

Stacking effects
“There are two new requirements for design,” said Andrew Yang, president of Apache Design. “The first is a 3D IC flow. The second is an RTL-to-gate power methodology.”

Included in the 3D requirements is the need for multi-die thermal and stress analysis. Yang said the key is the amount of current a design can sustain without failure over time, and it gets worse at advanced nodes and sometimes in stacked configurations because wire handling capability is decreasing, power density is increasing, and electromigration is increasing.

3D IC thermal stress analysis. Memory die is impacted by power distribution of logic die. Source: Apache Design.

“This can be a safety issue,” he said. “You need to make sure the metal topology is handled correctly. Electromigration is affected by heat. The hotter it gets, the less current a metal wire can sustain. The electromigration rules are increasing, which is why GlobalFoundries, Intel and TSMC are all coming up with complex electromigration rules.”

Front to back, back to front
Being able to get a chip out the door at all is a challenge, which is why there are more standards being dictated from the foundries these days. In addition to process variation, continually shrinking geometries is making it harder to obtain adequate yields as quickly as in the past. That has led to more rules for place and route, test, IP, and layered across all of those is power.

“We’re seeing it in the available sizes, speeds, memory and logic cell sizes,” said Chris Rowen, CTO at Tensilica. “That’s what we target—area, power and process compatibilities. Whether that’s stacked or conventional die is affected only subtly. But with die stacking you will see significantly higher bandwidth and less latency, which will have an effect on modeling of the system. It’s not a qualitative change, but it is a quantitative change. It won’t change how one DSP communicates with another, but it will change how DSPs communicate with memory.”

How much of that will be standards promoted by standards bodies versus de facto standards from the largest foundries remains is unknown. Also missing are good open standards for on-chip debug and trace, said Rowen.

ESL standards
One of the most glaring holes in all of this is at the ESL level, where standards for power models are non-existent. While this isn’t a big problem in a single vertically integrated company, it’s a huge problem in a disaggregated supply chain where various companies work on designs—something that will become even more pronounced in stacked die where subsystems at different process geometries need to be integrated with other subsystems.

“What’s missing is something that allows companies to exchange power models, especially for IP-based designs” said Ghislain Kaiser, CEO of Docea Power. “In an ideal flow you would be able to take the IP from the IP suppliers and put together a power model and assess the power impact on the underlying hardware. But you also need to have interoperability between suppliers and customers that goes beyond the semiconductor level. It has to be optimized at each level—the SoC, the chip set, the PCB and above. So there won’t be only one number.”

The accuracy of those power models also will shift throughout the design. At the beginning a model may be only 40% accurate, but at the end it may need to be accurate to plus or minus 5%, Kaiser said.

Other pieces are missing, as well. Kiran Vittal, senior director of product marketing at Atrenta. “Right now, when a designer uses memory they don’t realize the code they are writing is not optimized for power. When you read memory you get a redundant read. The controller code isn’t optimized for memory. And all of that has to be networked, because you may have as many as 2,000 memories in a design. If you do it right you can save about 20% of the memories and the power needed to run them.”

To show just how bad this can get, a large systems house was designing a chip was required to give an early indication of its power budget to the OEM. The OEM used that estimate for calculating its own power budget and came up with a spreadsheet that represented the total design. The problem was that the spreadsheet ultimately was off by 100% in its power estimate, which in turn caused problems with the final device and greatly increased the amount of time it took to successfully bring a product to market.

“A lot of the ESL tools today know performance and area, but they don’t have a clue about power,” said Vittal. “This is fertile ground for innovation.”

By Ed Sperling
The Consumer Electronics Show used to be about cool gadgets and really fast performance. Now it’s about really cool gadgets—the kind that use less energy.

Witness Intel’s big announcements at CES this year. The company showed off its Medfield processor aimed at the tablet market, and it entered a multi-year, multi-device relationship with Motorola based on Atom processors and Android. It even made a big splash about the ultrabook market, which is important now that the netbook market has largely evaporated. At the heart of all of this stuff is lower leakage—remember the finFET—less energy consumption, and reasonable performance.

Texas Instruments made a big push into the low-power Bluetooth market with a low-energy SoC it claims uses 33% less power. The company claims the chip will enable low-power sensors that can operate for more than a year on a coin-cell battery.

Even Nvidia, which has always been about raw performance, is now pitching power conservation through its fifth core—a lower performance, lower-power addition to its four-core Tegra 3 chip. In many ways, this does on a single chip implementation what laptop makers are doing with multiple chip implementations.

While each of these moves separately might be a market test, collectively they speak about a much more important trend in design. Making the battery last is now every bit as important to a design as area, performance, features and cost.

By Hamilton Carter and John Blyler

Legendary physicist and inventor, Nikola Tesla, conducted some of his most shrouded work in a forgotten lab at Wardenclyffe, NY. On November 5, 2011, that lab will come alive as the site of a major event (see Figure 1).

Figure 1: QSL card image, created by ham radio cartoonist, Jeff Murray, K1NSS.

At the turn of the 20th century, The Wardenclyffe lab was built to provide wireless power and communications across the planet. That potential was never realized as the world’s most powerful capitalist – J.P. Morgan - removed his funding from the project before it was completed.

On November 5th, ham operators will broadcast from the Wardenclyffe lab to raise awareness about a restoration effort led by the TeslaScienceCenter.org - a non-profit that will also host a Tesla conference at Brookhaven National Laboratory on the same day (see Figure 2).

Figure 2: Physicist Nikola Tesla’s Wardenclyffe laboratory, then and now.

Also on that day, a special ham radio event station, YU0TESLA, will broadcast from Telsa’s homeland in Belgrade, Serbia.

Finally, the New Yorker Hotel will serve as the final broadcast center for the event. Telsa spent his dying years working in the basement of this historic hotel.

Want to learn more about the history behind the Wardenclyffe lab and the reawakening of Telsa’s original vision for wireless power? Then read on.

Legendary Physicist and Inventor

Nikola Tesla, a scientist, engineer, and inventor that lived during the turn of the 20^th century, has been the unheralded inventor of radio. Also, he created the alternating current system that supplies power to the United States as well as the rest of the world. Every time someone plugs in an electrical or electronic device, they are using one of Tesla’s inventions.  

Tesla’s last big project started in Colorado Springs, CO, and ended in Shoreham, NY on Long Island.  In addition to providing radio communications for the world, he was convinced that power could be provided wirelessly as well.  He built a prototype of his system in Colorado Springs.  It pulled so much power from the city’s generators that they caught on fire.  Tesla had to pay to have them reconstructed to meet his specifications. This is the laboratory that was featured in the movie, ‘The Prestige’ (see Figure 3).

Figure 3: David Bowie as Nikola Tesla in The Prestige (2006). (Courtesy of Touchstone Pictures 2011)

After prototyping his wireless power system in Colorado Springs, Tesla returned to New York to obtain startup funding. Soon after, construction began on Wardenclyffe Laboratory in Shoreham, NY.  The laboratory, architected by Stanford White, was supposed to the be the center of ‘Radio City’ where people would send telegrams, voice messages and pictures all over the world.

The planned system was a precursor of the Internet – almost 100 years earlier! As the 186 foot tall tower was constructed Tesla’s funding sources got wind of Tesla’s plan to supply power for free to the world. That news combined with Marconi’s successful trans-Atlantic radio transmission led to Tesla’s funding sources pulling all support. Wardeclyfe was operated once and then fell into disrepair (see Figure 4).

Figure 4: Even in disrepair, Wardenclyffe lab still contains treasured engineering artifacts. (Courtesy of Hamilton Carter)

Eventually the tower was torn down and sold for scrap, but the laboratory building remains on the site to this day. Now, the building is for sale. A group of citizens in Shoreham, NY,  are trying to purchase the building to turn it into a science museum and study center - the Tesla Science Center.  To get the word out, the citizens are hosting on November 5th, 2011, a Tesla conference in Rocky Point, NY, just a few miles from Wardenclyffe.

In conjunction with the conference, radio transmissions via amateur radio special event station W3T will be sent from Wardencllyffe for the first time in over 100 years. The station will operate in conjunction with several other stations from all over the world to commemorate the event. Getting the Wardenclyffe back on the air for one day is a story of global connections, Internet technology and serendipitous timing.

Wireless Power Reawakens

Physicist Nikola Tesla’s discoveries in wireless power has slumbered for the last century or so. Only in the last decade has interest in Tesla’s forgotten research been awakened, thanks in large measure to the proliferation of high performance, power-hungry mobile devices.

Among the many recent announcements of wireless power research and products, perhaps the one most closely aligned with Tesla’s original work was come from the telecommunication industry. Several years ago, cell-phone maker Nokia was developing technology to transfer enough power from ambient radio waves to maintain a healthy charge on a cell-phone handset. The ambient sources of electromagnetic (EM) radiation included transmissions from Wi-Fi, mobile phone, TV and other antennas.

To date, the power harvested from EM transmissions is low, in the neighborhood of 50 milliwatts. This is enough power to slowly recharge a phone that has already been powered down. Still, it is a start.

Today’s inventors take advantage of resonant coupling to harvest EM transmissions. As the name implies, magnetic coupling is achieve at resonance – i.e., the same frequency – between the EM source and the harvesting receiver.

During an Intel research project demonstration, the chip company used a large coil source with supporting electronics to create current oscillating at 7 MHz. The harvesting receiver coil was tuned to the same frequency as the source. The resulting resonant energy transfer achieved 80 percent efficiency within a range of about a meter.

Figure 5: Intel researches resonant wireless power transmission. (Courtesy of Kate Greene)

One way to increase the amount of transferred power while extending the range is to harvest the EM signal at many different frequencies. This requires a wideband receiver to capture signals between 500 MHz to 10 GHz, noted Nokia researchers.

Today, wireless power finally appears poised to enter mainstream consumer devices. Earlier this year, Texas Instruments (TI) announced a Qi-compliant wireless power receiver which was 80 percent smaller than its previous chip. Qi is a wireless charging standard developed by the Wireless Power Consortium (WPC).

The small size of TI’s subsystem should make it easier for manufacturers to incorporate wireless power recharging into many new devices; from cell-phones to game consoles, digital cameras and more. The company claims that the power chip will provide 93% peak efficiency while allowing charge rates comparable to AC adapter. No range limit information was available (see Figure 6).

Figure 6: TI's wireless power charging subsystem.

By Ed Sperling

Highway harvesters
Hybrid cars may be taking on a new dimension. Rather than just running on batteries and gas, they could also generate their own energy.

This has happened already to a small degree with regenerative braking, which puts energy back into the car’s battery. But energy scavenging has come a long way since that concept was first developed.

The next challenge is to go well beyond just powering the infotainment in a car and actually use it to power the motors. IDTechEx contends that future vehicles may have energy harvesting spread throughout them, from flexible photovoltaic cells that wrap around the car to energy-harvesting shock absorbers.

This creates a new category of car—one that generates as well as uses energy. But the key is that it can use much less energy, go significantly farther on a single charge or tankful of gas, and probably be accomplished for a very low additional cost.

Cooler data centers
There have been two dueling problems inside of data centers for the past decade. One is heat, the other is energy. Both are related. The more servers, the more heat, and the more money it costs to power those servers and to cool them.

HP’s announcement that it is building extreme low-energy servers based on ARM’s, which it calls Project Moonshot, takes an interesting approach to this problem. Rather than thinking of servers as individual machines, it also allows resources to be shared throughout a data center. HP estimates energy can be cut by up to 89% using 94% less space.

Those are interesting numbers, and they speak volumes about the interest in energy costs rather than just performance. Energy costs are the main reason why Facebook just signed a deal to build a data center in northern Sweden, where outside air can be used to cool racks of servers 10 months of the year without turning on the chillers. They’re also the reason why data centers are being built along the Columbia River Gorge in Oregon, and in Arizona, which has a surfeit of energy produced by nuclear reactors.

This doesn’t end the war between Intel and ARM in this space, however. HP is planning to include Atom-based processors from Intel, as well, in the future. But the real key is that after nearly 60 years of focusing on performance in each subsequent server release, the central theme is now all about power.

By Ed Sperling
The race is on to provide enough performance gains to justify an upgrade while relentlessly pushing to extend battery life. The goal is nothing short of turning every mobile device into the processing equivalent of a notebook computer, regardless of the form factor.

This trend has been evident for some time, but momentum is building. ARM this week introduced its “big.LITTLE” processor, with its Cortex-A7 processor that it claims is five times more energy efficient than the Cortex-A8 with “significantly” better performance in just 20% of the area. http://www.arm.com/about/newsroom/arm-unveils-its-most-energy-efficient-application-processor-ever-with-biglittle-processing.php

Intel’s 22nm Ivy Bridge chip, meanwhile, has entered production. Intel has said its TriGate FinFET technology would be available at that node, as well, dramatically reducing the power. It’s questionable whether the rest of the industry will follow Intel on the FinFET path at 22nm/20nm, or whether it will substitute other technologies such as SOI and bridge the gap to 14nm. But either way, the direction is clear. More processing power, but a big push toward energy efficiency with maybe some area gains thrown in for good measure.

This is only a piece of the puzzle, of course. Software is becoming much more power aware. Mentor Graphics announced this week that it has added dynamic frequency and voltage scaling capabilities into the kernel of its Nucleus RTOS. While many consumers are used to this kind of capability in general-purpose OSes such as Windows and Mac OSX, RTOSes are also widely used in microcontrollers and in parts of a device that has not been particularly power-aware, if at all. This is the embedded space, after all, and for many companies this has been black-box technology. http://www.mentor.com/company/news/mentor-nuclues-rtos

In the future all pieces will be power-aware, including the IP, firmware and software applications. That should give an even further boost to energy efficiency, along with the need for co-development of hardware and software at an unprecedented scale. Power is a universal concern. There is only one battery, and everyone has to share it—and worry about it.

Intel working with solar power and 3D stacking
Intel Labs rolled out a novel concept this week—a new CPU architecture that it claims will offer five times the energy efficiency of other Pentium-class processors while offering the ability to run off a postage-stamp sized solar cell.

What’s unique about this approach is that the CPU drops below 10 milliwatts when its workload is load, but can utilize Intel’s burst approach to add in more cores when necessary. Bursting is akin to on-chip virtualization, in that it allows a single application to utilize any available processing resources.

Even more intriguing, though, is Intel’s collaboration with Micron on the latter’s Hybrid Memory Cube, which it claims will add a seven-fold improvement in energy efficiency over DDR3. In case you wondered whether Intel was experimenting with 2.5D and 3D stacked die architectures, this should provide the answer. The HMC is a 3D stacked die package, which greatly improves density and speed by adding multiple layers of chips connected with through-silicon vias. That both shortens the distance and widens the data pipes, while simultaneously requiring less energy to drive signals.

Most researchers look at stacked die as the best way to cut power while also improving performance. The fact that Intel already is collaborating with Micron on this approach opens up some interesting possibilities for the processor giant’s move into the low-power SoC world.

Lower power capacitors and transistors
Researchers at UC Berkeley are using a ferroelectric layer—in this case lead-zirconate-titanate—on an insulator to cut the minimum voltage needed to store a charge in a capacitor. By using this combination the charge can actually be amplified, creating negative capacitance and solving one of the big issues with capacitors.

The initial work was done at 200 degrees Celsius, but new materials are expected to allow this principle to operate at room temperature. They’re also working on putting these materials into transistors, which is where things get even more interesting. One of the big challenges in dropping the voltage inside of SoCs is the minimum needed to safeguard function and prevent data loss through gates. It remains to be seen whether amplifying a charge can actually alter the minimum voltage, but it’s certainly worth a try.

Perhaps even more interesting is who else is funding this effort—Semiconductor Research Corp. and the Office of Naval Research.

–Ed Sperling

By Mike Demler
Minimizing on-chip power consumption continues to be one of the greatest challenges facing SoC designers. Everyone who owns a cell phone has undoubtedly seen the effect on limited battery life firsthand, but the impact on the unseen compute servers in “the cloud” is even more severe, making total electrical operating costs greater than the hardware expense, according to AMD Fellow Stephen Kosonocky.

In his presentation at the recent Hot Chips Conference, Kosonocky shared the experiences of the AMD Llano APU (accelerated processing unit) design team and how they addressed these challenges. By integrating a quad-core CPU architecture with a GPU in Llano, AMD was able to eliminate the power that would have been consumed by chip-to-chip I/O, and increase the bandwidth between the CPU and memory by 3X. To achieve this integration, the team implemented a complex power management scheme that required power gating (PG) and dynamic voltage/frequency scaling (DVFS) throughout the chip, and the combination of hardware policies with operating system (OS) software interaction.

While advances in circuit design and process scaling have enabled higher levels of integration in multi-core SoCs, Kosonocky showed that another limiting factor must now be considered—device packaging. The Llano APU requires six separate power supplies, including two high-current supplies. Designers can’t just add more supplies, he said, because multi-layer packaging is typically limited to only four power planes of thick high-current metal.

Aside from the cost impediment of adding more layers, package and chip designers simply run out of space. Each power layer requires its own decoupling capacitors to suppress supply noise. These chip capacitors are mounted on the package during manufacturing, and they consume available space with surrounding keep-out areas. Also, whenever another VDD is added the impact is multiplied by the increased share of package resources that must be dedicated to the VSS return path.

With packaging constraints now limiting power delivery to the number of cores that can be supported in an SoC, designers are looking to circumvent the problem by bringing external voltage regulators on-chip. Voltage regulators fall into two classes—switching circuits that use capacitors or inductors to boost and scale voltages, and linear regulators. Switching converters are generally preferred for their higher efficiency, but they require large amounts of capacitive or inductive energy storage. New solutions for power management will require more sophisticated analog circuit designs, possibly combined with additional process steps to build higher capacity passive components that are compatible with nanometer scale CMOS.

Intel, meanwhile, is investigating the use of inductive “buck converters” for on-chip voltage regulation, according to Donald Gardner, principal engineer at Intel Labs. Inductors are commonly integrated into RF ICs for wireless applications, but the current carrying capacity and inductive density of such structures is inadequate for power circuits. By adding magnetic materials to a standard CMOS process, engineers can increase the inductance of copper interconnect that is typically used in power busses. On-chip integration of a switching voltage regulator enables the use of circuit techniques to increase frequencies by more than 100 times over off-chip devices, which reduces the total inductance required by a factor of 1,000. This makes a single-chip solution feasible, and also offers the benefit of providing much finer resolution for dynamic frequency-voltage scaling, because the output of a buck converter is a function of its duty cycle.

The magnetic materials that Intel is evaluating include CoZrTa (cobalt, zirconium, tantalum) and NiFe (nickel-iron). Gardner said that regardless of the material, physics limits the gain in inductance that can be achieved by coupling a single layer of magnetic material to a wire to only two times, which is insufficient. Building structures that completely wrap wires in two magnetic layers, as his team is doing, is more complex but yields inductance gain that is much higher—theoretically up to the increase in the added material’s permeability.

Figure 1 - Researchers at Intel Labs have added magnetic materials to a 90nm CMOS process to build integrated switched-inductor voltage regulators. (source: “Integrated Inductors with Magnetic Materials for On-Chip Power Conversion”, 2011 Hot Chips Conference)

Striped inductors (rather than spirals) are the “Holy Grail” of voltage converters, said Gardner, because the application of a magnetic field during the deposition process inevitably creates orthogonal “hard” and “easy” axes. The hard axis has the property of saturating too quickly, but laying an elongated stripe in the easy direction takes full advantage of the increase in inductance. By wrapping a thick copper wire with two layers of CoZrTa, and sealing the sides with magnetic vias to prevent flux leakage, Intel has seen inductance increases of more than 30 times compared to air-core inductors. Intel’s research has progressed to the prototype stage, with a 48-core test chip containing 8 on-chip voltage regulators that the company has distributed to researchers for further investigation of new power management techniques.

It is unclear how much additional cost would be incurred by adding magnetic materials to a fabrication process, but capacitors are an intrinsic component of CMOS transistors and are commonly used for analog/mixed-signal circuits and on-chip power supply decoupling. Elad Alon, of the University of California’s Berkeley Wireless Research Center, has explored this alternative.

In SC (switched-capacitor) DC-DC converters, Alon noted that efficiency is limited by conductance density, or the amount of current (or power) delivered to a load for a given voltage. A DC-DC converter could be built as a replacement in the same area as a typical decoupling capacitor, which he estimated to occupy about 10% of a chip, so that no additional cost would be incurred if the regulators delivered at least 10 times the power density that their loads consumed. A typical processor was estimated to consume about 1 watt per square millimeter, but the payoff would be even higher in a lower power mobile device, which typically has 10 times lower power density. The Berkeley Wireless Research team implemented a 32nm CMOS SOI (silicon-on-insulator) test chip to test their concepts, achieving about 80% efficiency at 86 watts per square millimeter—close to the goal of 1 watt per square millimeter for a processor SoC.

Figure 2 - Researchers at UC Berkeley's Wireless Research Center have proposed incorporating switched-capacitor DC-DC converters in a 3D IC configuration, to supply power over tha area of a processor SoC. (source: “Fully Integrated Switched-Capacitor DC-DC Conversion”, 2011 Hot Chips Conference)

Higher capacitance per area yields higher efficiency in SC converters, and losses in the bottom plate parasitic set the maximum efficiency that can be achieved. The use of dense trench capacitors, such as in DRAMs, has been shown to offer the potential of about 90% SC regulator efficiency. Alon proposed that SC voltage regulators could be integrated into about 10% of the area of a DRAM die, and used to supply the power in a processor-memory 3D IC package. Alternatively, because the power regulator circuits can be built in older, less-expensive process technologies, a dedicated converter chip could be stacked and connected through TSVs (through-silicon vias) to distribute power over the entire area of a processor die.

By Pallab Chatterjee
Power became the driving discussion at several major events last month.

The global cries for energy reduction, which have been mainstream since the early 1970s on the political level, have now moved to being real economic realities for component and systems suppliers. Chipmakers are finding that lower power makes good economic sense—lower cost of packaging, lower cost of ownership of the products, higher reliability and, most importantly, the differentiation in power reduction methods is resulting in a lower cost of sales for the products as it is increasing the customer retention.

Once a methodology is selected for the chips, it is carried through to the board, then the system and eventually the software that runs on it. This makes the cost of changing the power method very expensive and typically keeps the customer on multiple generations of hardware and components from the same suppliers under the same software umbrella.

The Hot Chips conference featured several dramatic network and multicore server products that all had enhanced power management. The power management formally was multiple rails (I/Os and cores) and sometimes a thermal shutdown. The new systems are pervasive to the point that architectures are created with equal attention paid to power management and data throughput. The features shown were multiple power supplies, variable power voltages, block-based shutdown and turn-on, new circuits to minimize turn-on/turn-off, alternate clock tree distribution systems, lower power PLLs and clocks, and even new logic methods.

Fulcrum presented a 1 billion packet/second frame processor, which ended up being a case study for the applicability of non-synthesized sequential logic or asynchronous design. The logic structure, while known in the past, has never been implemented in such a large-scale application before, and the results included not only better performance but a power envelope that was task-acceptable.

Similarly IBM, Intel, Tilera and Cavium presented next-generation many-core designs with performance targeted at application needs over the next 5 to 10 years, but with power profiles at levels similar to chips of many decades back. The general rule is that power per transistor in these designs is less that 100 times what it was five years ago.

On the system side, data centers are the driver. Dell addressed the issue of power reduction for its servers by not just swapping components, but also re-qualifying the systems to work at extended temperature ranges. This means peak air temperature can be as high as 113 degrees Fahrenheit (45C) for its servers without sacrificing performance or warranty. This increase from 80 degrees Fahrenheit means there is no need to provide chilled air to cool the machines. The cost of the environmental air is generally equal or greater than the cost of the energy to run the servers.

To keep the component power down, these servers use new 30nm DDR3 DRAM from Samsung, which are now down to operating at 1.35V from 1.8V. The reduction in the power supply, and the reduction of geometry to make the devices, provides higher performance, higher density and an overall reduced power envelope. Google has noticed that by using virtualized machines and high DRAM on its servers it can eliminate the power from rotating media and go to mostly high-memory machines. This architecture systematically drops power at the data center level by double digit percentages and provides an increase in performance. The performance increase allows for the implementation of new features such as “instant search” while a user is inputting the full search field.

Facebook, which is new to the game on hardware, took a fresh look at power and started not with the chips, the memory or even the board, but with “how is the power getting to the computers?” It was able to provide a 12% to 15% reduction in power by looking at and redesigning the power supply input (408V to 24v signal path) and eliminating the UPS in its servers. This is a new area of high-power and high-current design that companies need to think about and look at. Facebook also ended up changing the board designs for the base compute server modules. Information on the Facebook approach and other areas to address the power can be found at OpenCompute.

Power as defined by the EDA community, which is “dynamic peak power in active mode,” as well as in idle mode, multi-mode and transition, and even infrastructure, will all play key role in next-generation low-power design.

The rationale behind Intel’s new book and why the company has taken its current approach.

By Ed Sperling
Philippe Magarshack, group vice president for technology R&D at STMicroelectronics, sat down with Low-Power Engineering to talk about some of the fundamental changes ahead in how SoCs are designed, built, how they perform and what steps can be taken to speed time to market.

LPE: What do you see as the biggest changes ahead?
Magarshack: One is the sheer size of the ecosystem and the relationships you will need to have moving forward. We are already dealing with this at 28nm. At 20nm, we see this is as a tremendous challenge. We are not alone. The competition has to deal with this, as well. We have the size to justify moving to 20nm, and 14nm in the future. We also have a network of foundries, not only for manufacturing but also for process R&D, and we are able to do some of that process R&D internally. When you look at the holistic cocktail of components needed to move forward, this is very challenging. But we are also one of two players that can actually take advantage of that.

LPE: Who’s the other one?
Magarshack: Intel. Even though they are coming from the high-end microprocessor market, they are certainly very serious about moving toward systems on chip and lower power. They aren’t there in terms of low power, but they are very focused. There is also R&D among big established players.

LPE: Where does stacking of die fit in?
Magarshack: There is a lot of buzz about stacking of die and TSVs. We are not quite there. But the trend toward system-in-package, which may include 3D stacking or side-by-side or some other combination, is very strong. We are using that for our set-top box and digital products. We are concentrating the pure digital design on 28nm and using to our advantage lower cost and more efficient processes for all of the analog systems.

LPE: What node is the analog in?
Magarshack: It’s typically 65nm, moving into 40nm now. Over time we have perfected the ability to integrate two die together in a package, minimizing things like power and crosstalk. The overall system cost is not the only benefit at the end. In terms of program management and schedule, you concentrate your teams on the digital and making the analog IP work. We see this as a benefit in time to market. We also can swap the analog out without having to wait for the digital die. So while we don’t see a strong market case for 3D stacking, at least for the next two or three years, we do have the capability in-house, as well as with our foundry partners, to make this happen. We already have prototypes. The first products we see will be DRAM with wide I/O.

LPE: What’s the perceived benefit of system-in-package with wide I/O? Is it better power management, better utilization of cores, performance, or cost?
Magarshack: The cost is not a driver. At this point it will be neutral, at best. The number one benefit is the memory bandwidth. When you have intensively used CPU cores or graphics engines, they need to access 1,000 or 2,000 bits of memory. This is something enabled by wide I/O. And in terms of total system power, for the same quantity of data being transferred from the DRAM to the chip, the wide I/O drivers are much smaller. The distance is smaller so the overall power of the system is lower. That’s the other big advantage. One technical change that has not been addressed is that, as a consequence of this intense activity on the DRAM and the processing engine, you have a temperature elevation. Removing the heat is one of the big issues. We are working to simulate the heat effects and to have ways of dealing with it.

LPE: What’s new, though? We’ve had memory on the chip, on the board, and now we’re playing it somewhere in the middle.
Magarshack: We may be able to remove some levels of cache. That improves the system response in case of interrupts. The size of the DRAMs also is increasing at the level of Moore’s Law. We have not been able to take advantage of all these bits and DRAM except through the I/Os, so for me wide I/O is a potential architectural breakthrough. Within two or three years this will be on the table and it will be at the forefront of SoC technology.

LPE: What’s the big hurdle going forward? Is it the hardware or the software?
Magarshack: We have come a long way in optimizing pieces of the hardware and the software. There is still more that can and should be done in terms of validating the software before the hardware comes out. We also have come a long way in virtual prototyping where we can boot the operating system and debug the device drivers before we develop SystemC models for the IP, or a combination of hardware emulation of the other IPs. Once we get silicon, we can plug it in the board and boot the OS within hours, and have significant applications running within days. After that, applications can run in real time before we find problems that need to be fixed. But we can take advantage of the silicon as soon as it comes out and go into production soon afterward. We still have to wait between 6 and 12 months for software bring-up and testing of software in the customer’s environment. To me that has to be shortened even further.

LPE: Will 2.5D allow some of the software to be re-used, as well?
Magarshack: If you have an adequate digital chip and you need to add another interface, you may only have to touch one device driver.

LPE: Will this be available from other vendors or will it still be ST developing the software, hardware and IP in-house?
Magarshack: We do see this as a differentiation for us. We have applications ranging from GPS to set-top boxes and WiFi, and we are able to bring in the hardware as well as the software part. There are millions of lines of code developed for systems on chip. We do most of that internally, but we are looking for and finding external partners, as well, for things like device drivers. We also are looking at what open source can bring us. This is easing the burden of software development. But the integration goal is a differentiation, and we will not hand off this function to an outside partner.

LPE: Will you have a standardized way of building and packaging these kinds of chips?
Magarshack: Yes, and we are one of the few that have the breadth of applications from consumer to auto to wireless. We are taking the approach that business units within ST are exchanging IP, both hardware and software, among each other. We have IP in our GPS group and they are moving IP into wireless. WiFi expertise is moving toward automotive. We definitely are doing these exchanges. For this exchange to work, we are working on internal IP standards so you can plug it in and re-use it. We have the SPEAr (MPU) family, where we have processor cores and GPS or other modulator IP, encoders and decoders. This can use an undifferentiated block that can be configured by the customer. They can put their own proprietary IP or then can ask us to provide it.

LPE: So to some extent you’re breaking your products down as platforms and subsystems, as well as lots of other IP?
Magarshack: Yes, and this is not just the hardware IP. It’s hardware and software.

LPE: Is it a combination of cost and speed to market that’s driving this?
Magarshack: Time to market is the most important.

LPE: What happens to your ecosystem? Does it grow or shrink, and does it get tighter?
Magarshack: We tend to have deeper and stronger relationships with fewer partners. We have moved to become part of the Common Platform alliance. We work with IBM, as well as the foundries of silicon, in addition to our internal fabs. We have developed intense relationships with these companies. We also need to have a strong relationship with the back-end assembly partners. Each part of the supply chain has to be extremely reliable and committed and focused. We need tight delivery dates across the entire food chain.

LPE: Any changes in materials that will be used?
Magarshack: Right now we are moving forward with a differentiated approach. We are building on top of the bulk CMOS. At 28nm we are moving forward with fully depleted SOI. We believe this will bring a very strong advantage for us of higher performance at the same voltage or lower power. We are now moving to take advantage of this with our partners.