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Posts Tagged ‘Jasper Design Automation’

Low Power News: October 18

Sunday, October 20th, 2013

Jasper announced the availability of their Security Path Verification App this week.  The app makes it easier to specify your security paths and exhaustively verify them.  With Halloween coming up, you might also enjoy a few scary stories about what can happen when security isn’t verified.

Researchers at the University of Washington revealed several hacks that enabled non-drivers to control vehicles.  For example, they were able to program a vehicle to turn off all the lights at speeds above 40 miles per hour, and that’s just for starters.  For all the details, check out their paper.

It’s also been shown that internal medical devices like insulin pumps and pacemakers can be hacked.  In a bizarre twist, the hacker, Barnaby Jack, who did some of the leading work in this field was found dead a few days before he was to present new results at the Black Hat conference.

If your low power device is going into a harvested energy application, you might be interested in Alta Device’s solar energy solutions that are currently being applied to unmanned aerial vehicles.  The solutions have a power to weight ratio of roughly one watt per gram!

Researchers at the Université Paris-Sud are working on photon based thermal transistors that can gate the flow of information communicated via heat.  One potential application of these devices is the control of MEMs devices.  For a summary of their work see the MIT Technology Review arXiv blog, and for the undiluted, unabashed original paper, look here.

For this weeks pure science read, phonon based circuits, (not to distant cousins of the heat transistor mentioned above), utilize temperature biased superconductors as detector technology in the search for dark matter.  You can read all about it in Roland Clarke’s doctoral dissertation [pdf].

Sticking to our emerging theme of health-related products and MEMs devices, check out this announcement from ST that their MEMs accelerometer is enabling technology that will help detect when sports participants may have been hit hard enough to cause a concussion.

Finally, ARM and SuVolta have been working together to build Cortex-M0 processors based on  on SuVolta’s DDC transistor technology.  Their initial results are showing:

50 percent lower total power consumption at matched 350MHz operating speed
35 percent increased operating speed (performance) at matched power
55 percent increased operating speed when operated at matched supply voltage

Verifying Security Aspects Of SoC Designs

Thursday, August 8th, 2013

This paper presents Jasper technology and methodology to verify the robustness of secure data access and the absence of functional paths touching secure areas of a design. Recently, we have seen an increasing demand in industrial hardware design to verify security information. Complex system-on-chips, such as those for cell phones, game consoles, and servers contain secure information. And it is likely that the presence of this information makes providers vulnerable to unauthorized access to secure data. The potential business loss, direct and indirect, is large, and verifying whether the secure information can be leaked is hard to achieve with conventional RTL validation methods. The security requirements are not easily expressible by regular SVA assertions; therefore, it is not practical to achieve validation with standard formal verification tools. Jasper’s Security Path Verification App (SPV) is part of a wide spectrum of apps we provide for design and verification domains. SPV provides a comprehensive solution to the security path verification problem. With SPV, it is convenient to specify the security paths and perform an exhaustive verification based on our special path sensitization technology, automatic connectivity abstraction, path divide-and-conquer search, and by leveraging the comprehensive core formal engines and usability features of the JasperGold platform. Jasper security path verification has been successfully used by various customers in the SoC domain, confirming the impact of Jasper’s solution and technology roadmap.

To download this white paper, click here.

Where Should I Use Formal Functional Verification?

Thursday, July 11th, 2013

With innovations in formal technologies and methodology, the benefits of formal functional verification apply in many more areas. Although a generic awareness of where formal functional verification applies is useful, understanding the “what” and the “why” leads to greater success. Clearly, if we understand the characteristics of areas with high formal applicability, we can identify not only which blocks are good candidates, but also what portions or functionalities of the blocks will give the greatest return on the time and effort invested. In recent years, we have come to realize that although we can apply formal to entire blocks, it can be more valuable to apply formal partially within blocks by choosing the functions that have the highest return. This paper will aid the reader in understanding where, why and how to apply formal for the highest return.

To download this white paper, click here.

Verifying Security Aspects Of Designs

Thursday, June 13th, 2013

This paper presents Jasper technology and methodology to verify the robustness of secure data access and the absence of functional paths touching secure areas of a design. Recently, we have seen an increasing demand in industrial hardware design to verify security information. Complex system-on-chips, such as those for cell phones, game consoles, and servers contain secure information. And it is likely that the presence of this information makes providers vulnerable to unauthorized access to secure data. The potential business loss, direct and indirect, is large, and verifying whether the secure information can be leaked is hard to achieve with conventional RTL validation methods. The security requirements are not easily expressible by regular SVA assertions; therefore, it is not practical to achieve validation with standard formal verification tools. Jasper’s Security Path Verification App (SPV) is part of a wide spectrum of apps we provide for design and verification domains. SPV provides a comprehensive solution to the security path verification problem. With SPV, it is convenient to specify the security paths and perform an exhaustive verification based on our special path sensitization technology, automatic connectivity abstraction, path divide-and-conquer search, and by leveraging the comprehensive core formal engines and usability features of the JasperGold platform. Jasper security path verification has been successfully used by various customers in the SoC domain, confirming the impact of Jasper’s solution and technology roadmap.

To download this white paper, click here.

Formal Verification Of Power-Aware Designs

Thursday, May 9th, 2013

Power reduction and management methods are now all-pervasive in system-on-chip (SoC) designs. They are used in SoCs targeted at power-critical applications ranging from mobile appliances with limited battery life to big-box electronics that consume large amounts of increasingly expensive power. Power reduction methods are now applied throughout the chip design flow from architectural design, through RTL implementation to physical design.

This white paper addresses the verification challenges posed by power-aware chip design, and how the JasperGold Low Power Verification App works with other JasperGold Apps to overcome those challenges. It covers:

  1. Power-aware verification challenges
  2. Power-aware verification requirements
  3. The limitations of traditional power-aware verification
  4. Meeting power-aware verification requirements with JasperGold Apps

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