By Ann Steffora Mutschler
Having a clear understanding of what reliability means for a particular low-power application can make a significant difference when it comes to communicating with engineering team members and customers. Is reliability simply a question of how long a device can run without errors? And what happens to reliability when power modeling, verification and other design techniques are utilized?

As Massimo Sivilotti, chief scientist at Tanner EDA pointed out, “These questions are complex, and there is no universally accepted answer to any of them.”

In general though, low-power designs involve both architectural and circuit design components and issues such as sub-threshold leakage currents, upsets due to substrate- and power-supply-coupled noise. Device parameter variations due to statistical process factors for deep-submicron devices become more acute as power levels fall. As such, state-of-the-art device models, up-to-date model parameters from foundries, and data-driven noise calculations become essential.

From Intel Corp.’s perspective reliability is more an attribute of the nature (or use model) of an application – whether it is low power or not. “For example, a low power smart phone application would define ‘reliability,’ both from device and user perspective, very differently than an equally low-power battery-powered medical device that administers medicines to critically ill patients,” said Pranav Mehta, chief technologist for Intel’s Embedded Communications Group. “Having said that, low-power designs do offer special challenges to designers. Balancing the need to lower the operating voltage to reduce power while trying to achieve competitive performance provides significant challenges in terms of process technology recipe, architectural tradeoffs, as well as design tool chain and methodology selections.”

The core of the problem
Diving down, technically speaking, Srikanth Jadcherla, group director of R&D for Synopsys Inc.’s Verification Group, noted that reliability in low-power design goes back to the fundamentals – avoiding permanent or temporary dysfunction of the device due to physical effects such as electromigration, self heating and rail/signal integrity failures. While these might have been overlooked before, the causes of the failures or in some cases the magnitude of certain phenomena can no longer be ignored.

“Some of these cause IC designers to adopt a certain power mitigation (or current mitigation) technique,” Jadcherla said. “Some of these are caused by what is done for power reduction. So, it cuts both ways. Specifically, as the industry heads into nanometer designs, current magnitudes are rising while wire cross sections are shrinking – increasing current density dramatically. This puts a lot more stress on the wires from an electromigration point of view and also from a heating standpoint. Ditto for leakage, which increases the average amount of current flowing through the wires irrespective of activity. This issue didn’t exist before. To combat these issues, IC designers have adopted aggressive techniques such as power gating and voltage scaling to opportunistically reduce the current draw.”

Docea Power, based in Moirans, France, looks at reliability in low-power design from the system perspective. CEO and co-founder Ghislain Kaiser said high power consumption affects reliability of electronic systems due to thermal dissipation and electrical issues induced by high-density currents.

There are multiple reliability issues related to high temperature including physical stress on the package, especially on die-attached material; transistor and interconnect deterioration; alteration of transistor switching time, hence timing hazards; thermal runaway risk when leakage current becomes significant; and high temperature that may require cooling systems such as a fan, which increase the risk of reliability if a failure occurs in the cooling system.

But, Kaiser noted, high-density currents alter electrical properties by causing such issues as electromigration of metals atoms along conductors; crosstalk, which degrades signal integrity; or a voltage drop along resistive wires. “This last point is particularly important when a low-power approach like voltage scaling is used. Lowering voltage allows you to reduce power consumption, but it increases the risk of going below the working point of transistors. The design work involves correctly sizing the voltage margin regarding the use cases,” he said.

Jameel Hussein, Technical Marketing Manager for Xilinx Inc.’s Power and Configuration Solutions reiterated that consideration must be given to thermal management at both the component and system levels to ensure that all devices are operating within their specified temperature range and to maximize overall system reliability.

“The device’s operating (junction) temperature is a function of the device power, its ability to transfer the resultant heat to the surrounding environment via the component packaging, and the ambient temperature of the system,” Hussein said. “Reducing the device power consumption, therefore, has two significant benefits. First, it lowers the system cost by enabling the use of less expensive thermal solutions to keep the device in its intended operating range. Second, reduced power means lower operating temperatures, which directly translates into improved component and system reliability.”

Added Hussein: “The temperature is a function of the power so if you can lower the power, you can lower the temperature of the actual device and its surrounding parts. Equation 2 is based on the acceleration factors between the two different devices in this example. If it is a difference of 10 degrees, in junction temperature, the equation shows that a device that runs 10 degrees less on a junction temperature will last twice as long as one running 10 degrees hotter,” Hussein explained.

Actel, which has been the low-power leader in the FPGA space, has focused part of its reliability argument around on-chip memory. Unlike other FPGAs, Actel’s use flash memory, which is less susceptible to single-event upsets caused by either terrestrial or cosmic radiation. And while that’s of obvious importance in aerospace applications, it’s also considered important in critical functions such as automobile powertrains because upsets often affect multiple bits at increased densities. That may be enough to shut down a chip permanently.

There are workarounds in circuitry and software for these kinds of problems, but they add more area to the circuitry and raise the overall power consumption to make sure there are no problems.

New techniques impact low-power design
With designs today utilizing techniques such as power modeling and complete coverage verification there are pros and cons as to the impact on the design.

By Ed Sperling

Chip companies that have been betting the future on better battery technology and holding off on the often painful process of reducing voltage should probably start rethinking their plans.

Battery technology is not expected to improve by more than 3% per year, and even that may slow. Compared with the chip side, there are no breakthrough materials such as halfnium or technologies like high-k/metal gate or air gap to enable design engineers to hit the reset button. In batteries, those minimal gains already are coming from advanced materials applied to the anode (-) and cathode (+) of the batteries, as well as significantly higher density for holding more charge in the same space.

The basic variables in a battery haven’t changed, though. It’s still a balance between capacity, cycle life and safety. Add too much capacity and weight becomes a factor. Use cheap materials and the batteries hold less charge over time. Increase the density too much and the batteries pose a fire risk.

New Materials

At the center of most batteries—at least the ones in common use—are the anode and cathode and an electrolyte solution. Typically the electrons move from a negatively charged anode to the positively charged cathode, and the electrolyte is used to store the electrons and prevent them from flowing freely. When the battery is recharged, the flow is reversed. (There are exceptions, such as electrolytic cells where the cathode is actually negative, but use of that technology is far more limited.)

By adding a ceramic layer on the anode, Samsung has been able to lower the resistance with a smoother surface while also improving safety. It also has doped the cathode with aluminum and other materials to prevent leakage. All of this comes at a price, though, and battery makers are keenly aware of how much the market will bear.

“We found that 33% of consumers are willing to pay $45 for an extra hour of battery life,” said Sean Lee, head of Samsung marketing and business development in the United States. “A 2.8 amps/hour battery produces 10.5 watt hours. A 3.0 amps/hour battery produces 11.2 watt hours. The higher capacity has allowed up to 11 hours of battery life for a netbook and 10 hours for a notebook, but actual time varies significantly depending upon applications being used.”

Samsung also is working on a high-density graphite anode and a higher-voltage electrolyte to reduce the amount of gas inside a battery. Lee said the company expects to shift to a silicon anode system in Q3 of next year, which will increase energy efficiency by up to 30%. It expects to reach 3.4 amps/hour by 2012 using that approach. But all of that won’t show up in longer battery life. By lowering the voltage slightly, cycle life—the overall number of times a battery can be charged—can be increased to 1,000 charges.

Panasonic is making similar tradeoffs with weight, according to Atsuo Yoneda, one of the company’s lithium-ion development engineers. Rather than increasing battery life, the focus in many applications is to reduce the weight by decreasing the number of batteries and making sure they hold their charge longer. The company is looking at a 3.6 amp/hour battery using a cathode made of lithium-cobalt-aluminum oxide, or NNP.

Shapes and materials

No matter what shape the batteries are in—either cylindrical or flat—the determining factor on battery life and the amount of power being stored is density and size. This is a basic area equation, and the shape of the battery doesn’t affect much.

Cost is another matter, entirely. Andy Keates, power sources enabling manager at Intel, said that prismatic cells are about 40% more expensive for the same capacity. One reason is the majority of those flat cells are custom sizes. They can enable the manufacturing of thinner notebook computers, for example, but they don’t change the battery life.

What’s more important, by far, is the material used in batteries, and there are a bunch. But the battery material expected to continue dominating the market is be lithium ion, which is the successor to lithium cobalt oxide, or LCO. As the chart below shows, there are a slew of technologies available. Lithium ion wins, however, on the basis of consistent power delivered over the longest period of time, versus a burst of power in the lithium iron phosphate.

Figure 1: While some exotic combinations have been developed and tested, none beats lithium ion for most portable electronics. (Source: Intel)

Other considerations for the future

One of the more interesting ramifications for battery technology is what happens when voltages drop inside of SoCs.

“Right now we’re seeing voltages as low as 2.5 volts,” said Keates. “It may go as low as 2 volts on the discharge curve, which leads to a tradeoff because voltage regulators may lose efficiency at less than two volts.”

That means that instead of just designing more power-efficient chips, now they have to include more power efficient regulators—and all of this because everyone was counting on batteries to improve enough so that battery life of devices could be extended. At this point in time, at least, it looks as if the faith in battery technology improvement was over-optimistic.

John Kern, vice president of product operations inside Cisco Systems’ customer value chain management group, sat down with Low-Power Engineering to talk about the company’s internal focus on reliability and what factors are causing the most concern. What follows are excerpts of that conversation.

By Ed Sperling
LPE: How does Cisco gauge reliability?
John Kern: The bulk of our revenue today is switching and routing products, which have high use of complex ASIC and microprocessor technology. We have a pretty extensive technology qualification process, as well as an individual component quality process. At a high level, we focus on robust design with solid margin, manufacturing, and to complement all of that are high-reliability components. We have one process for all right now, but we clearly see the need to differentiate depending upon the use case.

What’s involved in that process?
We have a preventive process and a reactive process. The preventive piece starts with partnering with the right suppliers, component selection for the [bills of material].

Does that require new attention to suppliers?
For the past five years, we’ve had a process to have very tight alignment across our critical technologies. So for our ASIC supply base, SERDES and PHY, we have deep partnerships with a handful of companies that we really rely on. We count on them to make investments in areas where we have need, and to do that is we have to be articulate about what our future holds. The payback for that investment—and at times it’s a significant investment—is we reward them with new business. This has borne a lot of fruit in terms of major technology transitions for us. It also has given us access to intellectual property that has enabled our products.

Does complexity from low-power designs change anything?
Nothing is radically changing in terms of complexity. We embed a lot of differentiation and intellectual property in our ASICs. Each technology node has its own transition. The transitions of late have not been as severe. As we move to 32nm and beyond, the complexity curve goes up. The issue around power and reliability is definitely more of a challenge, and it’s something we’re spending a lot more time and energy trying to get ahead of. We’re using techniques that emphasize power reduction in our ASIC designs that are probably commonplace in handsets, but they haven’t been as prevalent in switches and routers.

These are techniques like power islands and various on/off states?
Yes, multiple Vt’s and clock gating and making use of techniques to optimize for power. We had the luxury in the past of creating an architecture, and whatever the power below was it was acceptable and we designed the system around that. We’ve flipped that around now to where we start with a system-level power budgeting process that then drives down to the individual boards and the individual components.

Why is Cisco involved that deeply?
A lot of it begins with our customers. There’s also a green component. We started to do things like embed into our requirements documents, which define the deployment of the product way up front, more considerations around green and sustainability. These are things like considerations for high-efficiency power supplies for our ASICs and recycling at end of life, which are things we never built into creation of a new product.

Is it all ASICs, or are you moving into programmable chips and SoCs, as well?
In terms of the effect we can make on the system-level, it’s largely ASICs. We are also probably one of the largest users in the world of PLDs. But optimizing in those areas doesn’t make as big an impact on the system level as we can with ASICs. And as far as SoCs, the lines are blurring between SoCs and ASICs. The distinction we make there is we control the designs.

In the low-power world, there’s so much complexity that debugging the chip is becoming more difficult. Is that a problem?
Clearly. At every process node there is a shift. Given the complexity of the ASIC designs we have, this isn’t a new phenomenon. We’ve been dealing with power modeling, signal integrity, multiple Vt planes on the same chip, some of the interaction between substrate design and chip design.

What node is Cisco at?
We’re at 65nm. We’ve launched a host of 40nm designs. We’re on an unusual schedule, though. A lot of companies will launch designs at the lowest power process because they want the learning early and the ramp to volume is faster. We require performance and lower power, so it’s really a function of where the IP qualification is and how far behind the process schedule that is.

Does Cisco do its own designs?
We do most of the ASIC work ourselves. When we enter into an SoC joint development it can be shared, where pieces are done by third parties and our suppliers and pieces are done by us. In most cases we’ll handle the stitching of the chip. We’ve outsourced that a few times, but it’s pretty rare.

Cisco doesn’t have its own fabs though, right?
No. We outsource the fabrication to the traditional players.

Does that mean you’re subject to the more restrictive design rules?
Yes. We will engage with more traditional ASIC players that have something unique in their flow, but we’ll usually wrap the design around their constraints. We use their design rules and libraries and we follow those, depending upon the supplier we’re working with. A few years ago we did all the intellectual property and back-end work. We were our own fabless chip supplier. It played out well for a couple nodes, but when we used beyond 90nm commercially it didn’t make sense.

As you push into 32nm, do you foresee more issues with quality and reliability?
For reliability, absolutely. IBM is very fearful that the techniques that have served them well for predicting the lifecycle of a product will be affected by pushing the voltage curve. Our products should last for 10 years. We’re certainly aware of the risk and we’re working with our key suppliers to learn what we can as we venture into that node.

Will you necessarily move to the next node as quickly as in the past?
I think so. It’s hard to tell how much is an aberration based on the current economy or Moore’s Law. We are certainly starting fewer designs because we can make use of the technology to pack more functionality into devices. The devices are more complex. When you look at future nodes, though, the learning curve is going to get steeper.

One last question: How does all of this affect your make or buy decision?
We’ll use as much outside content as possible for the areas that aren’t differentiating. If we do a good job articulating to our partners what we need and it works for them, we’ll usually get the investment we need. There are some cases where we need a capability that’s core to us, so we’ll partition those off. As a company, we’re also starting to get into some adjacent markets. We’ll use whatever is available to get us into the market quickly. The benefit of leverage or cost or scaling that custom silicon can give you isn’t a factor for jumping into a new market.

By Cheryl Ajluni
Regardless of what you are designing these days, one fact holds true: Your design is only as good as the design tools you use.

Gone are the days when a design could be done on the back of napkin. Today, engineers require a complex ecosystem of interworking tools to guide them through the complex design flow. This is especially true when it comes to low-power design, as its complexity now permeates every aspect of the design flow, creating challenges that threaten to derail design closure at every turn. Here, automated design tools can play a key role in speeding the design process, selecting optimal low-power architecture and ensuring design closure.

The problem, of course, is low-power or “power-aware” design tools and flows are still in their infancy—a fact that poses a bit of a dilemma for designers. Not only do they need to figure out what type of power management and low-power design techniques to employ, but they must also determine which tool vendors support those techniques. Then they have to evaluate the possible tool options and make a selection. This can be a stressful and time-consuming process, especially when you consider the decision is critical to the success of any design project and, for that matter, to a company’s overall success and vitality. While there are no hard and fast rules for selecting the right tool, or the right vendor, there are a number of considerations—over and above a tool’s verified functionality—that engineers can use to help simplify their decision. Those considerations include:

• Cost. A tool’s actual cost and its available pricing options are important considerations when evaluating a design tool. Of course, a tool’s true cost is also impacted by its learning curve and overall reliability—both of which can affect downtime—and therefore must also be considered prior to making a tool purchase.
• Speed. While it may not always seem like a key consideration, how fast a tool operates can directly impact the designer’s time-to-market schedule as well as overall design costs and therefore should not be overlooked. Was it designed for multicore processors, or simply updated to take advantage of them?
• Support for Industry Standards. Using a tool built to emerging low-power industry standards, such as the Common Power Format (Cadence and Magma) or the Unified Power Format (Synopsys, Mentor and Magma), ensures that it will interoperate with a range of other design tools and flows. It is also smart to select a tool that can be used within industry-accepted reference flows such as the power-aware reference flow recommended by the Low-Power Coalition (LPC) of Si2 or Accellera, respectively.
• Ease of Use. Is the design tool easy to use? Does it require special training or low-power design expertise? Does it make you more efficient or productive? Does it support multi-language user interfaces for globally disperse design team members and are the user interfaces familiar? Is it easy to deploy, administer and maintain? Does it integrate well with other low-power design tools and design flows? All of these factors should be carefully considered during a tool’s evaluation.
• Flexibility. Is the tool flexible enough to accommodate changes in technology and can it adapt to changing business conditions—an especially critical question given the current state of the global economy? Can it support the needs of a globally-disperse design team with features like revision control and policy control for IP management?
• Customer Support. How responsive a tool vendor is to the designer’s support needs can be vitally important to the success or failure of your low-power design. Does the vendor provide quality documentation, training when needed or on site technical support? Does the vendor have proven expertise in low-power design? Such expertise may prove invaluable if you find yourself facing a difficult low-power design problem.
• Vendor Credibility. Don’t forget to verify the tool vendor’s reputation with other designers. If they have had trouble with the vendor, then chances are good that you will, too.

Design Tool Options
Despite the fact that low-power design tools and flows are still relatively new, there are a number of options to choose from. A sampling of these tools includes the following:

• Catapult C Synthesis and SpyGlass-Power, from Mentor Graphics and Atrenta, respectively. SpyGlass-Power is an RTL power estimation and reduction tool that is used to automate multi-level clock gating. Catapult is a high-level synthesis tool that offers a fast path to verified RTL from pure C++. New low-power optimizations enable the tool to thoroughly analyze a design to determine gateable clocks and build the appropriate logic. An interface now exists between these two tools that allows RTL output from Catapult to be handed off to SpyGlass-Power. Static and dynamic power estimates from SpyGlass-Power can then be fed back into Catapult C.
• Eclypse Low Power Solution from Synopsys. Eclypse is an integrated flow of tools, intellectual property and methodologies that allows designers to include everything from MTCMOS power gating, multiple voltages, dynamic voltage and frequency scaling. The goal is to dramatically simplify design and the increasingly complex verification portion of that design. Eclypse also includes clock gating, low-power clock tree synthesis and leakage power recovery. As you might expect, it includes UPF support, as well as support for the Low-Power Methodology Manual created by Synopsys and ARM.
• Cadence Low-Power Solution from Cadence Design Systems. Cadence’s Low-Power Solution is a CPF-enabled design-to-signoff methodology that makes it easy to incorporate low-power design techniques in advanced SoCs. It includes tools like the InCyte Chip Estimator for chip planning, Encounter RTL Compiler for logic synthesis, Encounter Conformal Low Power for structural, functional and equivalence checking; the Encounter Digital Implementation System for physical implementation, the Encounter Power System for power rail analysis, and Incisive Formal Verifier for formal property checking (Figure 1).

Figure 1. The Encounter Power System solution accelerates power optimization and signoff with a unified timing and power database. It can be used by front-end logic designers seeking high-quality early power and rail analysis, as well as by back-end physical designers looking for comprehensive signoff analysis and silicon-correlation.

• PowerPro CG and PowerPro MG, from Calypto Design Systems (www.calypto.com). The PowerPro CG tool reduces power by implementing sequential clock gating logic in the non-memory portions of an RTL design. PowerPro MG is a memory gating tool that automatically generates power-optimized RTL by taking advantage of the low-power modes available in on-chip memories. It works with PowerPro CG to produce the lowest power design possible.
• Talus Implementation System, from Magma. The Talus implementation system provides a fully integrated RTL-to-GDSII flow for high-performance, high-complexity, low-power nanometer designs. Talus Design and Talus Vortex are key tools in the system. Talus Design is a full-chip synthesis environment, while Talus Vortex is a physical design environment. Another tool, Talus Power Pro, works in conjunction with Talus Design and Talus Vortex to enable optimal power management throughout the flow.
• PowerArtist-XP and PowerTheater, from Sequence Design (now part of Apache). PowerArtist-XP is an RTL Design For Power (DFP) platform that features fully-integrated advanced analysis and automatic reduction (Figure 2). Using it, designers can achieve a 10 to 60 percent or more power savings. PowerTheater is a solution for RTL power analysis.

Figure 2. PowerArtist-XP enables designers to make intelligent design decisions that maximize power savings while minimizing design impact.

The Bottom Line
While designing for low power remains a difficult and complex challenge these days, appropriate use of low-power (power-aware) design tools can help simplify the process. Such tools will only become better and easier to use with time. Of course, selecting the right tool or tools is absolutely critical to a successful low-power design, perhaps just as critical as determining which low-power design and power management techniques to implement. While there is no set criterion to follow when making this decision, the considerations outlined above can serve as a guide in helping to make your decision that much easier.

Low-Power Design today changes its name to Low-Power Engineering reflecting a broader context for low-power issues that extend well beyond the confines of just design.

We discovered the need for this change several months ago—and many stories after launching Low-Power Design. Polls of our readers and our sponsors, which we conduct on a regular basis, showed our name was too narrow for the market we serve. While our focus is still semiconductors, the stories we write range from deep technology within the chips to the causes and effects of lowering power—everything from macroeconomics and politics to atomic physics.

Reducing the voltage in a device cannot be viewed in a vacuum. It can affect everything from the delivery of power within that device to a battery’s voltage regulators and the overall return on investment for a chip company—fabless or IDM. Increasing densities has marked effects on single-event upsets. And demands in the data center may have a significant impact on the overall utilization of a processor’s cores and the memory structures within or outside of those processors.

These issues have a significant impact on decisions about how many power islands need to be created, how many cores should be added to the chip and whether they should be homogeneous or heterogeneous, and how all of this affects throughput and leakage. These are complex engineering decisions, and they stretch from outside the semiconductor to deep within and back again. Designs have to be validated and verified, and everyone needs to understand the tradeoffs and the context in which decisions are made.

We fully intend to cover these subjects the way we always have, in keeping with good journalistic principles—unbiased, well researched, well written and fiercely independent. But we also need to provide a better description of what we’re all about. Check out our new url, too. (www.lowpowerengineering.com).

While the industry clearly agrees that power modeling is a necessity for next-generation semiconductor design at the transaction level, what is lacking is a standard way to exchange power models. Low-Power Design talked with David Hathaway, Senior Technical Staff Member at IBM Electronic Design Automation and Nagu Dhanwada, Senior R&D Engineer and Team Lead for Chip Level Power Analysis Tools in the Electronic Design Automation group of IBM’s Systems and Technology Division to discuss power-aware design and power modeling.

By Ann Steffora Mutschler

LPD: What are the most critical issues you are dealing with in terms of low power design?

David Hathaway: In addition to what we are doing here, both Nagu and I are involved with the Si2 Low Power Coalition. I am the Chair of the Technical Steering Group, and Nagu was Chair of the Flows group (which is now on hiatus) where he worked with Jerry Frenkil at Sequence Design. Both of us work in the Modeling Working Group.

One of the key things that is very important in power-aware design (and I hate the term ‘low-power design’ because IBM is designing some servers that use a lot of power and it is very critical to be power-aware and to minimize that power as much as you can, but you can’t quite call them ‘low power’) is that the largest opportunities one has for reducing power are really early in the design phase at the architectural level when one is doing high-level design. I think it is important, therefore, that tools and modeling techniques and modeling languages be able to support making design decisions and doing design analysis and estimation, and what-ifs, in the design phase.

If you talk to people in the industry you’ll find that most people do that, but they do it off on the side in spreadsheets and things they’ve cobbled together themselves. One of the key things we are trying to do with the Low Power Coalition with the Modeling Working Group is to extend existing standards so that they can be useful at these higher levels of design.

LPD: Are you making progress there? What’s the current work like?

Hathaway: It’s always slow when everyone who is involved has a day job and is also working with the coalition. But we have come to some agreement on some of the key issues – not all of them certainly—but some things that we think are important like being able to support non-mutually exclusive power states in models, and having somewhat more flexible ways of parameterizing power models than are available within the Liberty spec.

LPD: To make the shift to architectural level design, what kinds of changes need to happen within design groups?

Hathaway: I think a lot of them have done it, even informally. One of the important things is to try to connect the early design phase to the late design phase. You’ll find that in a lot of cases it’s done with different tools. You transcribe things from a spread sheet, for instance, that you use from early on to the later design. But uou may not keep your early design estimation spreadsheet up to date so you end up with disconnects. Anyone who is doing power-aware design is already thinking about these things. It’s just difficult to do it very formally and it’s difficult to do very much analysis. Nagu has done some work in the past in terms of doing power modeling for Power Architecture, so he has more experience with doing that at a high level.

Nagu Dhanwada: It’s also target-design-dependent to a large extent. When you are going through a typical microprocessor-based methodology where you have previous generations, there are two things to consider. One is the kind of design you are dealing with. The second is the engagement model, specifically, when you are doing some sort of an ASIC for someone else who is going to consume it and who owns the applications side of things. There you are kind of limited in the applications you get in order to really optimize things and you don’t have that much control over what you are optimizing.

On the other hand, when you are doing more of a microprocessor base where a lot of it is derived from earlier generations you have control over the stack, which includes learning on it, but a lot of the methodology is fixed because you are coming with an n+1 generation design.

At least in the space in between, just as IBM licenses the Power Architecture, we try to promote the Power Architecture. With consortiums like Power.org you are kind of sticking together a design using existing IP, which is more of a bus-centric view. So there you have these early models [either internal or licensed] and along with it, we put in high-level power models to go along with these ESL models. Maybe 3 or 4 years back, when TLM was not a standard and there were no standard APIs and such, we were building on some initial models. Tying in a power model to a transaction level functional model was kind of ad-hoc. That was the approach we took when we were initially going ahead. Now, in the context of what David was mentioning about the whole modeling committee and such, where we started to work on it, that kind of started – even the whole notion of the modeling—from discussions Jerry (Frenkil of Sequence Design) and I had in the Flows Work Group (of Si2) where we were saying, ‘We are putting these power-aware flows together starting from ESL. Now, do we want a different kind of a power model for different pieces of IP or can we try to come up with a power model that can span across different levels of abstraction?’ That’s how the Modeling Work Group got started and why David came up with issues about the need for non-mutually-exclusive states. Those are initial things that came out of the working group.

At an early level, if you are really talking more of targeting the consumer electronics space where a lot of design is done with these pre-defined IP blocks and there are emerging standards at the ES level like TLM, I think it’s the right time to also formalize the power modeling aspect and hopefully extend some of the existing formats – like Liberty – to move it to the higher levels and make sure you can use those even at the ES level. It’s more timely now than before because on the functional modeling side, things have crystallized a lot – there are a lot more standards out there.

LPD: How long do you think it will take for the industry to decide on how to formalize power modeling?

Dhanwada: We’ve been doing things like TLM. It’s not TLM, but any processor designer at any company has these early performance models. Like power models, these performance models are typically at some point a spreadsheet. Later on they take their form of executable models. They might not be in System C but they are basically C with threads, and you model your whole architecture way before anything is out there. You also have proprietary simulators. There have been discussions on how you make such proprietary things talk with existing languages, like System C models. We’ve done some work on this—making these talk with System C and TLM, and what it takes and how you can use these models in a bigger context. Those performance models have always existed but we are still at the beginnings of the formalism, or the extensions to existing models, which are not necessarily tied to any language. For someone to be able to use these models there would be some mechanics needed.

Hathaway: I think there are three things that are important considerations as we start talking about introducing the formalism into this. First, we want some separation of concerns. What Nagu described was a situation in which the power modeling was embedded in the performance models. There wasn’t a clean separation of the power model from the simulation model and this is what people often do when they’re trying to do something very quickly – they push everything together. We would like to have separation of concerns because there are more and more things that people are interested in at the high level and you need some modularity.

Second, you need some continuity in the design. What people have typically done (and this is something that came out of the Flows group that Nagu was chairing) is you create your high-level model, get some answers. Then you sort of set it aside and start over from scratch at the lower level, and build something while looking at what you did before and hope you’re building something that matches it. There is no formalism for guaranteeing continuity. As I evolve one piece of my design, having a mix of high level and low level is difficult.

The third thing to realize about power, which is different from things like timing, is that it is used in many different ways. With delay models the rule is you go in, you get a delay. Maybe it is a statistical delay, maybe it’s not – there are things about what parameters are. Basically, you are saying there is a ‘from’ node and there’s a ‘to’ node. How long does it take for a signal to get from point A to point B? For power, you may be concerned about average power; you may be concerned about average power over short periods of time, over long periods of time that drive electromigration. You may be concerned about very local power. You may be concerned about electromigration of a particular via or wire. You may be concerned about overall chip power. Or you may be concerned about waveforms because there is transient A/C power grid noise that you have to worry about so you don’t just care about the power, you care about what the power waveform is.

A benefit, when you’re looking at power that we don’t always exploit in our current models, is that power is much more separable than delay. You can to a very large extent say, ‘This piece of my power came from leakage; this piece of my power came from A/C switching,’ and I can separate those concerns. It is useful to be able to give reports back to the user that gives them the sensitivities to these various things because the power is separable. We’d like to take advantage of that.

When you are talking about the architectural level, optimizing power – although there are some tools that may be able to help you a little – you’re basically talking about a designer decision process and unlike timing where there are millions of billions of paths, and you can’t possibly close them manually, you’re making high level decisions in power and its very important to give the designer feedback so that they can do their own pareto analysis and determine where to get the biggest bang for their buck. To do that, you need to understand the sensitivities.

LPD: Would you like there to be external tools that could be used internally?

Hathaway: I think the fact that we can’t do the things our designers want to do with external tools gives us a competitive advantage by doing analysis with these internal tools. I don’t think it’s the tools per se; I think it’s that we have certain capabilities. Particularly in our ASIC library, we have partnerships with other companies and we would like to be able to exchange IP more easily. We would like to be able to bring in IP that has power models, that has these properties that we think are important. For those reasons, we think it is very important and would be very useful to us to have industry standards, whether we are using our own tools or using vendor tools, so that we could at least have easier interchange and compatibility of IP.

Low-Power Design sat down with Richard Zarr, chief technologist for the PowerWise Brand at National Semiconductor; Jon McDonald, technical marketing engineer in Mentor Graphics’ design creation business unit; Prasad Subramaniam, vice president of design technology at eSilicon; Steve Carlson, vice president of marketing at Cadence Design Systems, and David Allen, product director for power at Atrenta. What follows are excerpts of that conversation.

By Ed Sperling

LPD: How important is it to be green?
Zarr: In the past, when our customers plugged something into the wall they didn’t care. They pushed the problem off. But with some of the legislation, people are starting to care. No system is ever loaded 100% all the time. Even data centers are not always busy. Typically 50% to 80% of the power is wasted. They’re running at high speed and consuming power when they don’t need to be. But they’re not doing anything about it because it’s adding complexity or it’s adding cost. You’re designing the hardware, but someone is taking that and using in ways that you didn’t design it.
Carlson: I wrote a paper on the effects of virtualization. One of the things they would do in data centers is offload the servers, but the servers would have to go into standby mode when they’re not being used. They didn’t stand-by very well because they were never designed to stand-by. An improvement in the architecture at the macro level would be a big benefit, but people aren’t doing that unless they’re forced to do it or unless it becomes a competitive advantage.
McDonald: Where people have been investing the time—in the handhelds and at the micro level and device-level optimization—we’ve squeezed a lot of benefit out of that. Things can be made better, but a lot has already been done. At the macro level, almost nothing has been done.
Allen: The great thing about the handhelds is they’re proof points that it can be done. There’s a lot of work going on in the networking companies now, but you’ve got to start at the IC level. Once you’ve got the infrastructure there, then you can start layering on energy efficiency in the lighting, the HVAC in the data center and controlling of peak power.
McDonald: Cisco did a study in 2006 where they determined that if they saved 1% on the power for a network router it was the equivalent of taking tens of thousands of cars off the street. But when you’re designing it, no one cares. They just want to get it out the door and meet performance.
Zarr: Education is a big thing here. Designers are not educated in the vehicles to reduce the power consumption in their designs. It hasn’t been a priority for them.
McDonald: It’s also the delayed benefit. It’s not a benefit to the designer or even the company making the chip.

LPD: If it came down to hitting a deadline for getting a design out the door or cutting power, what’s the likely response?
Carlson: In the case of a very large printer company, it’s getting the chip out the door—even if it ultimately costs more money.
McDonald: Power is not really what most people care about up front. You care about the economics. You care about power only insofar as it affects the economics.
Zarr: It may have more of an impact as we go forward.

LPD: What happens if we trim the margin in designs? Do we gain power savings?
Carlson: There’s incredible waste. If you look at design methodologies for front-end design teams, there was a 5% margin. Now it’s typical to see 20% to 25% margin. One company we’re working with is going to use a 50% timing margin on the design for a battery-operated application. You start to explain what the impact will be on the overall logic architecture and the response you get is, ‘I hadn’t thought of that.’ You need to look at timing and power together. That’s where the real increases in margin occur.
Subramaniam: Margin is an issue, but it’s even more than that. Today we’re overdesigning chips because we are designing for the worst-case scenario that may never occur. So how do we take advantage of the process itself? You need to monitor the chip and lower your voltage accordingly. You’ve designed the chip for the slow corner, but you know that in normal conditions the chip is going to work much faster.

LPD: We’ve been adding cores and power domains on a regular basis. Now we’ve got a bunch of this stuff. How do you manage all these pieces?
Allen: You need to start at the architectural level. You can’t retrofit designs on the chip. There are a small number of power architects who can do this. They understand what the tradeoffs are, and from an EDA perspective you have to arm them with the right tools.

LPD: How small?
Allen: At ST there might be four. At TI there might be a half dozen. Maybe that’s enough. You don’t need a whole new power architecture for each derivative. You need a power architecture for the first one, and then you may get 30 or 40 derivatives out of that. But can every small company afford to have one of those guys? No. But big companies do have this expertise.
Carlson: There are sources of expertise to bridge the gap.
Allen: With external expertise, there’s a question of how much the design team learns.
Carlson: It depends on how you structure the engagement. If it’s a turnkey operation, they’re not going to learn much. But you can also teach them how to fish.

LPD: Do we ever get to the point where it’s no longer economical to do this stuff?
Subramaniam: You can probably go quite low on voltage for digital logic. We had a customer running digital logic at 600 millivolts. They could afford to do that because the chip runs at a very low frequency. If you’re willing to go with low performance, you can go to very low voltage on digital logic.
Allen: We’re not quite at the end of this road. Another thing to think about is how much charge is in a battery. That’s not really going to change that much. But there is still a lot of potential for architecture at the high end of the spectrum. Those guys can probably learn a lot.
Zarr: Even architectures that scale frequency will find benefit.

LPD: Is there a limit to how far down we want to go down the Moore’s Law roadmap, though?
Subramaniam: There is definitely a tradeoff. Only those with high-volume products will be willing to go to the next step.
Zarr: You never know until the next materials come out. They’re just continuing with strained silicon techniques and SOI.
Subramaniam: There are still a lot of designs done in 0.25 micron and 0.18 micron today. TSMC has not retired a single process since its inception. People will be willing to go back to older nodes if it helps them, but it doesn’t really help with power because they consume more power.

LPD: How do more restrictive design rules affect all of this?
Carlson: That will drive a renaissance in architecture. The process guys will quit solving the problem for you, and you have to be more clever about everything. You can’t just say you’re going to use the next-generation LP process and think you won’t have a problem with it.
Allen: There have been a number of times where the design guys said, ‘Leakage is going to kill us,’ and the process guys said, ‘Don’t worry about it.’ Then it scales to the next generation and it’s something else. The process guys may save us, but they won’t be able to save us forever.
Zarr: Somewhere along the line we’ll have to change materials, whether it’s carbon or something else. Everyone’s trying to avoid making that kind of investment.

Low-Power Design sat down with Richard Zarr, chief technologist for the PowerWise Brand at National Semiconductor; Jon McDonald, technical marketing engineer in Mentor Graphics’ design creation business unit; Prasad Subramaniam, vice president of design technology at eSilicon; Steve Carlson, vice president of marketing at Cadence Design Systems, and David Allen, product director for power at Atrenta. What follows are excerpts of that conversation.

By Ed Sperling

PD: Some of the suppliers of IP have eliminated a low-power version because they assume everything will be low-power in the future. Is that the norm?

Allen: It’s a question of how much time the IP supplier has put into trying to reduce the power. There’s a large body of IP where it’s designed as one monolithic thing, but very often when it’s put into an SoC the whole thing can be shut off.
Zarr: A lot of the IP is on a block, so you cannot dynamically scale it down.
Subramaniam: Some of the IP also relies on a certain level of voltage. You cannot indiscriminately lower the voltage to lower the power. Analog blocks need a higher voltage for noise margin and all their special requirements. Memory is another one of those. Every process has a VDDmin associated with the bit cell. You cannot expect the memory to work below that VDDmin. At best you can split the memory into two power domains and have a power domain for the bit cell and another for the periphery. But these things make it more complicated. If all of this increases the complexity by 100% and increases the risk of not meeting the schedule, I’m going to be reluctant to implement it.

LPD: How real is the risk?
Carlson: A lot of the risk is perceived risk. Faraday did a study where they took out 20 chips of increasing complexity with some analog content mixed in. They found they were actually closing faster using some of the advanced automation techniques for low-power designs. Doing a big SoC is complicated, no matter what. Adding another power domain doesn’t double complexity. What people have to do in power grid design and analysis is already hard. You have these analysis loops and you’re specializing in power. There’s plenty of experience behind this to say, ‘It can get done and it can get done efficiently.’ It’s the people who haven’t done it who say, ‘ I don’t know how to do it and I don’t know what the impact is going to be.’ And by the way, it’s 2008 to 2009, and I’m not going to do anything that increases risk. No manager is going to put their program on the line with something they’ve never done before for an unknown benefit.
McDonald: My customers push that problem down to the implementation side. They’re worried about pulling enough of the system together to accurately characterize the workload. Using large blocks of IP is a good example. One of the customers we dealt with recently had a large graphics processor. They had designed it and it worked great, but they couldn’t use it in the SoC because it killed the power consumption. They didn’t have the modes available to control it and turn it off when it wasn’t needed. The guys who designed the graphics processor had no idea how this thing was going to be used. They needed to have the foresight to put in the controls to be able to turn it off.

LPD: So that graphics processor was being designed for multiple applications?
McDonald: Yes, and if it has multiple applications how it needs to be designed from a power perspective is completely different.
Carlson: I agree. You need to be overlay different power structures.
McDonald: If you can overlay those using the same core function and changing the power characteristics, that becomes very valuable. But the tools aren’t there to do that today.
Allen: The modeling languages aren’t quite there to do that today, either. An IP supplier may have in mind several different ways to configure the power strategy, but a user of the IP can’t come along and arbitrarily impose their own. They don’t have enough information about what the IP actually does. If analog is required to maintain a certain voltage, and a processor designer or IP supplier knows there are three different blocks that could be independently powered, they need to be able to present a menu of the available ways to configure it. Both CPF and UPF are starting to represent that as a list of possible configurations.
Carlson: It’s an orthogonal purpose. You may want timing constraints and power constraints to go hand in hand.
Allen: Right. So what are the possible different ways these things can be configured? The IP suppliers have been requesting this, and they’re driving these IP standards in that direction, but they’re not there yet.

LPD: Is there a minimum amount of battery life customers are asking for?
Zarr: There are two requests we see. It’s not battery life in particular. They’re looking for other things in handheld devices. One is thermal management, and they’re running out of vehicles to do that. Battery life is part of that. The other one we’re seeing, which is even bigger, is total power dissipation. In infrastructure types of applications, where there’s a lot of processing power, people are hitting the limit of how to get the feed out of the device or the current in. There’s also legislation being pushed for data centers to get power consumption down. They’re running out of simple approaches, so now they’re looking at architectural approaches to say, ‘What can we do to redesign what we’ve done in the past to lower the energy?’ One is frequency scaling or clock gating. What’s interesting is it’s not as much of an issue with the small handhelds as the larger power consumers.
Allen: The middle of the spectrum doesn’t care as much. It’s the low-power and high-power guys who care.
Carlson: What we see, irrespective of where they are on the spectrum, green is competitive. I haven’t talked to anyone doing 65nm or below who doesn’t care about power. Some of that can be mitigated just by going to a low-power process.
Allen: The corollary question is whether anyone would delay their tapeout if they didn’t meet their power budget. A lot of people say, ‘No.’ They’ll delay for timing, but if they had a 2-watt power target or a 10-watt power target and they knew they were going to miss it, they would still tape out.
Carlson: This is an area that really needs improvement, too—the way the specs get done. In timing we have to meet the specification. In power, it’s 50% or more. There’s a printer company that didn’t meet the envelope, so they added in a $1 heat spreader. That’s 50 million units, but when they got the chip back they found out they didn’t need the heat spreader, so they wasted $50 million. It’s overdesign. We used to have this in performance. Now we have it in power.
Subramaniam: People only think about timing and performance as their No. 1 goal. Power is never considered a primary goal in any design. We see the problems more on the high end of the spectrum. At the low end, most of these handles can be turned off, so leakage power is the problem. At the high end, you don’t have too many choices about turning off portions of the chip. In supercomputers, graphics accelerators and telecom chips, performance is the No. 1 criterion. Power is secondary.
Allen: The low-power design guys have been dealing with that. At the high end of the spectrum, they’re just starting to deal with green laws and the cooling problems in data centers.

Ludo Deferm, VP of business development at IMEC, the Belgian research house, talks about changes ahead at future process nodes.

By Cheryl Ajluni

The quest for low power in electronic devices is one that shows no sign of abating any time soon. Pressure for it comes from many different sources, such as the continual drive to pack more functionality into ever smaller, mobile electronic devices.

To try and maintain a decent battery life for today’s power-hungry “road-warriors,” engineers have to reduce power consumption. To achieve that, they must spend more time and care in choosing the components, materials and techniques they will employ to drive down power consumption. They also must look closely at the wireless communications protocols they choose to employ.

One protocol that has received a great deal of attention of late is IEEE 802.11n—one in a long line of standards to emerge from the alphabet soup that is the Wireless Local Area Network (WLAN). Its improved performance and enhanced reliability over previous WLAN standards is thought to be the critical component in finally enabling WLANs to function as predictably as their wired counterparts. It’s no surprise than that a recent study from ABI Research predicts that by 2012 shipments of 802.11n technology will account for a full 60 percent of the market. Today, virtually 84 percent of the WLAN market stems from 802.11 a/g technology accounts.

Unfortunately, as is typical with any new technology, 802.11n faces a slew of challenges. In the Wi-Fi enabled, battery-sensitive market, for example, a key challenge to 802.11n’s widespread proliferation is power consumption. Meeting this challenge demands an ultra low-power technology, but can 802.11n deliver the low power necessary to take the battery-sensitive mobile by storm? Let’s take a closer look.

802.11a, b, g…n?

Essentially, IEEE 802.11n is designed to enable Wi-Fi networks to do more, faster and over a larger area. Well suited for both enterprise and home networks, it has the potential to deliver up to twice the range and five times the throughput of traditional WLANs (e.g., 802.11a, b or g). To date, draft 2.0 of the 802.11n standard has been approved and forms the basis for Wi-Fi CERTIFIED 802.11n draft 2.0 products. Certification of such products began in June 2007 and is done by the Wi-Fi Alliance (www.wi-fi.org). The final 802.11n standard is expected in September 2009.

802.11n technology builds on previous 802.11 standards by adding 40MHz operation to the physical (PHY) layer (enabled in either the 5- or 2.4-GHz mode), and frame aggregation to the MAC layer. It is based on Multiple-Input-Multiple-Output (MIMO) technology, which employs multiple receiver and transmitter antennas to transport two or more data streams simultaneously in the same frequency channel. This allows MIMO to coherently resolve more information than possible using a single antenna.

Is low-power 802.11n possible?

While the use of MIMO gives 802.11n significantly increased data rates, its multiple transmit-and-receive chains also increase power consumption—turning MIMO-based products into potential power hogs and dramatically impacting battery life. That fact alone has raised many concerns. A full-featured 802.11n access point (AP) will typically consume much more power than a legacy 802.11a, b or g AP, although a device’s actual power consumption will depend heavily on the implementation and vendor involved.

To address this power concern, IEEE 802.11n has extended the power management capability of the 802.11 MAC to include the following mechanisms:

• Power Save Multi-Poll (PSMP). This mode is an extension of the Automatic Power Save Delivery (APSD) approach specified in the 802.11e standard for improved Quality of Service (QoS). With PSMP, the client schedules the frames that it transmits as the trigger for delivering downlink frames. This reduces the contention between clients and between the client and the AP, which in turn dramatically improves power conservation in the clients. As a dynamic method, PSMP immediately adjusts to changes in traffic demand by the clients using it. While this mode is often touted as a way for VoIP clients to save power, it is generally best used only in situations with relatively heavy traffic loads.

• Spatial Multiplexing (SM) Power Save. In contrast to PSMP, SM Power Save allows an 802.11n client to power down all but one of its radios and can operate in either dynamic or static mode. In dynamic mode, all but one of the client’s radios is turned off. The client can quickly turn on radios, as needed, when it receives a frame. After the frame reception is complete, the client can return to a low-power state by again disabling all but one radio.

  In static SM Power Save mode, the client behaves as an 802.11 a or g client by turning off all but a single radio. The client’s AP is notified that the client is operating in the static single-radio mode and that it must send only a single spatial stream to the client until otherwise notified.

  802.11n also specifies an optional power save mode—Dynamic MIMO Power Save. This mechanism essentially allows 802.11n devices to dynamically change the number of transmit-and-receive chains that are active when traffic loads are light, such as by downshifting from 3×3 to 1×1 MIMO.

  The wave of 802.11n products

  By employing the mechanisms previously specified, low-power operation of 802.11n is possible. Of course, it doesn’t end there. Today, 802.11n Draft 2 chip developers like Atheros, Broadcom, RedPine Signals, and Qualcomm, just to name a few, are employing their own advanced techniques and process technology to minimize power consumption. Their continued pursuit to develop low-power 802.11n chips is bolstered by announcements like Apple’s use of 802.11n in its next-generation iPhone and iPod Touch models.

  The Apple devices are said to use the Broadcom BCM4329 wireless chip, a complete IEEE 802.11 a/b/g/n system (MAC/baseband/radio) with Bluetooth 2.1 + Enhanced Data Rate (EDR), and FM radio receiver and transmitter (Figure 1). The chip not only adds support for 802.11n features, including the ability to find and join 5-GHz networks, but also incorporates new power savings, such as advanced design techniques and process technologies to reduce active and idle power consumption and extend battery life.

  

  Figure 1. Broadcom’s BCM4329 wireless chip supports a variety of 802.11n optional features such as SpaceTime Block Coding (STBC), Short Gual Interval (SGI), A-MPDU aggregation, Block Ack, Greenfield, and RIFS. During WLAN operation, it achieves low active transmit and receive power consumption and ultra-low power in standby and idle modes.

  Perhaps one of the most significant low-power 802.11n offerings to come to market recently hails from Qualcomm (www.qualcomm.com). Its new WCN1320 N-Stream WLAN chip is the industry’s first dual-band 802.11n standards-based WLAN solution with 4×4 MIMO technology (Figure 2). Based on 65-nanometer CMOS process technology, the chip combines an embedded applications processor, media-access controller, digital baseband, radio-frequency transceiver, and system power-management in a single compact 12×12 mm package. With its 4×4 MIMO technology, it uses four spatial streams to distribute multiple streams of concurrent voice, video and data in either the 5- or 2.4-GHz radio bands. The WCN1312 chip incorporates advanced power-management techniques to minimize sleep, standby, and active power consumption.

  

  Figure 2. With performance of 600 Mbps, Qualcomm’s WCN1320 chip enables the distribution of multiple simultaneous streams of high-definition video, voice and data throughout the home. Sophisticated algorithms take advantage of the chip’s multiple transmitters and receivers to increase data throughput, extend range and overcome interference with a spectrally-efficient solution.

  Conclusion

  IEEE 802.11n is a technology whose time has now come. Expected to be fully approved later this year, it will open the door to a wealth of high-performance mobile applications like HD video, high-resolution imaging and voice over wireless LAN (VoWLAN). Realizing this goal will require special attention to reducing power consumption. Many of the current 802.11n Draft 2 chips achieve this goal through use of advanced design techniques and process technologies, but they also take advantage of the standard-specified power saving modes. Future chips based on the final 802.11n standard will need to follow suit. Doing so will help ensure the success of 802.11n, while also driving continued growth of the wireless connectivity market.