By Cheryl Ajluni

The quest for low power in electronic devices is one that shows no sign of abating any time soon. Pressure for it comes from many different sources, such as the continual drive to pack more functionality into ever smaller, mobile electronic devices.

To try and maintain a decent battery life for today’s power-hungry “road-warriors,” engineers have to reduce power consumption. To achieve that, they must spend more time and care in choosing the components, materials and techniques they will employ to drive down power consumption. They also must look closely at the wireless communications protocols they choose to employ.

One protocol that has received a great deal of attention of late is IEEE 802.11n—one in a long line of standards to emerge from the alphabet soup that is the Wireless Local Area Network (WLAN). Its improved performance and enhanced reliability over previous WLAN standards is thought to be the critical component in finally enabling WLANs to function as predictably as their wired counterparts. It’s no surprise than that a recent study from ABI Research predicts that by 2012 shipments of 802.11n technology will account for a full 60 percent of the market. Today, virtually 84 percent of the WLAN market stems from 802.11 a/g technology accounts.

Unfortunately, as is typical with any new technology, 802.11n faces a slew of challenges. In the Wi-Fi enabled, battery-sensitive market, for example, a key challenge to 802.11n’s widespread proliferation is power consumption. Meeting this challenge demands an ultra low-power technology, but can 802.11n deliver the low power necessary to take the battery-sensitive mobile by storm? Let’s take a closer look.

802.11a, b, g…n?

Essentially, IEEE 802.11n is designed to enable Wi-Fi networks to do more, faster and over a larger area. Well suited for both enterprise and home networks, it has the potential to deliver up to twice the range and five times the throughput of traditional WLANs (e.g., 802.11a, b or g). To date, draft 2.0 of the 802.11n standard has been approved and forms the basis for Wi-Fi CERTIFIED 802.11n draft 2.0 products. Certification of such products began in June 2007 and is done by the Wi-Fi Alliance (www.wi-fi.org). The final 802.11n standard is expected in September 2009.

802.11n technology builds on previous 802.11 standards by adding 40MHz operation to the physical (PHY) layer (enabled in either the 5- or 2.4-GHz mode), and frame aggregation to the MAC layer. It is based on Multiple-Input-Multiple-Output (MIMO) technology, which employs multiple receiver and transmitter antennas to transport two or more data streams simultaneously in the same frequency channel. This allows MIMO to coherently resolve more information than possible using a single antenna.

Is low-power 802.11n possible?

While the use of MIMO gives 802.11n significantly increased data rates, its multiple transmit-and-receive chains also increase power consumption—turning MIMO-based products into potential power hogs and dramatically impacting battery life. That fact alone has raised many concerns. A full-featured 802.11n access point (AP) will typically consume much more power than a legacy 802.11a, b or g AP, although a device’s actual power consumption will depend heavily on the implementation and vendor involved.

To address this power concern, IEEE 802.11n has extended the power management capability of the 802.11 MAC to include the following mechanisms:

• Power Save Multi-Poll (PSMP). This mode is an extension of the Automatic Power Save Delivery (APSD) approach specified in the 802.11e standard for improved Quality of Service (QoS). With PSMP, the client schedules the frames that it transmits as the trigger for delivering downlink frames. This reduces the contention between clients and between the client and the AP, which in turn dramatically improves power conservation in the clients. As a dynamic method, PSMP immediately adjusts to changes in traffic demand by the clients using it. While this mode is often touted as a way for VoIP clients to save power, it is generally best used only in situations with relatively heavy traffic loads.

• Spatial Multiplexing (SM) Power Save. In contrast to PSMP, SM Power Save allows an 802.11n client to power down all but one of its radios and can operate in either dynamic or static mode. In dynamic mode, all but one of the client’s radios is turned off. The client can quickly turn on radios, as needed, when it receives a frame. After the frame reception is complete, the client can return to a low-power state by again disabling all but one radio.

  In static SM Power Save mode, the client behaves as an 802.11 a or g client by turning off all but a single radio. The client’s AP is notified that the client is operating in the static single-radio mode and that it must send only a single spatial stream to the client until otherwise notified.

  802.11n also specifies an optional power save mode—Dynamic MIMO Power Save. This mechanism essentially allows 802.11n devices to dynamically change the number of transmit-and-receive chains that are active when traffic loads are light, such as by downshifting from 3×3 to 1×1 MIMO.

  The wave of 802.11n products

  By employing the mechanisms previously specified, low-power operation of 802.11n is possible. Of course, it doesn’t end there. Today, 802.11n Draft 2 chip developers like Atheros, Broadcom, RedPine Signals, and Qualcomm, just to name a few, are employing their own advanced techniques and process technology to minimize power consumption. Their continued pursuit to develop low-power 802.11n chips is bolstered by announcements like Apple’s use of 802.11n in its next-generation iPhone and iPod Touch models.

  The Apple devices are said to use the Broadcom BCM4329 wireless chip, a complete IEEE 802.11 a/b/g/n system (MAC/baseband/radio) with Bluetooth 2.1 + Enhanced Data Rate (EDR), and FM radio receiver and transmitter (Figure 1). The chip not only adds support for 802.11n features, including the ability to find and join 5-GHz networks, but also incorporates new power savings, such as advanced design techniques and process technologies to reduce active and idle power consumption and extend battery life.

  

  Figure 1. Broadcom’s BCM4329 wireless chip supports a variety of 802.11n optional features such as SpaceTime Block Coding (STBC), Short Gual Interval (SGI), A-MPDU aggregation, Block Ack, Greenfield, and RIFS. During WLAN operation, it achieves low active transmit and receive power consumption and ultra-low power in standby and idle modes.

  Perhaps one of the most significant low-power 802.11n offerings to come to market recently hails from Qualcomm (www.qualcomm.com). Its new WCN1320 N-Stream WLAN chip is the industry’s first dual-band 802.11n standards-based WLAN solution with 4×4 MIMO technology (Figure 2). Based on 65-nanometer CMOS process technology, the chip combines an embedded applications processor, media-access controller, digital baseband, radio-frequency transceiver, and system power-management in a single compact 12×12 mm package. With its 4×4 MIMO technology, it uses four spatial streams to distribute multiple streams of concurrent voice, video and data in either the 5- or 2.4-GHz radio bands. The WCN1312 chip incorporates advanced power-management techniques to minimize sleep, standby, and active power consumption.

  

  Figure 2. With performance of 600 Mbps, Qualcomm’s WCN1320 chip enables the distribution of multiple simultaneous streams of high-definition video, voice and data throughout the home. Sophisticated algorithms take advantage of the chip’s multiple transmitters and receivers to increase data throughput, extend range and overcome interference with a spectrally-efficient solution.

  Conclusion

  IEEE 802.11n is a technology whose time has now come. Expected to be fully approved later this year, it will open the door to a wealth of high-performance mobile applications like HD video, high-resolution imaging and voice over wireless LAN (VoWLAN). Realizing this goal will require special attention to reducing power consumption. Many of the current 802.11n Draft 2 chips achieve this goal through use of advanced design techniques and process technologies, but they also take advantage of the standard-specified power saving modes. Future chips based on the final 802.11n standard will need to follow suit. Doing so will help ensure the success of 802.11n, while also driving continued growth of the wireless connectivity market.

By John Blyler

Believe it or not, low power is not always a driving concern in chip design, especially when it comes to prototyping portions of a System-on-Chip (SoC). That is the finding of a recent survey conducted by Chip Design magazine. The survey quantified a variety of trends in the use of FPGA-based ASIC and ASSP prototyping.

Here’s the question that was asked concerning prototyping priorities: What was the leading decision in selecting your prototyping system? Almost a third of the respondents cited “flexibility and expandability” as their primary concerns in selecting an FPGA-based prototyping system (see chart below). Also high on the list of concerns was the completeness of the solution, lowest cost and best throughput performance. But lower power was not a big concern to most prototypers.

Is this surprising? Not really. Most engineers use SoC prototyping in FPGAs to reduce the number of chip re-spins due to functional and verification problems. Indeed, that “low power” even made the list is somewhat surprising. Believe it or not.

By Ed Sperling

Low-Power Design sat down with Walter Ng, senior director of platform alliances at Chartered Semiconductor; Brani Buric, executive vice president of sales and marketing at Virage Logic; John Sanguinetti, CTO at Forte Design Systems and Andrea Kroll vice president of marketing and business development at JEDA Technologies. What follows are excerpts of that discussion.

LPD: What will the differentiator be in the future?

Sanguinetti: We have to take as input designs that are relatively high level. Our customers tell us the higher the better. We spend most of our time in raising the level of abstraction. But we also have to be cognizant of what happens downstream. We don’t want to put out RTL that is junk. And it can’t just be acceptable to the tools. We want to put out RTL, for example, that can make dramatic improvements to power optimization. That’s true with any of the logic synthesis tools. But we don’t have very good visibility downstream, so we’re very reactive.

Ng: On our end, everything is about cost. Cost touches time to market and all the specs. We’re seeing much more widespread adopting of ESL tools. If you’re looking at power and selection of architectures, that can be most influenced at the system level. At the gate level, optimizing on power techniques, the wrong selection of an architecture can more than skew what kind of power you’re going to get. With more integration happening because of silicon’s capabilities, the more complex functions and the more important ESL should be. Getting from the algorithm level through system description, RTL and the physical implementation is a huge cost. The verification of each one of those representations is a huge cost. The more structured that approach can be, the better. Most of the leading edge of design is consumer applications, and these are extremely cost and power sensitive applications.

LPD: Why hasn’t ESL taken off until now?

Buric: It did. But there’s a difference between what has been used and what is commercially available. ESL has been adopted in one form or another over the last 15 years, at least. Most of those are internally developed tools targeted at a particular application. If you want to move from there to the commercial market, you have to make those tools very generic. That makes the problem more difficult to solve. But complexity of designs is going through the roof, so you have to start using these kinds of tools everywhere. If you’re not first-time right, you can lose your business or even your company, but you certainly will lose your market opportunity. It is now a must-have to make sure everything downstream matches your intent.

Kroll: One of the problems in ESL is the models are not of sufficient quality to estimate what’s going on in the technology later on. What is the power consumption, what is the area and what is the cost factor for the models. That’s the problem in the commercial market. You can’t make the tools broad enough and still use them for a specific task in an individual company for a specific application.

LPD: Does the number of models increase for each node?

Sanguinetti: That’s the way abstraction goes. We recognized we need a higher level of abstraction in ESL for the past 15 years, but it’s taken a long time to get to any kind of agreement about what it looks like. There are a number of approaches to it, which are largely overlapping. That’s what happened with SystemC. It took a long time before it became a standard. TLM is the same. There were a lot of ways of abstracting out interfaces. That’s why there are a lot of different models.

Kroll: They just specified TLM 2.0 last year.

Ng: As more folks come to adopt ESL and more is flushed out, this is part of a natural maturation of the process.

Buric: As this happens, you’re also going to see the rise of a second generation of ASIC vendors—eSilicon, Open-Silicon, Global Unichip. And due to design complexity, there will be an ESL signoff between design intent and design implementation if you don’t have a clear signoff.

LPD: Can ESL handle all the power islands that are cropping up in designs?

Kroll: I don’t think so. There are people already doing power analysis with SystemC and TLM 2.0. They are switching off components and making sure the dynamic power is captured properly. There needs to be more standardization on how to do it.

Sanguinetti: ESL can do anything. You can write lower-level code in your higher-level environment. It’s a bogus complain about ESL that you can’t do this or that. Maybe it’s as much effort to do it if you weren’t using ESL, but that doesn’t mean it can’t be done. In some cases, ESL hasn’t made your life easier—yet. But that’s where continuing work will be done.

LPD: Such as?

Sanguinetti: Power islands. Right now you put a module in one domain, another module in another domain, synthesize them and hook them up with an interface. Writing that abstract interface is work.

Buric: It becomes structural ESL. You have to partition the problem.

Sanguinetti: You want to be able to write code at a higher level, and what you take advantage of is the language’s expressability and the tools’ capability.

LPD: As we get to the next several nodes we’re facing restrictive design rules. Does that limit the demand for ESL?

Ng: Now that the flow is a connected flow, through RTL to physical, more and more people will be adopting it. They don’t have a choice. The challenge is creating a really good representation of the physical design at such an abstracted level. Even developing a synthesizer to put out good RTL good, dealing with the different interpreters and synthesis tools, is a challenge when it comes to power. Connecting that physical implementation is to the highly abstracted algorithmic world is difficult.

LPD: How do changes at the smaller geometries affect RTL?

Ng: From an RTL standpoint, not much. But it does affect the implementation of gates. We’re getting to the point where we will have to question what physical structures are allowed. We’re not saying they’re bad or good. But it will be a fairly limited set. From that to gate-level implementations that leverage those changes. I don’t know how you can comprehend that in a model. It’s more constraints on the physical implementation.

Wally Rhines, chairman and CEO of Mentor Graphics, talks about what’s changing in design, the effect of low power, and who’s going to be doing the most advanced designs.

By Ed Sperling

Say goodbye to fat design margins in advanced SoCs. The commonly used method of adding extra performance or area into semiconductors to overcome variability in manufacturing processes or timing closure issues has begun to create problems of its own.

While there was plenty of slack available at 90nm, adding margins at 45nm and 32nm disrupts performance or eats into an increasingly tight power budget—or both. And while this may seem like a relatively problem solving exercise, margins are to a design engineer what a safety net is to a high-wire acrobat. They allow engineering teams to get to market on time and on budget, with an incredibly small number of bugs considering the complexity of current designs.

Cutting margins means substantially more up-front modeling and much more work in figuring out where the variability is in new manufacturing processes. It also means potentially more restrictive design rules and less creativity at the very front end of Moore’s Law.

Different approaches

“At 45nm and 32nm, you can’t put a margin on everything because your performance would go to zero,” said Rob Aitken, a research fellow at ARM. “For the relationship between design and low power, there are two approaches being advocated. One is to do a better job quantifying the margins. Instead of putting a finger in the air and saying, ‘Let’s worst case this and worst case that,’ the solution is more, ‘Let’s actually look at data and figure out where the worst cases lie, look for correlations and relationships between the amount of timing slack we have and our verification extraction methodology. Maybe we can use a better extraction technique and shave off some of that margin.”

A second approach is a more adaptive one, where you know there will be some margins but you don’t know exactly what they are. “When you get your silicon you have adjustable parameters, whether they’re voltage or clock frequency or something else, that you can tune on a per-chip basis to boost up yield and achieve margin without necessarily putting it in the design,” Aitken said.

There are other approaches being advocated, as well. Bhanu Kapoor, founder of Mimasic, a consultancy in Richardson, Texas, said building work-arounds into chips such as classic fault tolerance is an acceptable option.

“We need to start learning to live with errors,” Kapoor said. “Margin-related issues will lead to errors and they will not function correctly at times. That’s where you have to bring in techniques like fault tolerance, where you have error correction. That is a very useful technique for low power, too, because you can work at lower voltages. There will be times when your critical path timing will not be met and you will have errors. Then you try to detect the errors, correct them and learn to live with them.”

Still others say there should be no workarounds. Vinay Srinivas, group director for R&D at Synopsys, said the solution is eliminating variability up front so there is less need for margins and far fewer errors.

“You need better tools, modeling and methodology,” Srinivas said. “Having these guardbands is not acceptable. If you were to guardband everything when the system wakes up you would have so much latency that you couldn’t afford it in the design. At 45nm and 32nm, you need more voltage-aware modeling.”

What works?

While companies such as Synopsys are pushing for better designs up front, the majority of designs will still include some design margins—at least in the short term. Hamid Mahmoodi, assistant professor of electrical and computer engineering at San Francisco State University’s School of Engineering, said there are times when each approach works.

“There is a lot of variability and unpredictability in designs,” Mahmoodi said. “Adding margins is the easiest way to solve that. You can make the design faster than expected by adding in additional biasing or something to cope with the variation in processes. But adding margin means more silicon area and more power. There is cost in terms of additional sensors or voltage regulators. Even corrective action requires overhead.”

Sometimes, in fact, adding margin can be the most cost-effective solution.

“In a given process, which is more cost effective depends,” Mahmoodi said. “If the variability is small, adding margins is the most cost effective solution. When the variability is large, and there are variations is process parameters and voltage, then adding margins is too expensive. At that point, it’s best to consider fault tolerance schemes or adaptive asset calibration methods to make the design more reliable.”

Conclusion

The bottom line is that even the experts disagree on what route to take when. That largely will be up to the design teams working under intense deadlines to get their chips out the door. But at each new process node, there clearly is less room for adding margins and more restrictive design rules for getting chips to yield properly and perform as planned within power limits defined by customers. And if you think it’s hard at 45nm, it’s only going to get more difficult over the next couple nodes.

By Ed Sperling

Low power used to be an afterthought in semiconductor design, and it almost was never a consideration in verification or manufacturability. But at each new process node, the number of power considerations goes up as the line widths go down.

To begin with, there are two basic types of power. The first is dynamic, which has been a consideration ever since batteries were added into devices. Dynamic power is the amount of power needed to do something useful with a device. And while components continue to get more efficient, those improvements typically are measured in the single digits.

Much bigger gains come from more efficient use of those components, particularly turning them on and off. At 130nm and above, turning off components was a “nice to have.” Below 130nm, it’s a requirement because of static power consumption—the current that leaks out of transistors that are left in the “on” state when they’re not being used.

The effects are easy to see when nothing is done at different nodes versus remediation with power shutdowns, as the following diagrams show:

Source: Mimasic

Bhanu Kapoor, founder of Mimasic, a Richardson, Texas-based consultancy, said during a recent speech that there are several interdependencies in static leakage that need to be considered.

“Leakage has a linear relationship with the supply voltage,” Kapoor said. “Leakage also has sub-threshold and gate-tunneling components, which have been growing exponentially with respect to the threshold voltage. Gate tunneling is being addressed with high-k materials and metal gate technology. The sub-threshold component is still there.”

Old problem, new tricks

Addressing static leakage is absolutely essential at 90nm and beyond. Kapoor said that at 90nm, leakage amounts to 20% to 30% of the total power consumed by a device, and techniques such as clock gating have no impact on static leakage. The only thing that really has an effect is shutting down portions of a chip or device that are not in use. So while a cell phone also has a camera, games and music, the only function that has to be on all the time is the ability to receive calls.

“There is a strong dependence on power with respect to voltage, and there are several techniques to use voltage to get a handle on power consumption,” he said. “A typical application like a cell phone has times when you use applications and there are long periods of standby when the device is not in use.”

Voltage also can be scaled for a specific function or application of a cell phone, for example, something that is beginning to make its way into heterogeneous multicore design. The basic idea is that you have a fixed power budget for a design, and you can better utilize that budget if all the cores aren’t drawing the same voltage. A phone needs more power than the camera, for example, so the core design can be changed to reflect that. Similarly, logic and memory for one function may be significantly smaller than for another.

Verification challenges

But even after a design team has done everything to minimize power consumption, the problem is far from solved. Verification, which accounts for 70% of the time spent in chip design, gets significantly more complicated as each of these new tricks is implemented. There are now a lot of different power states in the design, and there are voltage islands that can be on, off, or somewhere in between. Intel, for example, has seven sleep states in its core processors.

“What all of these techniques did was introduce voltage as a variable in the design process,” Kapoor said. “Verilog and VHDL, or any other language, don’t have a notion of voltage as a variable. You need additional description to go along with the functional descriptions to describe the power management architecture. That has led to a power architecture description format that is being standardized through IEEE’s 1801 working group. But in terms verification, now that you are powering down different regions of the chip you need to isolate those and retain values when you are powering down. When you are going from one region to another you need to level shift these signals. And all of these things need to be validated.”

He said that requires protocols for shifting things on and off, potentially changing the design to allow for verification, and some formal assertions for when one area powers down and what effect it has on other areas of the design.

Pallab Chatterjee & Ed Sperling

A French startup has a new angle on power analysis, targeting the solution to the design task of energy in an electronic system as a systematic binding element rather than just a static parametric element.

The founders bring experience from the wireless, semiconductor and software arenas to the task of “energy management” for electronic design. This takes the form of both power and thermal design analysis and planning. Their methodology is based around a proprietary product they have created called ACEplorer, which is an Abstract Concept of Energy exploration tool.”  

Basically, the flow requires the designer only to have a concept of the power state flow for their design (on state, off state, sleep state, power down state, video off state, etc.). They do not have to have any detailed RTL. Using a VCD interface, and a traditional XML data format, a designer can describe the models of the IP blocks of the system and the design functions for each of the power states and create an appropriate UPF model that incorporates all relevant energy information. This includes active power, passive power, thermal power and the power associated with the drivers connected to the external load/package/cable. The resulting compact models are then appropriately temperature modified and used in power simulations to determine the device level power performance and spectrum of the product.

For new devices, high-level XML-based traditional models are used and input, and the new UPF model are created. The methodology can be also used for characterization of existing devices as well as for migration and spec creation for derivative IP.  For the derivative flows (typically on similar technologies such as a G process to an L process) the flow would be to create a detailed characterization model, run the power simulation (SPICE level), then modify the values to in the model to reach the new goal and create the spec for the new block RTL.

Unlike some of the other tools on the market, as the models are high level, and work up at the power state, it does not matter the if the blocks are digital, memory, I/O, analog, display, board level, power regulation or SIP.  This method allows for the detection of thermal run-away, prior to it being a disruptive event in an incompatible set of state changes.

Started as a spinoff from the Grenoble ecosystem project, which has since evolved largely into an STMicro ecosystem, DOCEA founder and CEO Ghislain Kaiser said the real advantage is to be able to do power analysis that takes into account more parameters up front to make estimates more accurate.

“What these tools allow you to do is make estimates that are more accurate and explore an architecture that will be optimum,” said Ghislain. “That decreases the need for

additional margin.”

As it is a new paradigm, it will be interesting to watch and see the adoption cycle in the mainstream semiconductor industry. DOCEA rolled out the first version of its product at the end of last year and says it has several customers already and has received positive adoption of the methodology from several key clients in the portable design space.

Low-Power Design sat down to discuss green technology and the future of low-power design with Rich Kapusta, Actel vice president of marketing and business development; Tom Quan, TSMC senior director of EDA and design service marketing, and Brani Buric, Virage Logic executive vice president of marketing and sales. What follows are excerpts of that conversation.

By Ed Sperling

LPD: Is there a shift in how customers are using technology. For example, are they sticking with the traditional processor and working around that or are they shifting that approach?

Kapusta: Customers are now deciding what’s the right tool for the job. Is it RTL gates or some embedded processor. They’ll pick the right one for them.

LPD: What process node did that start at?

Kapusta: For us it was 130nm, because that’s where we began offering embedded processor cores. It does change the EDA side significantly, because now designers are either RTL or embedded guys, and they don’t bridge both.

Buric: That was the problem 20 years ago with synthesis versus engineers who did schematics manually.

LPD: Are there any new materials entering into these chips?

Quan: In general, the industry is looking at high k/metal gates for the next process node. But at the end of the day, the question is what you’re going to charge the customer. You still can achieve performance, power and area using bulk CMOS. High k/metal gates will be more expensive. That’s why when we announced 28nm, we said will have both versions available—one with high k/metal gates and the standard version.

LPD: What’s the tradeoff?

Quan: One is a traditional curve at 45nm and 40nm. The high k/metal gate is better for leakage and it offers higher performance.

Kapusta: We’re big believers that non-volatile cells are the way to go for programmable structures, and you’ll see more and more people move away from SRAM. Right now, it’s flash. But at some point the road for flash will end and there’s all kinds of stuff that may come after that.

LPD: What’s Actel’s next node?

Kapusta: We haven’t figured that out. But we need to get as much time per node to recoup our investment, which is why we went from 130nm to 65nm. I would imagine we’ll be at 65nm for quite some time.

LPD: How does IP change at different nodes?

Buric: At 90nm we have specialized IP for high performance, high density and low power. When we moved to 65nm we realized that all designs are low power so we have killed a separate low power version. All of our IP has low power features that users can disable if they want. We have minimized the number of components, but we have added low power as a ‘must have’ to everything we are doing. As we move to new processes we also realized that yield is another issue that we have to consider. So instead of just area, power and performance, we now have added yield to that. We characterize all our components under different yield assumptions. If you have just one component on the chip, you can assume certain power versus performance behavior. If you have thousands of those components on a chip, you have to be more conservative. We have added that kind of complexity. At 28nm and 22nm, we anticipate adding new modifications that will help on the manufacturing side.

LPD: How long does it take for process variability to stabilize?

Quan: The traditional wisdom is the more chips you make, the more stable the process. At 130nm and 90nm and 65nm, those nodes ramped up fast and we learned a lot. We have a lot of activity at 65nm. With DFM, there used to be a bunch of rules at the beginning. Most of those rules have been relaxed or eliminated. We don’t have to run a lot of stuff we did at the beginning. The same will happen at 40nm. The number of design rules that need to be followed during tapeout is large, but over time there won’t be as many required by the end user. Our process does mature.

LPD: Does it change from one node to the next in terms of the time it takes?

Quan: In the past, all we had to worry about was the performance of the device and the leakage. The next thing you have to worry about is whether you can manufacture it in large volume, which is the DFM space. Now, most of DFM relates to how you lay things out. If you let the designer draw anyway they want, potentially the DFM issue will increase as you go down. You need to be more restricted in the way you lay out stuff. Mostly you laid things out in one dimension for the lowest layer for the polygons, the diffusion, and metal layers one and two. That reduced the systematic random defect issue. We had to introduce that on the design side to make the process more reliable.

LPD: Is there more variability at future processes than in the past?

Kapusta: We’ve been at 130nm for some time. It’s very predictable. We feel pretty good about jumping into 65nm because it’s been running for some time. We’re just working on adding the embedded flash to the 65nm logic process that UMC has had in production.

Buric: For some of those, no matter how stable the process when you put more devices in a given area it increases the probability of variability. There are ways to control that with statistical modeling and statistical timing analysis. It is changing how we work with silicon.

Quan: The physical approach of doing designs is important. When we go down to 28nm and 22nm, timing and closure have to become a serious design practice. Right now, the corners are killing everyone. When you go to 40nm, there are so many corners it’s hard to manage them all. 

By John Blyler

Most engineers would agree that developing products that use less power requires a balance of integrated hardware and software implementation strategies.

The challenges extend beyond just hardware and software issues, especially when you consider domain-specific variables such as increased device intelligence and network connectivity. Low-Power Design sat down with Jonathan Luse, director of marketing for the Low-Power Embedded Products Division of Intel, to talk about these challenges and how they might be resolved.

LPD: Let’s start with the high level, domain-specific trend in embedded, low-power systems. What do you see?

Jonathan Luse: The trend is twofold. First, you have intelligence being added to all kinds of devices. Second, you have the continuing trend of connectivity. By about 2013 or 2015 we expect to see about 15 billion connected devices worldwide—everything from mainframes and servers to cell phones and embedded devices. Some of these embedded devices will be seen, but many will be unseen or in the background.

LPD: Define connected, intelligent devices.

Luse: An easy example is the navigation system in your car, whether it’s integrated into you car or a portable unit. One standard feature of these devices is the capability to connect with traffic monitoring systems. If the navigation device was a bit more intelligent and connected, it could reroute you based upon traffic optimization. That’s just one example of adding connectivity and intelligence to a device. Another example is in the energy delivery mechanisms for power. Alternative energy sources are interesting and will add new forces of power to the grid. But you have a huge infrastructure of existing power generation plants and manufacturing plants that consume electricity. Intelligent low power and connected devices could really help make that entire infrastructure more efficient. Imagine the scenario if each consumer had a smart power meter at their home that could communicate back to the power station. That way, these smart meters could tell both the consumers and power generators how the energy was being spent. Studies have shown that if consumers just knew where they were inefficient in their power usage—regardless of taking any action—they could reduce their electricity bill by 10%.

LPD: Many technology pundits talk about the coming sensor swarm—the increase in the use of sensors in all kinds of connected applications. Such applications would be well suited for a micro-controller architecture rather than a general purpose processor. How do you see the intelligence being distributed in such a system?

Luse: I would see basic intelligence being added at the sensor level too, which might aggregate into a programmable logic controller (PLC), a computer used for automation of electromechanical processes. At the controller level you might need an embedded processor, like the Atom. Depending upon the number of interfaces or inputs/outputs, you might have some physically distributed activities that require a more traditional processor. Then you might have more massive programmable controllers that require a lot of power, so they would go to a dual- or quad-core processor. In fact, a lot of companies that use PLC technology have been using Intel inside their medium and high-end systems for the more intensive processing tasks. But we’ve never given them a 5-watt solution to put into their entry-level PLC applications. Now, with the low power embedded processors like the Atom, they have an entry-level product.

LPD: This is not the first time that Intel has entered the embedded market. What makes this time different?

Luse: Intel has had processors in the mobile, desktop and servers markets for a long time. One example in the embedded space is the xScale, which is a low-power device. The main difference now with the embedded Atom family is that it’s instruction-set compatible with the rest of our embedded roadmap. One thing I’ve heard our customers say is that the xScale is good if it’s used in an isolated application that doesn’t require scalability. But many companies want a good, better, and best strategy. From our perspective, the Atom is the good, the Celeron is the better and the Core-2 Duo is the best for these clients. The benefits that they see are design scalability, architectural scalability and software scalability. They can go top to bottom of their own software stack to include the right features at the right level of product offering and only have to do it once. These customers don’t have to manage multiple architectures, since the Atom and higher processors are all based on Intel’s IA architecture.

LPD: Are these software stacks changing? A lot of legacy software has been remarkably inefficient because it was developed to run on a general-purpose operating system that then runs on a general-purpose processor.

Luse: To answer that question, I need to explain my day job. I’m director of marketing for the Low Power Embedded Products Division, which includes the Atom processors. But in that role, I’m also responsible for the embedded software group. From that perspective, I see that the big trend in the last five to six years has been from proprietary to off-the-shelf systems. Let me explain. When times were good, companies were vertically integrating their stacks, their solution from hardware and hardware-aware Basic Input/Output Systems (BIOSs) to software operating systems and applications. Companies developed it all – homegrown and proprietary. After a while, though, the companies realized that they weren’t getting any real value for the middle portions of the stack – the BIOS, OS and some of the middleware. In addition, these companies understood that a proprietary OS or BIOS wasn’t where their core intellectual property resided, as opposed to an open OS or BIOS. The strength of these particular companies was in the creation of acceleration software that made the existing hardware run faster, e.g., packet processing or a user interface. From this trend I realized that the middle portion of the stack – from silicon to applications – largely moved from proprietary, homegrown OSs and BIOSes to commercial off-the-shelf versions that had become “good enough.” Today, few of these companies use proprietary OSes. Instead, they’ve moved from a completely vertical integrated stack to an off-the-shelf model.

LPD: Your example of the GUI developer or packet processing raises questions about whether we’ll soon see a multicore version of the Atom. You could run your embedded legacy code on one core and the new code – say, a GUI – on the other core.

Luse: Well, I’m not here to launch any new products, but consider Intel’s direction as a company. We’ve gone multicore with everything over time, as a way to extract more performance. The reason is the way that silicon substrates work. If you dial up the last 15% of a processor’s maximum frequency, then you basically double your power consumption. Conversely, if I dial back my frequency by about 15% of the maximum, then the power drops by about half. Further, if I have a second core, then the power decrease almost pays for the second core. Now I’m at 170% performance versus 100% performance for approximately the same power. I’m not trying to tip my hand, but you can see the direction of Intel’s processors. Multicore architectures are a very good way of getting more performance for the same power out, which makes for a very good low-power story.

San Francisco—It’s no surprise that different sections of the electronics supply chain see the low power challenge from different perspectives. But the similarities and differences are changing as the low power problem becomes the driving force behind today’s mobile devices.

At the recent Globalpress event, Portable Design’s editor in chief John Donovan moderated a panel on low power: “Portable Power Management – Dodging Moore’s Law?”

Donovan said low-power design faced a turning point in 2008, thanks to three converging issues: The growth of portal devices, power consumption costs at data centers, and changes in process technology, which are the result of Moore’s Law. A 45nm chip contains more than 400 million transistors, which equals a lot of power generation and dissipation.

Wally Rhines, CEO of Mentor Graphics, talked about system-level power issues in a speech at the event. The focus of this panel was at the chip level, which has a 20% to 50% impact on the overall board-package lever power budget.

One Theme – Differing Views

The first question addressed by panelists involved emerging trends in low power designs.

Richard Zarr, chief Powerwise technologist at National Semiconductor, said a new generation of user interface technology combined with the consumer’s desire for higher bandwidth content will drive the need for increased local processing power in mobile devices.

User interface technology has come a long way since 1983, when Motorola introduced the DynaTAC 8000X – the first FCC approved mobile phone (see Figure 1). This phone boasted an alpha numeric LED screen that was a single row in length. Since that time, phones and other mobile devices have gotten smaller while the displays have gotten larger. The larger, higher resolution displays are needed, in part, to support the customer’s desire for multimedia data such as MP3 music and video streams.

“By 2014, Cisco forecasts that 64% of mobile traffic will be video,” said Zarr, adding that other high-bandwidth applications would include online gaming, where cloud computing will move most of the intensive processing tasks to the server while pushing video to the personal mobile devices. All of this will increase the need for local and remote low processing technology.

Figure 1: In 1983, Motorola introduced the DynaTAC 8000X – the first FCC approved mobile phone. (courtesy of Wikipedia)

Instead of the typical power-to-clock equation for chip power, Zarr used the energy dissipation equation to show how energy (power given a certain amount of delta time) is really a function of process and temperature variations, plus aging and the clock frequencies of the device. This lead-in was tailored to National’s Powerwise Adaptive Voltage Scaling (AVS) products, which addresses – you guessed it – process and temperature variation, plus frequency via voltage scaling. AVS touts energy efficiency by eliminating the need to pre-identify voltage levels via voltage lookup tables for various performances modes.

Next up was Bruno Kranzen, Ultra-Portable product line director for Fairchild Semiconductor. He built upon Rhines’ keynote comment that energy storage technology innovation was at a standstill. According to Kranzen, this means power innovation has to accomplish more while using the same power afforded by today’s batteries. That “more” includes 5.0 GBits/data rate support for USB 3.0 interfaces that are so common on today’s mobile devices. It also means support for 10 megapixel image sensors in today’s cameras, multicore processors, 3D MEMS sensors for touch-screen displays and 8 RF bands, to name only a few of the power consuming technology requirements.

All of these power-intensive features must be met with battery technology that has improved at a snail’s pace, as Rhines pointed out in his keynote presentation. He observed that innovation in lithium-ion battery capacity had essentially stalled, with capacity improvement increasing by less than 5% per year (Figure 2). So how can the electronics industry meet the demand for increased feature sets that use today’s battery technology?

Figure 2: Innovation in lithium-ion battery capacity has stalled. (courtesy of Mentor Graphics)

Kranzen answered that question by taking a system view. He explained that while Fairchild is a chip company, it is collaborating with partners in both the operating system and applications space. He emphasized that merely making energy-efficient chips is not enough. Instead, software designers must be engaged to meet the demands of low-power system. Fairchild’s Mobile Power Systems platform is one way to achieve this end, by utilizing power management hardware components that are tightly integrated with the operating systems and even applications that run on a mobile device.

The final panelist was Pravin Madhani, general manager of the Place and Route Division at Mentor Graphics, who represented the EDA side of the low power equation. Madhani spoke in unison with the other panelists in terms of the need for a systems view for the design of low-power devices. Specifically, Madhani defined the system process as starting with an architectural-level specification that takes into account PCB, package and component-level design. Each step in this process affords different opportunities to impact the overall power budget for a device.

Taken together, the total impact can be significant, with potential power reductions of more than 50%. Mentor’s low-power platform addresses each of these design stages, from optimal hardware architectural design through power integrity and predictability at the PCB level through the capture of the designer’s power intent at the component level via the Unified Power Format (UPF).

Devil is in the details

So what are the real-world applications of these ideas?

Mentor’s Madhani shared his experience with a recent multicore design project in which a graphics company couldn’t meet power and performance requirements for two graphic engines on one core. The solution required moving to a smaller process geometry, in this case 45nm, which afforded significant power savings but with slightly lower performance. The key in this design was clearly understanding the tradeoffs of each scenario, as well as being able to simulate and verify all of the hundreds of operation modes for the chip.

Fairchild’s Kranzen challenged the drive toward increasing number of cores. He said transistor leakage was the culprit, which drastically increased the level of static power drain for multicore designs at the low process nodes. Leakage current is the result of the small amount of current that continues to flow even when the transistor is off. This challenge must be address by device-level physicists and material ngineers.

Conversely, having just a single core is often impractical, since that core must run so fast to perform all of the processor-related tasks that it consumes unacceptable amounts of power. So designers must find the “sweet spot,” which is the optimal number of cores needed to balance the power-performance constraints of their design. One solution is to turn-off unneeded cores. Such an approach requires close operation between the cores and the systems operating system, explained Kranzen. Cores could be turned off by the software kernel, but that activity must be closely coordinated with the Real Time Operating System (RTOS).

National Semiconductor’s Zarr agreed that part of the low power problem must be solved at the transistor device level, probably with improvements with high K dielectric materials and designs. But the bigger challenge is to clearly understand the goal, the intention of a given design. He cautioned that just “throwing transistors at the problem,” as with multicore and/or lower process node technology, is not the best approach. Instead, a top-down architectural solution is needed. One outcome of such an approach would be to divide different blocks of system functionality into different voltage islands to better manage the power usage of the system.

So is the ESL-to-RTL design problem still the biggest challenge for low-power design teams? Madhani believes that most people have a better handle now on low power design, thanks to improved architectural power modeling and better tools to verify the numerous power modes for a given operational scenario.

Kranzen stressed the need to run software models, as well. These models would execute the drivers, OS and application-level code to provide a gauge of related power consumption. Running both hardware and software simulation or co-simulation would provide a system-level view of the overall system power usage.

Finally, Zarr believes the best way to address the top-to-bottom low power design is with an energy tax on the operating system, in other words, placing a real emphasis on energy management of the entire hardware-software system.

The bottom line: The power problem is too big for a point solution. Only a system-level approach that incorporates the co-simulation, co-design and co-verification of both hardware and software will be sufficient to meet the demands of lower-power electronics. This is hardly a revelation, but the growing consensus by EDA and semiconductor companies of the importance of software design in the hardware equation looks encouraging.