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Posts Tagged ‘low-power engineering’

Cutting The Power

Thursday, February 11th, 2010

By John Blyler
A flurry of activity in the last quarter of 2009 suggests power—and particularly low power—is the major focus of this year’s design starts.

What a difference a year makes. This time last year it was nearly impossible to decipher the power trends in chip-level architectural trade-off investigations (see “Chip Power trends Murky”) But this year the trends have more pronounced tendencies because there are simply more design starts. Recent analysis of cumulative data that track of architectural exploration of chip design projects – precursors to design starts, which now number more than 96,000 distinct investigations since 2005 – show a definite interest in specific power regions, namely; 0.25 watts to 1 watt, 1.5 watts to 4 watts, and even 5 watts to 15 watts. (see Figure 1).

Figure 1: Power ranges (in watts) that have been of particular interest to IP chip architects over the last four years. – Chip Design Trend (CDT) Report

As in last year’s analysis, the 1.5 watt to 4 watt range was still the most popular for architectural exploration. Assuming that last year’s trends in IP usage were unchanged through the year, most of these investigations were in analog and mixed signal (AMS) and digital core IP, followed by on-chip bus and off-chip interface IPs. Again, assuming no change in last year’s trends would mean that leading markets for these investigations remain in the communication and consumer electronic sectors.

Perhaps the most compelling overall trend is that “Total Design Investigations” collectively are at levels not seen since three years ago (Q1 of 2007). Another encouraging sign is that this activity is slightly broader than in was in the first quarter of 2007, when investigations rose above the 1,000 mark only briefly during January and February of 2007. Conversely, the 2009 investigations were above the 1,000 mark between August and October, and were also across several power ranges.

This increase in architectural-level IP exploration activity portents actual chip product availability within the next 4 to 12 months – just in time for the December 2010 holiday season.

Other supporting evidence of an increase in design start activity can be found from the just released report, which indicates that the “North America Semiconductor Leading Indicator (NoAm-SLI), a forward-looking composite index that forecasts six months ahead, on the average, business activity in the North America semiconductor industry rose in December 2009.” (see Figure 2)

Figure 2: “On the average, the leading index leads by six months sales. The index is continuing to grow.”

Both of these trends – the increase in architectural-level chip investigations and the upward semiconductor index – are welcome news to the EDA and chip industries.