By Ed Sperling

Low-Power Engineering moderated a panel featuring Bhanu Kapoor, president of Mimasic; John Goodenough, director of design technology at ARM; and Prapanna Tiwari, CAE manager at Synopsys. What follows are excerpts of their presentations, as well as the question-and-answer exchange that followed.

Bhanu Kapoor: There are two types of power you need to consider: Dynamic power, which is consumed because you are doing some useful activity, and leakage power, which gets consumed whether you’re doing something or not.

The dynamic power has dependence on switching activity, the frequency, the capacitance and the supply voltage. There are two components of leakage—sub-threshold and gate tunneling. Gate-tunneling is addressed by advances in process technology such as metal gates. Sub-threshold leakage grows exponentially with the decrease in threshold voltage. At 90nm it was significant, at 65nm it was equal to the dynamic power, and it grows from there.

If you look at the typical smart phone, it’s the same system-on-chip that is running different applications. These different modes of operation have different performance requirements. You can use different voltages to achieve those different levels of performance.

A typical power-managed SoC includes a power-management IC that provides different cores. One core can be a processor. And if it’s an ARM Cortex A9, there is power management in that core, as well. A second core might be for mixed signal, which potentially could require higher performance. And then this power controller, which is on all the time.

All of these power techniques have an implication on verification.

If you look at standby leakage, one of techniques is power gating, which is cutting off power to certain regions. If you don’t need portions of the chip to be on, you can completely shut it down. That is power gating. But that has an effect on performance, because turning on and off a function is a long event compared to a clock cycle. You need to sometimes retain the state so you can come up fairly quickly.

All of this has an effect on verification, as you can see from the following chart.

If you can do gate-level simulation, that is very helpful. You need input/ouput and power connected and you need to have appropriately modified your library definitions so power is one of the variables. With domain isolation, once you shut down you have to make sure you are not sending floating values to other regions. You have to isolate it to proper ones and zeros, which you can check with isolation gates using a rule-based checker.

If you have power in your simulation, a lot of rule-based issues can be addressed right up front. Over the years, simulation was not power aware. In the future, simulation will take a more and more important role. Simulation, by default, will incorporate power.

John Goodenough: We are verifying systems on chip. They’re large. They have lots of power domains to match all the application workloads that are going to be demanded on those devices. They have processors and software. Some of the domains are being switched on and off to meet the energy profile. They have virtually every technique available. The state space you’re trying to validate is therefore exploding by an order of magnitude.

One of the things we think about a lot at ARM is that it’s not so much the techniques that you can apply. It’s how you’re going to scale them to tackle these problems. There are lots of clever ways to validate, but not all of them scale effectively into workflows and onto your infrastructure. Power verification is not just about logical verification.

If you get a chip like the one below, you can mess it up in a lot of different ways.

Usually, you can fix it in software. But you also can mess up the connectivity between the power domains. If you get your level shifter or always-on buffer or retention register wired up wrong, it’s not going to work. It’s going to be D.O.A. on the bench. A lot of chip failures are being caused by the failure to verify the integrity of the power network.

That’s a non-standard piece of verification, particularly where that interacts with the logical function of the chip and you’re trying to measure the maximum in-rush current and the average in-rush current. If you’re switching domains on and off, what’s the power domain going to look like from an electrical perspective? Is turning one domain on and turning another domain off going to put the voltages on either side of a level shifter into a pathological state that will damage or degrade the transistors and the level-shifting buffer?

There are some very interesting cross-coverage issues between what is traditionally more of the analog verification space on the power network and the logical verification space. We need, when considering power simulation, to run abstracted analog simulations, SPICE-level simulations, and cross between the two.

Unfortunately, the explosion in power states is also increasing because of the number of software states or the number of field configuration states. From a verification standpoint, not only are you adding a multiplier due to power states, you also have things like a secure or non-secure state. Will they work when a chip is configured for a single package and pinout if it uses another package and pinout? There’s an explosion in these operating modes.

The other pressure we have is making sure you’re going to hit a given schedule. In looking at the power metrics it’s important to see how they can be applied into practical workflows and how you can feed performance metrics from wherever you are in the process back up into reporting and closure reporting. If you combine the need for those two, one of the things it leads to is enterprise scaling, both in terms of infrastructure to support the simulation and how you scale this across workgroups that are not co-located.

The other problem you face is that if you do all of the verification, you’re never going to get the chip out the door. You’ve got to have a verification plan and really narrow down which of the power modes are going to be pathological and which ones can be worked around in software. A major part of thes power verification is the integration of a VP of engineering risk-reduction play into a more mainstream verification practice.

We’ve come a long way in a lot of the techniques, but at the end of the day you have a block diagram that needs to be simulated. Today that block diagram consists of RTL and some way of describing the power network or the power intent and power state space of the design. You also have to support the verification IP and transactors. You need coverage across the RTL and the power descriptions. It’s not rocket science. It’s just a more complicated block diagram.

By John Blyler

A flurry of activity in the last quarter of 2009 suggests power—and particularly low power—is the major focus of this year’s design starts.

What a difference a year makes. This time last year it was nearly impossible to decipher the power trends in chip-level architectural trade-off investigations (see “Chip Power trends Murky”) But this year the trends have more pronounced tendencies because there are simply more design starts. Recent analysis of cumulative data that track of architectural exploration of chip design projects – precursors to design starts, which now number more than 96,000 distinct investigations since 2005 – show a definite interest in specific power regions, namely; 0.25 watts to 1 watt, 1.5 watts to 4 watts, and even 5 watts to 15 watts. (see Figure 1).

Figure 1: Power ranges (in watts) that have been of particular interest to IP chip architects over the last four years. – Chip Design Trend (CDT) Report

As in last year’s analysis, the 1.5 watt to 4 watt range was still the most popular for architectural exploration. Assuming that last year’s trends in IP usage were unchanged through the year, most of these investigations were in analog and mixed signal (AMS) and digital core IP, followed by on-chip bus and off-chip interface IPs. Again, assuming no change in last year’s trends would mean that leading markets for these investigations remain in the communication and consumer electronic sectors.

Perhaps the most compelling overall trend is that “Total Design Investigations” collectively are at levels not seen since three years ago (Q1 of 2007). Another encouraging sign is that this activity is slightly broader than in was in the first quarter of 2007, when investigations rose above the 1,000 mark only briefly during January and February of 2007. Conversely, the 2009 investigations were above the 1,000 mark between August and October, and were also across several power ranges.

This increase in architectural-level IP exploration activity portents actual chip product availability within the next 4 to 12 months – just in time for the December 2010 holiday season.

Other supporting evidence of an increase in design start activity can be found from the just released eForecasting.com report, which indicates that the “North America Semiconductor Leading Indicator (NoAm-SLI), a forward-looking composite index that forecasts six months ahead, on the average, business activity in the North America semiconductor industry rose in December 2009.” (see Figure 2)

Figure 2: “On the average, the leading index leads by six months sales. The index is continuing to grow.” Eforecasting.com

Both of these trends – the increase in architectural-level chip investigations and the upward semiconductor index – are welcome news to the EDA and chip industries.

By Pallab Chatterjee
Design partitioning for power in an IC is driven by which functions are on simultaneously. The new generation of “smart” power management chips introduces new constraints to the task.

Case in point: The new LP8725 from National Semiconductor. These chips have multiple DC-DC converters and both analog and digital low-dropout regulators (LDOs), with a common I2C interface for control and thermal management.

Single chip regulators mean that SoC designers have to account for peak power available, channel-to-channel matching on their power grids, data- and operation-dependent dropout on the various LDOs, and timing for the startup/shutdown of the power regulation that drives the SoC. The logic and ESL tools that work on lowering dynamic power by creating voltage islands, switched/gated power and reduced operating voltage levels make the assumption of stability and availability of these global signals. The IC tools work on the design considerations from the bond pad IN towards the logic and I/Os. And the new power management chips, due to their multi-function and multi-channel characteristics, make the design if the SoC external power source is part of the SoC design architecture.

Portable and multimedia designs have multiple modes of operation to extend battery life. The operations generally require several high current paths (600mA+), some mid-current paths (250mA+) and some low current paths. To accommodate these current levels, the SoC block partitioning needs to manage the peak current available with a tolerance, not just an IR-drop specification.

The current limits have an associated voltage dropout and absolute target limit. On the voltage targets, +/- 2% is a typical level. On the voltage dropout, levels below 200mV are considered aggressive. With target operating voltages in the 1.2v to 3.3v range, this dropout can be a significant delta in the supply. It is important to make sure that the power-down blocks have both signal tolerance to support these dropouts without either switching into the “powering down” sequence or losing information that has passed thru by reloading from non-current state retention registers.

The timing loop for power-up and power-down inside the SoC now has to accommodate “system power modulation” as additional states. To extend operational and standby time for portable devices, the various regulators can started and stopped. This function is generally controlled by state and operational logic contained in the SoC.

There are two major challenges with this design. The first is making sure data and logic that control portions of the regulator system are part of shutdown blocks that might put the design in a non-functioning mode (such as a block being turned off, which controls a regulator that is off, and not getting the control loop closed to restart one or more of the blocks). The second is the timing loop for restarting a shutdown block. The timing has to include the I/O time through the package to the board level, onto the data load and turning on of the regulator block, the stabilization of the supply, and then the completion of the block restart inside the SoC. The external portion of the loop, including the time to stabilization, can take a millisecond. This extended turn-on time may affect the transient power use in data retention and reload logic, as well as on tri-state circuitry that is waiting to turn on. These same constraints affect SoC block turn-off, as well.

If the end system, primarily portable systems, are going to use these centralized control blocks, the power grid design and application has to take into account the interconnected nature of the power rails external to the SoC. The benefits of centralized dynamic control of the application power, as well as the ability to thermally monitor the use and distribution, outweighs the added design task. These new power management chips are key drivers for low-power systems and their feature set is growing rapidly.

Low-Power Engineering sat down to discuss reliability with Ken O’Neill, director of high-reliability product marketing at Actel; Brani Buric, executive vice president at Virage Logic; Bob Smith, vice president of marketing at Magma, and John Sanguinetti, chief technology officer at Forte Design Systems. What follows are excerpts of that conversation.

LPE: As we push to the next process nodes, do all of the tricks of power islands and multiple voltages become more common in designs?
Buric: No, because people will look at the cost of implementation. We have customers looking at simulating and figuring out what are the power savings of switching something off and turning it back on. That costs power. They are doing fairly complicated analyses and staying away from these techniques if they don’t have to use them.

LPE: If you implement all of these techniques, though, is a device more reliable or less reliable?
Buric: In my opinion, it becomes more difficult to make it reliable. But it’s all comes back to your capabilities. If you know how to do it and you’ve done it before, it’s more difficult but you can still do it.
Smith: I don’t think it’s de facto less reliable. But it makes it a heck of lot more difficult to maintain reliability. That requires a lot of work. The other side of this is that low power used to be just battery-powered devices. Now it’s part of the overall Green movement. Everybody is searching for ways to cut power. About 1.5% of all the power generated goes into servers, server farms, and the cooling associated with it. We have a lot of wireless customers. Power is a huge deal. Reliability is a huge deal, too. If you have a phone that dies all the time, the manufacturer is going to go out of business. But we’re starting to see more of a focus on low power for things people plug into the grid, and the government is starting to mandate that. Reducing power without giving up the reliability is very hard.
Sanguinetti: That’s true even in this industry. Quite a number of companies have verification server farms. You run your regression tests with 10,000 processors. That has a power bill of about $1 million a year. That’s a lot of electricity.
Buric: We have 1,000-plus processors just to do fairly straightforward tests. One of the things that is responsible for what’s going on here at the lower technology nodes is that IP memory and logic design and EDA tools help solve reliability problems that may be caused by calculation errors from migration that overload certain parts of the design. It’s much more critical on the current nodes than before. You have to properly characterize IP and use synthesis, high-level synthesis and place-and-route tools to avoid any potential reliability problems in operating conditions.
O’Neill: We’re all coming at this from a variety of different directions, but in our world we see an intersection between low power and reliability. This is from a system-level for high-reliability and outer-space systems. The motivation for achieving low power in the consumer space is battery life and the greater good of the planet. In military and aerospace, battery life can be important in handheld radio systems, but there’s much more interest in reliability. Power becomes a reliability issue for a different reason. There are a lot of very high-performance systems where they can’t have forced cooling. The cooling fan itself is a factor in reliability. Fans can fail and they can increase the risk of foreign debris, which can cause short circuits and add other reliability risks.

LPE: So it’s imperative to lower the power in the parts?
O’Neill: Yes, because as you increase the performance of these systems, more power is being generated. That means more heat, and heat equals reliability risk. There are very few failure mechanisms that decelerate with temperature. Most of them accelerate with temperature, and some of them accelerate exponentially. So minimizing the heat dissipation inside enclosures that have very complex systems running inside them becomes a primary issue. People often come to us seeking low-power FPGAs because there’s some other power-hogging device inside the enclosure generating a lot of heat. They need to minimize that. They can’t afford another heat-generating device.

LPE: Do devices that use lower power last longer?
O’Neill: Given the same process node, if you run at lower power you’re probably going to have better reliability because your junction temperature is lower. That’s going to result in prolonged life.
Buric: If you look at what people are doing with end of life now, they’re saying lower temperature will extend the life. It’s very clear that if you go to overheated conditions where a lot of parts become unpredictably fast then you have a very high chance of a device completely malfunctioning.

LPE: Where does this get designed in?
Sanguinetti: We don’t have any visibility into this.
Smith: Neither do we. It’s something our customers have to deal with. Our job is to get them from concept to manufacturing. Their job is to figure out the application and the expected lifespan. In some applications, a year is fine. If it’s going into the engine controller of an automobile, a year is not fine. That would be more like 15 or 20 years at a minimum.
Buric: End of life is primarily a process function, and for that reason it is analyzed and characterized at the device level. A lot of people simulate end of life, and those models are typically provided by the process side. These are similar to any other SPICE model.
O’Neill: When we design a chip, we design with a package that comes from the foundry. That package will include things like the design rules, which are decided by tradeoffs between reliability, power, functionality and sheer utilization. You want to cram as much logic into as small a space as possible, but you’d better not exceed the electromigration rules or whatever other rules are in there for reliability.

LPE: In the synthesis world, what’s the biggest reliability issue?
Sanguinetti: Logic errors. It’s getting the design right. The issues that our customers have, aside from the spec being wrong, is interfaces between blocks or sections of the design that are done with high-level synthesis and those sections that are done with legacy RTL or manually. That’s where the opportunity for errors is the greatest. When you’re within the confines of high-level synthesis, the opportunity for error gets reduced and the verification problem is reduced. But at those interfaces there’s a lot of potential for miscommunication.

LPE: As the industry becomes more disaggregated, does it become more difficult to pinpoint the source of reliability problems?
Buric: No. Problems are well defined and everyone has to take responsibility. If you go back to our discussion about radiation and alpha particles, you design to eliminate that problem. That design can be in the memory space or error correction. You know what the problem is and you solve the problem. If the problem is end of life and the technology provider gives you all the guidelines, then you design with those in mind. If you own the design, you own the problem. It’s in designers’ hands and it’s a well-defined boundary.
Smith: It’s a gray area. In the ideal world, we get a set of rules from the foundry. There are thousands of them, and if you do this and this then they’ll stand behind the process in the design. For a big part of the population, that’s the way it works. But the people with the deeper pockets will go back to the foundry and say, ‘Let’s talk about where these margins really are because we need to do something special for this product line.’ They’ll get the data, analyze it, and they may design outside of those guidelines. The rules are the rules except when you break them to get an advantage, and then you’d better have the time and the money to go analyze everything to make sure you don’t end up with a product that fails or doesn’t yield.
Buric: You actually don’t break rules. You define a new set of rules that are mutually agreed upon. If you set those rules unilaterally, you’re shooting yourself in the foot. Memory cells have violated every rule, but they’re so predictable in manufacturing that they can violate the rules. All of those are mutually agreed upon, though.

By Pallab Chatterjee
Until recently, low power engineering has been defined by the automated use of EDA tools in the design flow to help cut back on peak dynamic power. The new generation of mobile and video products has forced a change in that methodology.

There are two other fast rising architectural approaches. The first is multicore, which is prevalent in new product introductions from Nvidia, Samsung SLSI, Imagination Technology, NetlogicMicro, Broadcom, and Qualcomm. To address the usability specs required by e-readers, mobile Internet devices and other mobile information products, a new compute architecture was needed that did not just rely on “function disabling” as a power reduction technique. All of these companies introduced designs that are focused on multicore architectures, where there is complete functionality available at all times even though the process has been optimized for low power.

This low power optimization has to do with custom library design creation, modification of internal clocking schemes, datapath and buffer optimization, memory segmentation and placement, and most importantly dynamic control of the design’s power use and speed based on the data content of the information being processed on a per-packet basis. This re-architecture of products was the key enhancement with the new dual Cortex Nvidia Tegra, which is targeted to e-readers and tablet PCs, as well as the high-performance Alchemy multicore and multithreaded processors for automotive and navigation applications, and the many new video and communications appliances from Broadcom and Qualcomm.

The basis for most of these systems are ARM processors cores (A8 or A9 primarily) or MIPS cores. This shift has allowed both a performance increase in the end systems as well as a nearly doubling of the operating battery life.

The second prevalent low-power methodology is the segmentation of design to a CPU and a GPU rather than a single compute engine. While the initial impression is, this takes more power, the GPU is actually more power-efficient on graphics and some video data than the CPU, and on general use functions, the CPU is more power-efficient than the GPU. For most of the smart phones and media processing chips, this approach has replaced bigger single-processor cores with clock-gating and multi-voltage device process solutions.

These architectural changes were implemented to address both the data dependence of the power use and the yield-process variability of sub-wavelength manufacturing. As most of the applications have a very thin and small form factor, they are bound by a fixed or diminishing power envelope. To address the longer term of operation the components can lower the operating voltage, but this does not take into account the associated reduction in performance in the power envelope that is associated with it. In order to address this aspect of design, the mobile handset and mobile computing requirements have driven to the smallest geometry process flows available.

The utilization of these processes (45nm and 40nm, currently) requires restricted design rules, restricted topologies and limited device size diversity to yield well. These designs are optimized with new RTL and physical libraries, new floor plans, and power routing to highlight the data path symmetry that is required by the data sets being processed. Examples of this are new 3dmedia processor in 40nm by Samsung for mobile phones that utilize the IMG Tech 3D video and graphics engine and a high-performance ultra low power ARM CPU.

The distributed multicore approach also has been utilized in high performance for lower power products. AMD/ATI introduced the 5970 Radeon graphics card at the Consumer Electronics Show. The card has two GPUs and is a Direct X11 product with more than 4.6TFlops of peak performance. The restructuring of the device/cell library, its reliance on proven 40nm bulk CMOS processing and the use of GDDR5 memory allows the product to operate with a peak power of about 300 watts but only requires 51 watts for nominal operation. The design was optimized for power and a data control flow to support the 3200 parallel stream processors and the 160 texture units. Dynamic power is managed based on how many streams and texture units are needed at any time based on the contents of the data that being processed on any given cycle.

Most of these new systems are targeting use of Samsung’s low-power DDR3 memory, which operates at 1.3v vs. 1.5 volts and offers higher densities than DDR2. These higher-density, low power solutions can provide in excess of 35% overall power footprint reduction for the design, if used with 32nm low-power flash memories in SSD applications rather than rotating media.

The takeaway from CES this year is that architectural engineering and new firmware control methods are now seen as essential to address the functional requirements of the new mobile communication and processing platforms. This is an intelligent shift from recent years, when only feature size reduction and blind tool-based selection of power gating and power routing were in vogue.

Max Domeika talks to Low-Power Engineering about the impact of power and how that is affecting everything from embedded to multicore software.

http://www.youtube.com/watch?v=BVoren-2N40

By the EEFocus staff
In early 2009 there was a lot of coverage in the media at home and abroad about plasma display panel (PDP) TV sets being banned in the EU. Paul Gray, Director of European TV Research, denied the claim but did mention that they were planning to set minimum energy efficiency standards for flat-panel TVs and set maximum energy consumption limits according to screen sizes. He also said they would require manufacturers to reduce standby power consumption of TVs to less than 1 watt within about a year.

While the EU hasn’t really proposed a ban on the sale of PDP TV sets, it still will put severe restrictions on the (standby and average) power consumption of these products, which will compel companies to make relentless improvements and conduct research to reduce power consumption, enhance power factors and improve luminescence efficiency.

Here are the areas that will be affected:

1. Power Supplies
As an important component of PDPs, the power supply should be efficient and small, provide large transient output power, and have protection function and the function to start different output voltages in sequence.

A traditional PDP power supply generally applies a two-stage scheme, namely, power factor correction (PFC) stage plus a DC-DC conversion circuit topology, each with its own switching device and control circuit. Although it can get good performance, it’s too large and expensive and the circuit is rather complicated. Therefore, its optimization and transformation has become a direction in the PDP power technology research.

PFC modules and scan driver electrode DC-DC conversion modules account for a large proportion of both the transmission energy and space. Therefore, it’s better to start the PDP switching power optimization and transformation from the transformation of these two modules.

There are two optimization solutions available at present. One is a single-stage PFC (SSPFC) circuit, which has become a preferred solution to small-scale PDP switching power transformation due to its small size and simple circuitry. The basic principle is that by adopting single-stage PFC converter circuit topology, full-wave rectified single-phase AC power is connected to dual-transistor flyback DC-DC conversion unit by being in series with two inductive ICs. In the half-power frequency cycle, the inductive current only works continuously part of the time.

A second approach is to use power-factor control chips to carry out active PFC.

2. Drive Circuits
In the total power consumption of a PDP not all of it is gas discharge power consumption, because in the drive circuit high-power and high-frequency switching circuits are needed to provide a variety of high-voltage pulses needed by gas discharge. Although the parasitic capacitance of a PDP screen doesn’t consume energy, its charge and discharge will lead to the energy depletion in the circuit resistance and electrode lead resistance.

The voltage amplitude of a PDP drive circuit is from negative tens of volts to positive hundreds of volts, the working frequency is 100 to 233kHz, and the design and selection of drive circuit is particularly important to the image quality and work efficiency of PDP.

Among PDP drive circuits, the address drive circuit has the highest frequency. Therefore, in addition to using energy recovery technology in the address drive circuit, reducing the pulse voltage of the address drive circuit also can significantly reduce the addressing power consumption. The address voltage pulse can be reduced in the following ways:

● Address while Display (AwD) – Address, sustain and erase pulses combined together can reduce the addressing voltage, thereby reducing useless power consumption. Meanwhile, as the maintenance time occupies most of the time of a sub-field, the frequency of the sustain pulse can be reduced.

● Erase address – After the initialization it enters the light-emitting sustaining phase, and when the gray scale meets requirements it extinguishes these units by erasing addresses. There is only one-time addressing for each pixel in each field, which effectively reduces the power consumption by using low erase voltage and current.

● Changing the work mode of pulse circuit – The switching component can work in the switch tube zero-voltage/current-switching (ZVS or ZCS) state to reduce the switching depletion of the component itself.

In the large-size PDP display, the row/column driver IC consumes a lot. Its power consumption roughly consists of three parts: logic, level-shift register and high-voltage drive. Under normal circumstances, the logic part consumes less than 20mW and the level-shift register part consumes less than 200mW. The useless power consumption of high-voltage drive circuit generated by the charging and discharging of the screen capacitance mainly results from the parasitic load in the loop – the consumption of resistive component. The existence of the resistive component is inevitable, but for the capacitor charging and discharging power, the drive IC can manage to recover a part of it through built-in energy recovery circuit.

To meet the requirements on the operating performance of high-voltage devices, and reduce the useless power consumption of the high-voltage drive part, we should take the following control measures in the design and technique of PDP drive IC, which should be more stringent than that for an ordinary IC.

● Adopt SOI process structure, which can significantly reduce energy consumption compared with the conventional power module;

● Adopt dielectric isolation to avoid the interference among output clamping diodes in the drive IC;

● Give special treatment to internal component structure and layout, and the tunneling current at high voltage switch can be eliminated through internal control;

3. Type Selection of MOS Transistor
The power MOSFET with appropriate parameters can make the drive circuit work efficiently and be more stable in its normal lifecycle. The transition of MOSFETs should be fast enough to reduce the switch loss; the on-resistance should be low enough to reduce the turn-on loss; and the off-resistance should be high enough to increase isolation.

The drain-source on-resistance, reverse recovery time, input capacitance and total gate charge should be given serious attention. Low on-resistance will help reduce the turn-on loss, especially with the MOS transistor related to the “energy recovery circuit,” improve energy recovery efficiency, and reduce the power consumption of PDP. Combined, these can reduce the drive power of MOSFET gate and simplify the design of the gate drive circuit.

The gate drive circuit is an external factor affecting the switch loss of MOS transistor, and only the integration of the excellent gate drive circuit and high-performance MOSFET can make the high-performance PDP drive circuit.

4. Phosphor Materials
New luminescent materials need to be developed. Phosphor materials directly affect the luminescent efficiency and lifespan of PDP TV set, and the lifespan of a PDP TV generally refers to the time it takes for the TV to lose half of its original brightness. Next-generation tailor-made PDP phosphors with long lifespan and high luminescence are now available on the market.

5. Electrode Structure
Although increasing electrode spacing is an effective measure to enhance the brightness and luminous efficiency of PDP, larger spacing needs higher supply voltage. To address this challenge, a floating electrode can be added between the sustaining electrode and scanning electrode, which does not add voltage signal during cell operation but generates some inductive kick amid single sustaining voltage pulse.

6. Others
Useless power consumption needs to be taken into full consideration in terms of logic control, master core boards etc. For example, we can employ the clock-gating method for logic control and close all internal registers in standby state to eliminate useless power consumption.

In conclusion, we can reduce the power consumption of PDP from many perspectives, and simultaneously proceed from power supply, drive mode, phosphor materials, structure of discharge chamber and new high-voltage technique to maximize the efficiency.

EEFocus is the Chinese Media Partner of Low-Power Engineering.

Low-Power Engineering sat down to discuss rising complexity and its effects on verification with Barry Pangrle, solutions architect for low power design and verification at Mentor Graphics; Tom Borgstrom, director of solutions marketing at Synopsys; Lauro Rizzatti, vice president of worldwide marketing at EVE, and Prakash Narain, president and CEO Real Intent. What follows are excerpts of that conversation.

LPE: Does complexity make verification less reliable?
Borgstrom: Verification is an unbounded problem. It’s difficult to ever be 100% confident, and the design is so complex that the state space to be verified is enormous. That is driven by verification complexity.
Rizzatti: Back in the 1970s there was a rule of thumb to achieve confidence in a design. The complexity at the time was in the thousands of gates. The 8086, which we considered large at the time, had 30,000 transistors and 10,000 gates. To achieve confidence you had to apply a number of vectors equal to the square number of the gates, so 10,000 gates will give you 100 million vectors. The Pentium in the 1990s had 1 million gates, so that would mean 1 trillion patterns. That is when the industry split. On one hand, emulation and hardware-assisted came into play. On the other side it was everything formal.
Pangrle: Complexity is certainly going up, but that creates opportunities for the EDA industry. That’s our lifeblood. If design complexity were to stop a lot of the innovation would stop, too. It creates opportunities for better coverage tools, for example. We’ve invested a lot in those hard-to-get-to spaces so the designer isn’t alone trying to figure out how to get there. With formal, you can check properties. There are certain things the design either does or doesn’t do. On the other side, looking at the square of the vectors is on a component basis. The blocks are seeing this kind of complexity, but then you have to catch the interactions between them. That starts coming into the low-power space because you have different modes.
Narain: Verification is an unbounded problem from two dimensions. It starts with something to check for or to check against and then how to check. You really cannot check for everything that can go wrong, though, so your verification is only as good as the number of checkers you have in place. You can apply a trillion vectors, but if you don’t have anyone checking the design you won’t get anything out of it. It’s the quality of the checking. Plus, with the increase in complexity you’ve got many diverse things in the design like clock domain crossing. We cannot have a single clock domain running through the design. When you put all these things together the failure modes go up and we have issues covering the failure modes, and we need a process to manage that. You focus on interactions between the blocks, which bounds the problem with a divide-and-conquer approach. But the cost of verification is still going up and the probability of failures creeping into a design is getting higher.

LPE: Is verification really just split between formal and emulation?
Borgstrom: No, and I’d like to take issue with that. Device complexity is growing in many different facets. Not only do we have low-power designs becoming much more common, but almost every block contains analog components that need to be verified. Plus, there are embedded processors where you have to do hardware-software co-verification. One of the aspects of complexity in this unbounded problem is you need to take multiple approaches with multiple engines to get competence across all aspects of a design, such as mixed signal simulation or hardware-software co-verification at high speeds.

LPE: When it comes to verifying a complex chip, what’s good enough?
Narain: At the time the project manager makes the decision to tape out, I wouldn’t want to be in his or her shoes. In a structured methodology you create your checklist and process and you check everything in there. Then you worry about the chip coming back bad. The complexity is so high that the best mechanism is to isolate the failure modes and then use the most thorough mechanism to check for them. With design planning, where you are doing power verification on blocks and have something specific for checking interactions between them, it should be a totally independent process. It’s the same for low-power analysis. But the more you can isolate them, the more confidence you have that you have minimized your failure modes. And then you need to make sure there are no bottlenecks and all your interactions work.

LPE: But the other piece no one is talking about is time to market, which gets worse when we start factoring in power modeling and multiple islands, right?
Narain: Absolutely. And there’s another piece beyond that—at what cost? How many engineers can you hire and what are your resource constraints?
Borgstrom: In the past, verification was very much an ad hoc process. It was up to individual verification engineers to decide when they were done. What we’re seeing now is a more structured approach where you have quantitative metrics for things like code stability of the design itself, the number of vectors that have been run, what is the bug discovery rate, and then tying them all together into a verification plan. So at the beginning of the process you decide what you have to verify on a feature-by-feature basis, and then for each of those features how do you assess whether it’s been verified. Maybe you use formal techniques for some features, hardware-software co-verification for other features and some mixed signal for some things. An executable verification is gaining more traction in the industry so you can make a more educated decision to tape out.
Pangrle: It’s definitely important to have that process and make sure you know what you’re looking for. On top of that there are other tools that you can use to see which paths you are covering and point out places you might not have thought about.

LPE: But how do you know when you can check at a higher level of abstraction, and when you have to drill down with formal techniques?
Pangrle: Part of that depends on the level you’re running at. You can look back at building an arithmetic unit using formal techniques. But formal techniques have to be kept on a level that’s still tractable. At some point it’s going to blow up, so you have to figure out what can you simulate using vectors and what can I cover with different kinds of assertions or properties I’m looking for to make sure they’re captured in my design. Above that, some of it falls into the expertise of the person who’s running the verification process. Some people do it better than others. Going to a higher level of abstraction is another way.
Rizzatti: The problem with a higher level of abstraction, though, is that as soon as you deal with software and you have to test the interaction between the software and the hardware all of that will collapse. I’m not aware of any formal approach that will do any good there.
Narain: A higher level of abstraction is a double-edged sword. It certainly reduces complexity, but then you have to go through one more level of translation to get to RTL, and from there to gates. You lose control over your process. Functionality is not the only thing. There’s also timing and physical characteristics, and all of those are controlled at the RTL level.
Pangrle: I would argue that now you already have architects doing modeling in C.
Narain: But that’s for a verification model, not as a design model.
Pangrle: Then there’s a total disconnect. If I’m an architect doing some mathematical modeling and I take what some engineer did in Matlab, create a C model and if I think it’s okay then I just throw it over the wall to the RTL guys to implement it—then where’s the connection?
Narain: Other than emulation the big problem is coming up with what you want to test for. Typically the higher-level models are used as the model against which you simulate RTL. If you don’t have the two-model approach then you’re compromising on the verification quality.

LPE: So higher-level models don’t work as well for verification?
Borgstrom: If you can generate that RTL from the higher-level description directly, there’s less importance in doing a lot of verification at the RTL level. You still need to do some verification at the RTL level. You’re looking for different types of failure modes. If you originally implement the functionality in RTL, you’re looking for functional bugs in the RTL.
Narain: But how do you check for those?
Borgstrom: We can use high-level models written in the M language, which is very common for algorithm architects, and we can automatically map it down into a discrete-time RTL model that can be simulated. You can do your verification at your high-level algorithm and assume that your translation from algorithm to RTL is done correctly. There’s equivalence tracking that can be done. That’s one of the bigger challenges of enabling this high-level verification flow—enabling that formal equivalence checking and the synthesis parts of the flow. I think we’re starting to make progress.
Narain: In my opinion if you attempt to use that, you compromise on verification quality. Verification is not an isolated problem. Verification and design are constantly making tradeoffs.

Low-Power Design today changes its name to Low-Power Engineering reflecting a broader context for low-power issues that extend well beyond the confines of just design.

We discovered the need for this change several months ago—and many stories after launching Low-Power Design. Polls of our readers and our sponsors, which we conduct on a regular basis, showed our name was too narrow for the market we serve. While our focus is still semiconductors, the stories we write range from deep technology within the chips to the causes and effects of lowering power—everything from macroeconomics and politics to atomic physics.

Reducing the voltage in a device cannot be viewed in a vacuum. It can affect everything from the delivery of power within that device to a battery’s voltage regulators and the overall return on investment for a chip company—fabless or IDM. Increasing densities has marked effects on single-event upsets. And demands in the data center may have a significant impact on the overall utilization of a processor’s cores and the memory structures within or outside of those processors.

These issues have a significant impact on decisions about how many power islands need to be created, how many cores should be added to the chip and whether they should be homogeneous or heterogeneous, and how all of this affects throughput and leakage. These are complex engineering decisions, and they stretch from outside the semiconductor to deep within and back again. Designs have to be validated and verified, and everyone needs to understand the tradeoffs and the context in which decisions are made.

We fully intend to cover these subjects the way we always have, in keeping with good journalistic principles—unbiased, well researched, well written and fiercely independent. But we also need to provide a better description of what we’re all about. Check out our new url, too. (www.lowpowerengineering.com).