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Expert Interviews: Jasper’s Lawrence Loh: IP Power Specs

Tuesday, February 4th, 2014

LPD got to speak briefly with Lawrence Loh of Jasper Design Automation about IP power specifications recently.  Here’s what we learned.

Q: “What can IP providers do to provide better models to more accurately represent power in various operating states?”

SOCs today are made from IP, they aren’t designed from scratch.  Most of the power description is done at the SoC level though.  You rarely see power domain descriptions for IPs.
There are two types of power models that are very important to provide for IP.  Power estimation is not just a number.  It’s about what determining what usage scenarios use what power.  The first set of models is built by looking at which signals are switching during a particular functional behavior of the IP. Then power-estimation for each of these behaviors is performed. With this model, the SOC team can perform its own power estimation based on which and how often certain functional behaviors of these IPs are used.
The second set of models is the functional model that maps the behavior of the SoC in terms of integrated functionality.  These models need to accurately model the behavior of the IP, not just for normal functionalities, but also for power-up and down behavior. The SOC team will then able to verify the overall SOC functionalities including power-sequencing and other low-power behavior.

SOCs today are made from IP, they aren’t designed from scratch.  Most of the power description is done at the SoC level though.  You rarely see power domain descriptions for IPs.  There are two types of power models that are very important to provide for IP.  Power estimation is not just a number.  It’s about what determining what usage scenarios use what power.  The first set of models is built by looking at which signals are switching during a particular functional behavior of the IP. Then power-estimation for each of these behaviors is performed. With this model, the SOC team can perform its own power estimation based on which and how often certain functional behaviors of these IPs are used.  The second set of models is the functional model that maps the behavior of the SoC in terms of integrated functionality.  These models need to accurately model the behavior of the IP, not just for normal functionalities, but also for power-up and down behavior. The SOC team will then able to verify the overall SOC functionalities including power-sequencing and other low-power behavior.

Q:  Who is the customer of the power description information?

The SoC team usually has a group that is specifically in charge of low power. They determine what power each IP block uses, compare this with the power budget they have, and determine how to partition the IP into different power domains to accomplish their goals. Once the power domains are determined, they will need to define a proper power sequence to enable and disable power for each domain.  The next level of customers for IP power specifications are the people who do the implementation.  They create a file alongside the RTL code that describes how IP blocks connect to each other.  They try to include enough information so that if, for example, blocks that were initially connected with each other directly are placed in different domains, it will be apparent where rails need to be placed to isolate the new domains from each other.  These are usually people who write in the proprietary or standard format that describes the power.  Finally, there are the verification people who need to make sure that the different power behaviors work as expected.   With so many different groups of people that need to work with the power domains it’s important to have a way to capture this information.

From the solution space point of view, obviously many vendors are providing solution to different aspects of low power engineering projects.  Having a power specification language that describes power consumption, power domains and interconnects allows different tools to enter into the flow.  Low power is a big aspect of SoC design projects spanning many activities and solution spaces.   A power specification language gives different vendors a way to integrate their tools together so that they can implement a complete low power solution.  There are some standards around and standards have advantages and disadvantages, but the advantages are more universal.  IPXACT is one way to standardize. SystemRDL is another.  The jury is still out on what format is the best.

Lawrence Loh, Vice President of Worldwide Applications Engineering, Jasper Design
Lawrence Loh holds overall management responsibility for the company’s applications engineering and methodology development. Loh has been with the company since 2002, and was formerly Jasper’s Director of Application Engineering. He holds four U.S. patents on formal technologies. His prior experience includes verification and emulation engineering for MIPS, and verification manager for Infineon’s successful LAN Business Unit. Loh holds a BSEE from California Polytechnic State University and an MSEE from San Diego State.

Lawrence Loh, Vice President of Worldwide Applications Engineering, Jasper DesignLawrence Loh holds overall management responsibility for the company’s applications engineering and methodology development. Loh has been with the company since 2002, and was formerly Jasper’s Director of Application Engineering. He holds four U.S. patents on formal technologies. His prior experience includes verification and emulation engineering for MIPS, and verification manager for Infineon’s successful LAN Business Unit. Loh holds a BSEE from California Polytechnic State University and an MSEE from San Diego State.

Expert Interviews: Apache’s Aveek Sarkar: Low Power Design

Monday, December 23rd, 2013

By Hamilton Carter, Editor/Verification-Low Power

LPE got to sit down with ANSYS Apache’s Aveek Sarkar to discuss how design engineers sort out the variety of low power techniques that are available to them.

LPE:  Where do design engineers start when looking at different power efficiency design techniques?

Clock gating was one of the first things people started to look at for power optimization.  In clock gating you shut off parts of your clock network such as a the portion of the clock network driving a particular bank of registers that do not have any data activity – this way you can save dynamic power.  It’s still one of the first places to look for savings as dynamic power is a big component of overall power.  There’s a pitfall however.  A common mistake is not taking the design of the enable signals or their efficiency into account.  If 99% of the design is clock gated, it doesn’t mean that you have a low power design – it also depends on whether the enable signal is operating efficiently.  Often times, projects which have clock gated the entire design can still lose sight of the fact that the efficiency of clock gating is controlled by the enable signal. If the enable signal is not designed properly it can limit the amount of power reduction you can achieve. So it’s  important to simulate the design and perform rigorous power exploration, tracking various metrics including clock gating efficiency especially at the RTL level to isolate and fix such scenarios.

LPE: What about power gating?

Power gating is commonly used to control  leakage current or standby power.  Its use started to become prominent around 2005 by mobile IC design teams, especially starting with the 65 nm process nodes.  The leakage current was an increasing trend in those process nodes – to control that, they started adding power gating as a low power design technique.  Power gating effectively breaks up power supply into two paths: an external path and an internal path by putting NMOS or PMOS transistor in series with the power rails.  For example, if the video block of the device is not being accessed then the video processing section of the chip does not need to operate. By flipping off that particular switch on the power rail, it turns off or disconnects that block from the rest of the power supply.  As a result, the leakage current drops significantly, sometime as much as 10x to 15x. However, based on some of the metrics that are printed in the press, especially with the advent of finFET, leakage power seems to be getting more under control as compared to dynamic power.  So power gating is still being used but it’s not clear if it’s going to be a standard technique going forward.

When using power gating, you need to worry about few things. The first thing to consider is that when you turn off power, you need to make sure that the state of certain parts of the device needs to be retained.  So you need well designed retention logic to make sure that you don’t lose whatever the design was doing last even if you shut off the power to that block.  You want to make sure you can recover the last state and move onwards. The second thing to consider is the time it takes to bring the block back on after its power off state and the current and voltage levels during and after the power up process.

The current trend is to look at power gating the design from a macro level – that means to power gate bigger sections of the chip rather than looking at it in a finer grain. With power gating at the macro scale, there are a couple of things you need to worry about.  For example when you turn a block back on you need a lot of current.  If the size of the power gated block is significant, such as an entire CPU core, a lot of charge is required to turn it on. If you have to supply power all at once, the battery may not be able to supply it quickly enough.  When this current goes through the package, it gets impeded. Two things can happen.  First, if you don’t power up quickly you can end up seeing an hourglass on the device’s screen since that block takes much longer to power up or doesn’t power up to the right voltage level.

Second, and possibly worse, the block that is turning on may borrow charge from a neighboring block.  For example, if  you powered off one of the CPUs in a quad core architecture and shortly thereafter turn it back on. This power-on process will require a lot of charge and you may end up stealing from the neighboring CPU. But the neighboring CPU may be still running.  So, as you take charge from the neighboring CPU it can end up experiencing higher voltage drop or increased noise coupling, which can impact its performance or cause it to fail.  This kind is scenario is fairly common and has to be watched out for, ideally with the use of a full-chip level package-aware power noise analysis flow that can model such a scenario.

LPE: How do dynamic voltage and frequency scaling factor in?

Depending on the type of application that is running, the chip can become very hot and to control the heat, the chip will need to be slowed down to extend the its lifetime or improve its power performance. But this technique, like others has the same set of challenges since it can introduce unknown behavior that can crop up when the device goes from one mode to another, or from one activity to another.  To protect against unpredictable behavior, the design needs to be modeled at the full chip level with the package and the board to simulate the transient current changes that accompany these mode transitions.

LPE: What other power saving techniques might be of interest?

Forward and reverse biasing rate techniques are making a comeback.  We are seeing designs where these techniques are being used.  Another interesting technology that is becoming prevalent is the use of on-chip voltage regulators (LDO).  When people want to control voltage for mission critical devices in an automotive IC or say for a sensor inside a pacemaker or other devices where you consume very little power over time, on-chip regulators will become increasingly critical. For these devices, it is very important to model the operation of the LDO in context of the design it is supplying power to. This ensures that the LDO can operate reliably across the entire range of operation of the chip.

Aveek Sarkar joined Apache Design, Inc., a subsidiary of ANSYS, as a senior applications engineer in 2003. Since then he has taken on different roles and responsibilities. Prior to joining Apache, Mr. Sarkar worked for Sun Microsystems on several generations of UltraSparc processors. Prior to Sun, he held engineering positions at Cadence Design Systems and National Semiconductor. Mr. Sarkar holds a B. Tech from the Indian Institute of Technology, Kanpur, a MSEE from Oregon State University, and MBA from Santa Clara University.

Low Power News, December 20, 2013

Friday, December 20th, 2013

ARM Acquires Geomerics
You may have noticed the mention of the partnership between ARM and Geomerics in this months Research Review.  ARM took the partnership to the next level by announcing their acquisition of Geomerics last Friday.  Pete Hutton, executive vice president and general manager of ARM’s Media Processing Division said,

“The innovative technologies being developed by Geomerics are already revolutionizing the console gaming experience and are set to rapidly accelerate the transition to photo realistic graphics in mobile.  Empowering Geomerics’ portfolio with ARM’s graphics capabilities and market reach will be transformative for the user experiences in future mobile and entertainment devices.”


STMicroelectronics joins the ARM mbed Project
STMicroelectronics announced that it has joined the ARM mbed Project giving users of their STM32 microcontrollers access to the mbed software, development tools, and collaboration platform.  Simon Ford, director of IoT Platforms for ARM explained the mbed project,

“The mbed project is bringing together leading technology companies to create a step change in productivity for embedded device development.  We have learnt from the web and smartphone revolutions that by building an open-source software platform with reusable software components and free development and collaboration tools, we can enable the creation of IoT and smart devices on a previously unimagined scale.”

New Wireless Charging SDK for Nordic Semiconductor nRF51 Series
Nordic Semiconductor announced the availability of the S120 8-link central protocol stack and the nRF51 Wireless Charging SDK for wireless charging applications based on the Rezence standard, developed and maintained by the Alliance for Wireless Power (A4WP).  Nordic’s nRF51 series of devices enables Bluetooth low power which is the out of band communications channel used by the Rezence standard.  For those not familiar with the technology, Rezence is a magnetic resonance charging technology utilized for the wireless charging of battery operated devices.  If you’d like to find out what the nRF51 series is all about via hands on experience, check this out.

Silicon Labs Announces new Wireless MCUs
Silicon Labs has announced two new entries in their series of RF enabled 8 bit microcontrollers, the Si106x and Si108x wireless MCUs.  These devices combine an 8051 MCU with a sub-GHz RF transceiver and a number of handy peripherals such as ADCs and serial interfaces.   Both MCUs feature low power consumption when the radio is active puling 18 mA when transmitting at +10 dBm and 10.7 mA in low-power receive mode.

Atmel On Wearable Computing and CES 2014
Finally, read about what you might expect to see in the latest wearable computing at CES 2014 on Atmel’s blog.  According to Gartner’s Angela McIntyre, the segment will be hot!

Low Power News November 29th, 2013

Friday, November 29th, 2013

ARM is helping to build the future supply of ARM architecture based engineers with an agreement that will bring the ARM Accredited Engineer program to the National IC Design Shenzhen Industrial Center (SZICC), in Shenzhen, China.

Qualcomm announced they’re applying their Mobile DNA technology to what they’ve deemed the Internet of Everything.  Amir Faintuch, president of Qualcomm Atheros, says, “Just as Qualcomm helped propel the smartphone experience and ecosystem, we are now employing the company’s mobile DNA to enable the Smarthome as a platform to deliver an advanced class of content, applications and services that can be enjoyed throughout the home. Qualcomm is bringing together its mobile and networking expertise in the Internet Processor to extend its portfolio and enable new capabilities for network platforms

Spansion has launched a new family of microcontrollers for the industrial internet of things. Saied Tehrani, senior vice president and CTO of Spansion  “Spansion delivers a scalable family of microcontrollers designed for the industrial market with options from low power to industry-leading performance that allows for differentiated features such as touch, connectivity and inverter drives to be added into a single MCU,

Synopsys has announced a new ultra low power non-volatile memory that consumes 90% less power than the previous generation of the technology.

At the Elektra Awards, ARM was awarded the Educational Support Award.  SureCore took the Design Team of the Year Award for ultra-low power memory technology.

Finally, researchers at Eotvos University in Budapest, and at the University of Vermont are studying how the light harvesting networks of plants could be serve as computational engines.

Predictions About Technology and Future Engineers

Tuesday, November 26th, 2013

By John Blyler, Content Officer

What follows is a portion of my interview with Dassault Systemes’s “Compass” magazine about the most critical technologies and issues faced by the technical community to manage increasing complexity within shrinking design cycles. My list includes hardware-software co-design; cyber-physical systems; wireless chips; low power; and motivating students to high-tech. – JB

Compass: The past decade has seen many milestones in hardware/software co-design. What do you think will stand out in the next decade?

JB: Thanks to Moore’s Law and the efficiencies of engineering chips and boards, these things have become commodities. Companies have been forced to differentiate themselves with the software. Also, when you design a chip, you have to think about designing the board at the same time, so you get into the co-hardware/hardware design with software tying everything together.

That trend toward tighter integration is only going to accelerate. The time to get your product to market is shrinking, so you need to have software designed while the hardware is being designed. In many instances, the software demands at the user level are dictating what the chip design will be. Before, it was the other way around.

Compass: What are today’s biggest challenges in systems modeling, integration, and designing for the user?

JB: When I tell my engineering friends the movement is toward designing for the end user’s experience, they scratch their heads. It’s easy to see how that applies to software, because with software it’s easy to change on the fly. But for hardware, that’s trickier. How is that going to be implemented? That’s something the engineering community and manufacturing community are still wrestling with.

You see it in cell phones. The end-user input must come early in the design cycle as it will affect both the software and electrical-mechanical subsystems. Further, everything has to be low-power and green. You have a mountain of considerations, aside from just getting the product to work.

Read the full interview at Compass magazine.

Research Review November 12, 2013

Tuesday, November 12th, 2013

SmartLoc System Improves GPS Accuracy and Increases Battery Life

Researchers at the Illinois Institute of Technology have developed a system that can not only improve the accuracy of smartphone GPS systems in large city settings, but also extend their battery life.  While GPS accuracy in highly congested areas averages about 40 meters, the new system claims accuracies of 20 meters or better.

The new system uses a phone’s inertial tracking systems, (accelerometer), and compass to glean more detailed information about the users location between GPS location updates.  In addition to tracking the movement of the phone, the system builds a database of geographic features near a given GPS location.  For example, as a car travels over a humped bridge, the phones accelerometer produces a recognizable pattern of slightly increased and then slightly decreased downward acceleration.  The system can use this pattern to pinpoint the phones location on a nearby bridge that fits the pattern.  All geographic information is currently provided by Google Maps via the 4G network.  These network accesses use significantly less power than GPS functionality increasing battery life.  Using the SmartLoc system, as its called, it may even be possible to turn off GPS circuitry for periods of time resulting in even greater battery efficiency.

Selling Verification Internally
Paul McLellan chronicled ARM’s Laurent Arditi’s efforts to promote the use of formal verification techniques.  The advice given by Arditi can be applied to selling any new technology in-house.  Arditi advises engineers first,  not to oversell a technology by promising benefits that the system simply can’t deliver, and second to record metrics on the gains and costs of the technology meticulously over each project where the new technology is utilized.  By keeping expectations rational and being able to objectively report results, engineers can more easily influence executive decision makers to participate in their own success.

Arditi was specifically working on propagating successful formal verification techniques with ARM and reports that the aspects of a design to focus formal verification on are:

  • embedded assertions/properties are primarily written for simulation and so can be used for formal at no extra cost
  • X-propagation is low hanging fruit since simulation has issues with it and formal can do it with very few hand-written properties
  • complex clocking schemes are hard to verify with simulation but formal has found many corner case bugs and a major bug on the Cortex-A12
  • use Jasper ProofKits
  • reduce the cost of simulation. correlate formal coverage with simulation coverage, don’t try and do stuff like X-propagation in simulation, remove a big effort from simulation/humans
  • use simulation tricks (like reducing FIFO depths, changing arbitration) to reduce formal proof times too”

Low Power News: November 8, 2013

Friday, November 8th, 2013

ARM and Nordic Semiconductor announced an agreement to incorporate Nordic’s low power bluetooth solutions into ARM’s mbed IoT device development platform.

This announcement comes on the heels of Nordic’s introduction of an SoC that incorporates both bluetooth and ANT+ wireless protocols.

ASIC startups are entering the Bitcoin mining market.  The newish currency is created/printed based on networked computers solving crypto algorithms.  I wonder if the market could be crashed by the NSA at will.

Today is the deadline for the Movein3D design contest sponsored in part by Daassault Systemes.  Keep an eye out here for news of the winners.

GPS is battery hungry and often just unavailable in city centers.  A team of researchers in Chicago has developed an app that offloads some GPS tasks to smartphone onboard accelerometers.  The result is a more precise position and longer battery life.

Third quarter results continued to roll in with ANSYS of ANSYS-Apache fame reporting record results.

In other news of ANSYS, they’ll be offering a free ANSYS DesignModeler online course for egineering studentsNovember 28th and 29th.

Lockheed is working on the successor to the SR-71 Blackbird.  Initial mockups indicate the Mach 6 craft might be windowless.

Peregrine Semiconductor announced a partnershiop with Global Foundries to produce their SOI RF switch devices[pdf] paving the for their entry into the 3G handset market.

Low Power News: November 1, 2013

Friday, November 1st, 2013

Amiq introduces improved mixed language capabilities, Qualcomm/Arteris rumors,  and the newest addition to the IoT, a brassiere that tweets.

Have you heard about Qualcomm and Arteris and DSPs?  Check out the latest rumors.

If you enjoyed this week’s article on power grid design and inductors, and you’d like to get even deeper into the analog side of elctronics, check out this primer on 1/f noise and the 80 year old mystery surrounding its frequency spectrum.

Amiq introduced new mixed language capabilities to their multi-language IDE.

The newest addition to the IoT is highlighting womens’ breasts in Greece.  During breast cancer awareness month, Nestle has teamed up with Greek TV presenter Maria Bacodimou, who has agreed to wear a bra that, when removed, will send tweets reminding women to perform breast self-exams.

At ARM Techcon this week Xilinx’s customers showed off their newest applications for the  Zynq-7000 architecture which melds an ARM Cortex A9 MPCore with 28nm programmable logic.

If you’re looking for a fun way to kill a few hours this weekend you might want to check out Google’s quantum mechanics mod for Minecraft.

And, in closing this week, Lenovo has announced their newest product engineer, Ashton Kutcher.  That guy can do everything!

Digital vs. Analog and the verification of power: Inductors

Tuesday, October 29th, 2013

I got a chance to speak with Aveek Sarkar, vice president of product engineering and support at ANSYS Apache this week.  Our conversation about power aware verification revolved around the di/dt voltage drop caused by on chip inductors also known as power delivery grids.  Although, I grew up as an analog engineer dallying with inductors and capacitors on a daily basis, as a functional verification engineer, I’ve considered inductors and capacitors… well… almost never.  Consequently I thought it might be kind of fun to run through a high level review of why inductors drop voltages.

Inductors, Calculus, and the Time Domain

While discussing verifying the power distribution grid, the expression, ‘LDIDT drop’, came up a lot.  Written down, it looks like this

and is translated as: the instantaneous voltage drop across an inductor is equal to its inductance times the rate that the current through the inductor is changing with time.  Why does it matter?  When a block of a chip is powered off and then powered back on, there is a quick change from zero current running down the supply bus to the total amount of current needed by the block.

The above picture is idealized, but it gets the point across.  The current running down the supply bus jumped from zero to Io in a very short time.  Consequently, the voltage drop across the inductor went from zero to a big number, (Io divided by a number approaching zero).  It is this voltage drop that can cause problems downstream on the power bus, especially if the power bus in question is attached to other blocks.

An analogy of Aveek’s that I paraphrase here is apt.  If you’ve ever rented an old cabin, or had the pleasure of living in college slums at school, you may have noticed that with all the lights on, and the washing machine running, when you turned on the microwave, the lights all over the house flickered.  That flickering was due to the L di/dt voltage drop caused by the microwave quickly slurping a gulp of current off the shared power line.  Flickering lights can be intriguing and even romantic in the right setting, but in digital circuits, flicker is just plain bad.

Inductors and the Frequency Domain

Thanks to Heaviside lots of us like to think of inductors in the frequency rather than the time domain.  In the frequency domain the expression for the above voltage drop is:

where j is the square root of negative one and omega is the frequency of the current running through the inductor.  In short, the inductor acts as a larger impedance to higher frequency signals.  How does this apply to our step function above?  Any time-based waveform like our step can be expressed as sum of sine waves via a Fourier series.  The picture below illustrates how sine waves of different frequencies can be added to create a square wave-like shape.

Note that to get closer to an actual square wave, more waves of higher frequency have to be added to the sum.  The additional sine waves of higher frequency see a higher impedance due to the inductor and therefore, a larger voltage drop.

A Musical Side note

The same process described above is why audiophiles will tell you that music sampled at 56 kHz simply isn’t crisp enough and that they prefer the ‘more realistic’ sound of 96, or even 160 kHz sampled music.  It’s all about having more available frequencies to more accurately reconstruct a waveform.

Summary

Fast changes in current can make circuit elements that once looked like wires behave like inductors.  The associated voltage drop downstream can wreak havoc with the rest of the circuit.  The equation that governs this voltage drop can be thought of in either time domain as it happens via a bit of calculus, or in the frequency domain as a consequence of the high frequency waveforms required to create fast current transitions.

Low-Power News October 25, 2013

Saturday, October 26th, 2013

Find out what powers the internet of things.  Stephen Ohr of Gartner describes the two main R&D thrusts to provide power for IoT sensors that have to live in the wild unmaintained and without a power main for up to 20 years.

NXP introduced a new data acquisition oriented microcontroller which utilizes an ARM cortex processor this week.  The LPC4370 features “… the fastest 12-bit ADC available on a Cortex-M microcontroller today with a sampling rate of 80 Msps”.

Many companies announced their third quarter financials this week.  ARM and NXP both announced theirs.

For the most complete and up-to-date copies of any publicly traded U.S. company’s results, you can search the SEC’s Edgar database.

ARM will release new technical details for their ARMv8-R architecture next week at the ARM TechCon, in Santa Clara,  (Tuesday 29th – Thursday 31st October 2013).  The new architecture is targeted for the automotive and industrial controls markets and features new virtualization and memory protection technology as well as NEON SIMD instructions for improved digital signal processing.

Power Integrations were the first to demonstrate a reference design for Qualcomm’s Quick Charge 2.0.  You can read all about the design in their report [pdf], (it’s pretty and detailed!)

ANSYS moved into the top 100 of the Software 500, (as ranked by Software Magazine), list this year.

Researchers in Twente have announced nano-etching technology that should be able to store data for up to one million years.

Finally, astronomers announced the discovery of a new galaxy which now holds the record for being the farthest from the Earth.

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