Power consumption due to leakage has become a major factor in the total power consumption equation for battery powered and sub-100 nm designs, compelling design teams to adopt various power management design techniques. Power gating is one of the most effective techniques for managing leakage power.

In addition, at sub-65 nm process nodes, different biasing techniques are being combined with power gating in order to minimize leakage power. Employing low power techniques, such as power gating and substrate biasing, gives rise to many thorny verification challenges. For example, are the power control sequences correct; is my biasing strategy functionally correct; do the “awake” portions of the design still function correctly when other domains are powered down; is adequate state information retained when state retention is employed; is the proper retention protocol followed; and is my isolation strategy functionally correct.

To download this white paper, click here.

By Ann Steffora Mutschler

Back in the early days of semiconductor design engineers could count the number of transistors on their chip with their own two eyes. They designed and worked at the same level of design abstraction when doing the timing analysis. Tools were SPICE-like, maybe abstracted with slightly simpler timing models than the SPICE-level transistor models.

Thanks to Moore’s Law, the number of transistors that can fit on a chip has grown to the billions, which obviously can’t be counted with the naked eye. But they also no longer scale with SPICE. Abstraction has been the way out by providing a higher-level view on the design.

“Clearly, even when I’m at gate level, I know I’m not getting the same accuracy that I would be getting at SPICE level, but if my models are good enough and it is close enough, I’m willing to take that slight hit to be able to do bigger designs,” noted Barry Pangrle, a solutions architect for low-power design at Mentor Graphics. “That’s the progression that we’ve gone from—transistors to gates. Then people were doing schematic capture and everything was gate-level models. Then we went to RTL and we started moving to RTL models. Now we are moving on into system and bigger components and functional blocks. At each level, we’re giving up some measure of accuracy—it’s just not going to be as detailed. It’s not going to be as fine-grained and the hope is though that we have enough information that we can make the decisions at that level of abstraction.”

The abstraction levels in use today were developed over a long period of time. They are well-defined because a huge amount of work was done in terms of both modeling, to make sure we can move between levels, and to ensure there is the appropriate level of detail to accomplish what needs to happen in that level.

“Today, we’ve tuned it and created enough modeling around it so we can get the information that we need out,” said Cary Chin, director of technical marketing for low-power solutions at Synopsys. “But I would say that the model isn’t general enough if we thought of some new use of these connections and voltages and expected it to give us the data that we wanted. Whereas if you did that all in SPICE, it likely would [provide the right data] because that’s one indication of the maturity of the model—whether you can use it for things that weren’t anticipated originally when you built the model.”

At the RTL level engineers synthesize down to a gate-level netlist so that they can bring in their gate level models, Pangrle said, with the hope that based on the information they get from those models, they can create something that’s going to be representative of what they need at the RTL level. “Now we’re looking at going one level beyond that and saying, ‘Okay, at the next level of abstraction what kind of information can we capture here?’ The tricky part is making sure that you still have the level of accuracy that you need to be able to make the types of design decisions that you’re going to rely on that information.”

But these levels of abstraction are not all fun and games. For engineering teams doing low-power designs, there are many challenges moving between these different design abstraction views, the biggest one between the RTL to gate because these two abstraction levels have too many big differences, explained Qi Wang, technical marketing group director for low power and mixed signal at Cadence. “On top of that, there is a lot of handshake of tools between those two levels.”

For example, he said an important aspect of low-power design is to gather activities. RTL simulation is run to collect activity, so all of the signal activity is annotated along with all the signal names. The engineer hopes to re-use that activity at the gate level, but the problem is the name seen at the RTL may not be the name seen at the gate level because the synthesis tool renames the files.

Power formats

In addition to this renaming, a lot of optimization can happen between the RTL and the gate level, which means that some signal may simply optimize out. Another possibility is that the logic may not optimize out but the representation can be changed, Wang said. “On the activity side, this is a flow challenge. The activity file you get for the RTL you hope you can re-use for the gate level, but many times you will find it is very difficult.”

Another kind of difficulty involved is with the power format, no matter what standard is, Wang noted. “The whole idea is that you describe your power intent in another file… If you write a power format file for RTL, which means it will be used for the RTL so all the names you refer to would be the RTL names. Now when you get to the gate level you hope you can use the same RTL level power intent because I want to keep my golden power intent through the design and verification flow.” But this will have the same problem as in the activity file.

To address this formal verification techniques can be used to indicate which RTL register names map to the corresponding flip flop on the netlist with a name-mapping file.

Then on the power intent side, he suggested the easiest way to deal with the renaming issue to have the synthesis tool write out a new power intent file, which automatically will reflect the name changes and the hierarchy ungrouping. When it comes to enabling the flow, however, the power intent written out by the synthesis must be equivalent to the original power intent, which is where power-aware equivalence checking tools are utilized to prove that the new power intent and the old power intent are equivalent.

Twenty years of hard labor

Traditionally, traversing levels of abstraction has been relatively straightforward—it’s just a lot of work. “If you look at the library modeling process that has evolved to go from kind of transistor level to gate level, things are very well defined today,” Chin said. “Libraries are super solid and vendors know how to characterize things even as the technology changes. That’s an example of a level of abstraction that’s pretty mature because over the last three, four or five generations of technology, we haven’t had to make major changes. There have been many, many little extensions and timing models and functionality and things like that but basically since we haven’t changed the fundamental design flow, the models and libraries have stayed pretty much the same, which is great.”

There have been similar advances in synthesis. “If you look at this between RTL and gate level, synthesis has changed a lot over that time, as well, but in general if you couple synthesis with verification tools and formal verification tools, things have actually grown nicely so that we still have very dependable flows that most people are still pretty happy with. You can push the button and trust what comes out at the other end. And as you recall, it took us 20 years to develop that level of trust,” he concluded.

Once the engineering community moves en masse to the system level, that 20 years could easily be duplicated.

By Ann Steffora Mutschler
Electromigration (EM) and electrostatic discharge (ESD) may not be new, but design design sophistication and tiny wires are demanding that engineering teams take a fresh look and utilize new tools to lesson the impacts of damaging electrical events.

“These are certainly not new phenomenon,” said Carey Robertson, director of product marketing for Calibre at Mentor Graphics. “We’ve had to wrestle with them for some time. Fifteen years ago when I was doing microprocessor design at 0.35-micron at DEC (Digital Equipment Corp.) we had an electrical migration budget and the reason for that requirement was that DEC—which put chips into VAXes and things that would do your financial statements—essentially had budgets that said our chips will last 10 years and expected 1%t of them to have failures due to EM.”

That type of requirement was never applied to the mobile market because devices aren’t expected to last that long, and fabless companies historically have not been particularly concerned about EM. Automotive companies have been a different story because cars are expected to last for a decade or more. That’s all changing as designs scale and chips get smaller and smaller, however.

“There was an inflection point some time ago when we switched from aluminum to copper—at about the 65nm/40nm process node,” Robertson said. “The characteristics of copper made them much more robust against electromigration, so we bought ourselves a couple of generations of time. At 28nm and 20nm, the wires are now thin enough that regardless of the chip, they are running at very high frequencies so electromigration is a concern for nearly any type of designer, not just for those who expect their chips to last 10-plus years. It’s a concern for those who expect them to last one to even five years. It really gets down to the scaling of the geometries and why it’s such a concern.

Smaller nodes magnify electrical effects
When the design moves to advanced nodes, reliability becomes one of most important challenges. Reliable chip operation increasingly is affected by environmental conditions, such as electrostatic discharge (ESD), electromagnetic interference (EMI), and soft error rate from radiation (SER), and these things could even damage devices on a chip, according to Tianhao Zhang, senior product marketing manager at Cadence. “In the meantime, the multiple power domain application requires the appropriate signal protection to make a device work, which is more susceptible to ESD.”

Arvind Shanmugavel, director of applications engineering at Apache Design said in terms of electromigration, the single biggest driving factor for making things more complicated is process migration. “What we have noticed over time is the transistor drive strength has almost remained constant over the different technology nodes, meaning they can push out the same amount of current from 65 to 40 to 28 and even going down to 20nm, but the wire geometries have decreased over these generations. The wires have become thinner and they have decreased in overall geometry sizes and the EM limits for these wires have also decreased over these different technology nodes. The EM limit is essentially how much current can be pushed to a unit area of metal for a particular technology node. This depends on the metal properties and so on. We have noticed that those limits have also decreased with technology migration.”

ESD on the other hand, is an event-based failure. Technology migration as well as design styles have affected ESD design. In terms of technology migration, ESD needs to be designed within the operating window of device breakdown and normal operation. “As we move from one technology node to another, our device breakdown characteristics have drastically decreased, meaning that the drain-to-source breakdown, the gate-to-source breakdown voltages have drastically decreased but the operating voltage of ICs has not really changed that much,” he said.

Interestingly, Mentor’s Robertson said some fabless semiconductor companies aren’t necessarily so concerned with reliability of chips over a 5- to 10-year span and equate ESD failures to yield issues/the cost of doing business. ‘It’s a hard problem so we’re willing to lose a couple of percent due to this simply because it’s difficult to verify or difficult to protect against.’ However a greater and greater portion of your circuit is going to be susceptible to ESD failures. The oxides of your transistors are so small these days that it’s not just a human with a large piece of static electricity that’s a concern, it is potentially what we would consider rudimentary voltages in the past not dissipated correctly and blowing the oxides of a delicate 28nm or 20nm oxide. A larger portion of the chip could fail due to these events and so there’s been a push for new techniques.”

New techniques fall into a couple of camps, none of which are really new. “Since the beginning, we’ve always been able to simulate. We could always run circuit simulation for electromigration or ESD. The problem, however, is as these chips get bigger, this really requires a transistor-level simulation, and transistor-level simulators cannot accommodate today’s chips because of the size of the designs–multi millions, billions of transistors. In order to do this appropriately, you need a transistor-level simulator. Even the best Fast SPICE tools are not going to accommodate today’s designs. And static timing, while people are doing full chip static timing sign-off, with these ESD, electromigration issues many times you need to go down to the device level. At 20nm, you need to have even more stringent rules that identify what’s possible or not [with EM] and I think you have to be more sophisticated with your analysis. For ESD I don’t think it changes all that much because you’re trying to find out which are the sensitive devices and what they can tolerate, and then if there are protection devices that will accommodate the charge or currents that are possible. It’s essentially a math problem.”

Cadence’s Zhang said a new industry approach called design for reliability is emerging, which consists of adding more protection to minimize or even solve the impact of ESD and EM. However the verification this protection is extremely challenging. Right now most of design houses do the verification manually by experts, which has the significant risk of missing design flaws.

Cadence, Apache, Mentor Graphics, Synopsys and others provide tools here to help designers automatically verify their designs.

Looking ahead
Solving full-chip challenges for reliability are very interesting because, “when you put more components on the same die or when you put more dies in the same package, you’re affecting the reliability behavior of that system,” Apache’s Shanmugavel said. “With IC integration, for example, we have seen a lot more IPs being integrated on the same piece of silicon and that really effects the ESD design of the full chip. Because every IP has its own power delivery network and for each PDN, we need to have ESD protection devices protecting the power, the ground and the signal nodes associated with that particular domain. With the increasing number of IPs being used today comes an increasing number of voltage domains. Similarly with the increasing number of voltage islands for low-power design comes a higher complexity of verifying ESD protection for all these domains.”

ESD has to be verified not only on every domain but must also be checked cross-domain. This means that between every power domain and any other domain on the chip, there must be some kind of an ESD protection to make sure that there is a reliable discharge path of current during an ESD event. “This is no longer possible by visible checks. ESD is one of those art forms where people have visually looked at a layout and qualified that it’s ESD ok. But that’s no longer going to be possible—it has to be translated into a rule-based check and not just an art form,” he explained.

“The ESD limits have not really changed over time — it’s the same ESD standard that we’ve been using for the last 25 years but the geometry sizes have obviously gone down quite significantly, so pushing the same amount of ESD current through the geometries and the geometry sizes going down, there is a higher propensity to metal burnout. That is a huge aspect in terms of ESD verification that has to be available in your analysis platform,” Shanmugavel concluded.

By Ed Sperling
The move toward stacking of die has always been a series of disconnected pieces and vague promises for the future, but in the past few months the scenario has changed radically—and so has the commentary.

All three of the Big Three EDA vendors now have at least some of the pieces in place for 2.5D stacking and are working on a full 3D flow. Two of the biggest FPGA vendors, Altera and Xilinx, have rolled out 2.5D prototypes. The big foundries have developed processes and interposer technology. And IP vendors are beginning to talk about how IP will have to be characterized to work effectively in stacked-die configurations.

Unanimous vote of confidence
Possibly the most dramatic change has been at Synopsys, which has been vague about stacked die for the past couple of years as it tried to sort out where the issues were and where the opportunities will be.

“For some time, the situation has been very foggy,” said Marco Casale-Rossi, product marketing manager for implementation platforms at Synopsys. “We decided to let things settle to understand the main directions, and believe that over the last 18 months we have understood where mainstream will be—2.5D with an interposer. It will be a number of die, side by side, communicating through an interposer and with the outside world through a TSV.”

Synopsys has decided to focus in three areas: a complete solution for implementation and verification; an evolutionary 2.5D to 3D flow that builds on what already exists; and an R&D commitment with customers and research groups to solve whatever problems may come up in the future.

“Extraction will be very important,” Casale-Rossi said. “We need to take into account a number of new elements such as microbumps, TSVs and interposers. And historically, EDA tools have been designed to deal with one process technology at a time. Now we’ve got bricks manufactured using different process technologies and the rules are different depending on the die.”

EDA’s next big thing
Synopsys isn’t alone in trying to predict where the pain points and the opportunities will be. Both Cadence and Mentor Graphics threw their support behind stacked die over the past couple of years, and Cadence has been working on system-in-package since the beginning of the millennium. So far it appears that the opportunity is large enough and broad enough that there isn’t much overlap.

Cadence has built its 2.5D suite from its SiP tools, which were introduced in in 2007 at a time when the market was still focused on planar ASIC solutions. At that point, the company was divided over whether stacked die would really be an opportunity going forward. There is far less doubt these days that it was the right choice.

“The big question as we got into 3D was whether we build separate tools or use the same tools,” said Samta Bansal, senior product marketing for SoC Realization at Cadence. “We did need new layout tools because of the new electrical features—TSVs and microbumps. The analysis tools also have to be able to comprehend the new constraints, which are thermal and mechanical. And we needed new models and tools with respect to microbumps, and had to make sure the current tools understand the new dimensions.”

She said TSVs are similar to vias, but still different enough to require changes in the tools. And floor-planning requires understanding of placement in a stack to optimize behavior. But she noted that what customers discovered they really needed were tools for packaging.

“Customers that are developing 2.5D are looking at this one of two ways,” she said. “One is a package-driven flow, where the interposer is an extension of the package substrate. The other is an IC-driven flow, where as you go along you have more TSVs and more IC-centric routers. But for both of them, 3D stacking is a combination of digital, custom (analog/mixed signal) and the package.”

Mentor Graphics likewise has been extremely active in 2.5D, with a long-range view of 3D stacking, focusing in particular on both test and manufacturability.

“Several factors need to be addressed,” said Steve Pateras, product marketing director for Mentor Graphics’ silicon test products. “One is known good die. How good is the testing before you put chips in a package? Most times you test chips after they’re already in the package, but with 2.5D and 3D the yield goes down as you increase the number of die.”

A second issue involves I/O testing—or more accurately, the lack of testing—which takes on new meaning in a stacked die. In stacked die, it’s imperative to test the I/O before the die are packaged because many times it will not be testable after they’re already in the package.

Pateras said one of the approaches being talked about is wafer on wafer stacking to reduce costs, but that makes it particularly hard to test. He said the better approach is die-to-wafer stacking, using a base wafer with everything else stacked on top for greater control and better yield. But that also creates another problem.

“When you stack heterogeneous die in a stack, there is no standard for communication between the die,” he noted. “We’ve solved one problem, which is memory stacked on logic. But we need to develop a 3D test standard and standards for embedded self test.”

On the manufacturing side, Mentor has modified its DFM tools for 2.5D and 3D verification. And most experts believe existing ESL models can be relatively easily tweaked.

What’s still needed
It’s easy to forget that 2.5D and 3D are evolutionary steps with possibly game-changing impacts. While some EDA tools have always been offered well in advance of the mainstream, they are typically behind the chip design teams working at the leading edge of Moore’s Law. At 20nm and beyond, the cost of making chips has become so enormous that leading-edge companies are building upward. And as they do so, they are finding some pieces are missing that will need to be filled in.

“The first thing that’s missing involves the temperature issue,” said Ghislain Kaiser, CEO of Docea Power. “When you stack die together you’re putting more power into a package, whether it’s 2.5D or 3D. You have to manage that. Many times there is no dissipation problem, but you need to have tools to make sure. You need to be able to analyze the dynamic power profile, and right now it’s impossible to make a link between the software and dissipation when you run actual software on the chip. The best you can do is a simple profile.”

One of the great benefits of stacked die, in addition to not having to move analog designs to the next process node, is increased flexibility and options for designers. Teams can stack different memories in different places and they can move functionality from one die to another to improve performance or lower power or both.

“With that freedom you need to do more exploration,” said Kaiser. “But you may have too many degrees of freedom. You need to be able to optimize different chips along price, performance and power. And you need more accuracy. The gate-level tools are not 100% accurate.”

That’s easier said than done, however. There are no standards in the IP world that would allow an accurate comparison between one piece of IP and another. Frequently they are not even measured the same way by different vendors. Moreover, they can vary significantly with different usage scenarios.

That’s typically where standards fit in. Cadence’s Bansal said the foundation to enable 2.5D and 3D is clear, but there needs to be a seamless and consistent way to integrate digital, AMS and the package. “If the routing is not optimized, for example, you may end up with several layers of interposer. That will make the chip much more expensive.”

Data Center Strategies
One of the most lucrative markets for processors is at the data center level. While improving efficiency in mobile devices is a competitive advantage because it affects time between battery charges, inside the data center it is measured in dollars. It costs some companies millions of dollars each year to power servers and to cool them.

That accounts for the rush to add virtualization into data centers, and the rising fortunes of both VMware and Citrix. It also feeds into the private cloud fortunes of companies such as IBM, and the massive reorganization underway inside of Hewlett-Packard. But at the bottom of the stack, powering all of this, there still has to be a processor. And it is the density of processors, coupled with inefficient use of them, which has caused this scramble inside corporate data centers for a way to cut costs.

Water cooling has returned as one way of dealing with excess heat—IBM re-introduced plumbing a couple years ago. A second approach has been to raise the temperature ratings for servers, which Dell instituted last year. But a third approach has been to reduce the overall amount of heat being generated in the first place by adding more efficiency into the data center on a macro scale.

AMD’s acquisition of SeaMicro gives a hint of what’s to come. SeaMicro has created a supercompute-fabric technology—the basis of a mesh network that can pull resources as needed. Virtualization companies such as VMware are heading in this direction, as well, with data-center load balancing. But a mesh network takes that approach one step further, dynamically adding more resources when necessary. This is the goal of cloud computing, and these are the latest pieces to make it work.

So can more energy be saved with that approach than trying to improve the individual pieces. The reality is that everything helps, and everything saves money. But it will take time to sort out exactly how much efficiency is gained by each part, and which investment will pay the biggest dividends. For more information, Mentor Graphics’ Barry Pangrle has taken a deep look at this subject.

For now, the good news is that work is underway to improve efficiency on all fronts. But don’t be surprised when the numbers start rolling in to find a series of rapid acquisitions as companies look to strengthen their competitiveness through combinations of more efficient technology.

Hidden Costs In Advertising
Most people are annoyed when they get cold-called for marketing their cell phones because they’re paying by the minute. But what is less obvious is the amount of power being consumed by the advertisements in free mobile applications. A team of researchers at Purdue and Microsoft found that up to 75% of the energy consumed by the applications is caused by ads.

Of particular interest is the number of “wakelock” and “energy” bugs. Just as there’s no free lunch, there’s no such thing as a free app—unless, of course, it’s open-source and monitored by an independent group with high-minded aspirations. The free apps available for smart phones generally don’t fall into that camp.

A white paper on the subject was published by Microsoft and details the energy consumption of popular games such as Angry Birds, Free Chess, as well as popular information sites such as the New York Times and MapQuest.

This is interesting research, partly because it shows how to detect software power issues, and partly because it shows how users can affect their own battery life even using the best-designed systems.

–Ed Sperling

We define four abstract models in common use today for electronic design—electrical, digital gate, digital RTL, and transactional—and discuss the relationships among them. The new low-power model described by IEEE Std 1801-2009 UPF is introduced, and its relationship to the other signal-level models for digital and analog design is defined. We then discuss the connections between the lowpower model and the underlying physical implementation of a chip, elucidating some of the concepts in the low-power model that are missing from the commonly used abstract models. We define extensions to the electrical/RTL boundary model to support application of the low power model in mixed-model simulation. Finally, we recommend extensions to the existing transaction model to reflect the concepts of the low-power model.

To download this white paper, click here.

By Ann Steffora Mutschler
Assertions. Just the term conjures images of writing boring lines of code to feed into a simulator. But for engineering teams working at the 40nm node, the pain of making sure their verification is complete and accurate is real—and so is the potential for literally melting silicon if something goes wrong. With this in mind, ‘boring’ goes out the window and gets replaced with ‘necessary.’

Assertions have a long history in verification, noted Krishna Balachandran, director of low power verification marketing for Synopsys. “They emerged and became popular about 10 years ago because there was a need to improve the verification productivity. You had tools dealing with the back-end flow that were constantly beating on performance, which is the same with simulation. We try to improve the performance to simulate things faster. In verification, there’s a design/verification gap. Designs are growing faster than verification tools and technologies are able to keep up without putting the undue burden on the number of engineers required for verification or the number of computers required to verify a design. Assertions were a way to boost that verification productivity.”

The driving force behind assertion usage is accuracy. Increasingly the engineering teams that are building power awareness into their designs want to know how to build this into their environment. But they also want to be sure, given the NRE costs and all the rest, that its going to work, observed Adam Sherer, product management director for Cadence’s Incisive simulator tool and secretary of Accellera’s UVM committee. “At 40nm and below, the chips are just going to melt. The industry can’t afford to do anything else. The chips will not close without this—40nm is about the transition point where this really becomes acute.”

Assertions are used primarily to validate the behavior of a design and are also used to provide functional coverage information for a design. They can be checked dynamically by simulation, or statically by a separate property checker tool such as a formal verification tool that proves whether or not a design meets its specification. But there is also some confusion about what exactly a low-power assertion really is.

“The term ‘low-power assertions’ probably can mean different things to different people. From my perspective…an assertion is a particular kind of way of making a statement about something—in particular, a statement about behavior of a design—such that certain values will appear on certain signals at certain times,” said Erich Marschner, product manager for Questa Power Aware Verification at Mentor Graphics. “Typically you use it to define sequences of conditions over time. It is also used more generally to mean checks that are made as part of the verification process. While not all checks are functional, some of them are structural or apply at different levels of abstraction.”

For example, when a design is divided into power domains, those domains must be able to interact correctly. That involves looking at the power states of the system, which domains can be in what power states at what time, and whether there is any isolation or level shifting required because of two domains that are interconnected but in different power states at the same time, he said.

Cadence’s Sherer noted that the bulk of projects today still aren’t using advanced power techniques. “For the companies that are using any of the power aware structures—frequency modification, voltage levels, power shut-off, or any of those techniques that are very focused—all of those have very specific triggering activities. They have specific signals that set up the condition by which the power is going to change and to set a recovery from that power condition. That’s when assertions start to come in because there are two aspects that our users are very concerned about. One is, for a given power domain, is that being affected correctly? Did I set it up correctly? Do I recover correctly? What are the input and output signals? Are those being properly sequenced? And that is a key thing—that it’s properly sequenced.”

For an engineering team that may have just one power domain, their first power shut off can probably manage by hand, he said. “The assertion is good, but you can look at the waveform tool and you can probably figure it out. But if you have three or four power domains and they are overlapping and some of the signal triggering is coming from software, some of it’s coming from hardware (obviously they are all manifest in hardware), now you have an interesting dynamic that may go beyond casual observance in a waveform tool or human proof point.”

Power-aware simulation tools contain a collection of these checks, with a large number of the static checks done by analyzing the structure of the power intent that’s described in the CPF/UPF and comparing it to the power states that are defined in CPF/UPF. The power states report what states various domains will be in, the structure of the design dictates which domains are connected to which other domains and other parts of the UPF specify whether isolation or level shifting should be inserted in certain places.

By comparing all of this and analyzing that information, the engineering team can tell whether the isolation and level shifting has been inserted in all the right places for all the possible power states that have been defined in UPF/CPF, Marschner explained.

“To verify an assertion you really have to have full functional information about the design. One of the interesting problems with low power is that, depending upon the level of integration, you many not have all the information necessary to do the verification—or at least the static analysis of all the possible behaviors, which is usually how assertions are used in a formal context. This is especially true if the low power activity is driven by software ultimately,” he added.

What’s Next?
To leverage the full strength of assertions and their role in a low-power/power-aware design methodology to improve the accuracy of verification—particularly below 40nm where things get really painful—the industry must bring some pieces of today’s verification technologies rather than continuing to look at verification as a standalone process.

In-situ verification with power intent could be a way to go in the future in terms of bringing different technologies together, suggested Vic Kulkarni, general manager and senior vice president of the RTL business group at Apache Design.

In the case of Apache’s RPM technology, he explained that it was disparate groups within the front end and the back end that did not talk to each other creating power budgeting issues. “By bringing a technology that fuses these two worlds together, it brought the front end to influence the back end power delivery network and power integrity and so on, which essentially helped the designers trying to optimize their power grid, for example, instead of over-design or under-design. Similarly, one can think of a scenario in the verification world where people who are doing day-in, day-out verification, the classic verification companies or business units, have to start crossing the boundaries and bringing the UPF and CPF world and the designers intent world together to create the next generation of low power design methodology.”

In the meantime, noted William Ruby, senior director of RTL power product engineering at Apache Design, customers are putting together power regression methodologies. “You used to have functional regressions. Even the power intent CPF/UPF-driven is still kind of functional in nature. But power regressions are all about power consumption. The idea here is that you want to track your power consumption early on in the design cycle before synthesis, especially as you freeze the RTL and then you start fixing functional bugs. Going through the functional verification process by fixing a functional bug, you may introduce a power bug and if you don’t catch it. The power bugs we see are not going to magically fix themselves in synthesis or place and route. At the end of the day you’re going to get a nasty surprise and that’s not something you want to see.”

Whether the vectors are being generated automatically, pseudo-randomly or special testbenches, engineering teams are throwing everything they’ve got at power consumption verification. And for now, that’s about all they can do.

By Ann Steffora Mutschler
Complete and exhaustive verification of low-power designs requires a substantial effort and part of this includes running real applications on the hardware. Simulators fall short as designers realize that the so-called testbenches they create are artificial and don’t necessarily represent typical applications. As such, this is the sweet spot for emulators, also known as hardware accelerators, in the overall verification environment.

While it sounds like a straightforward approach, this industry segment has been anything but.

Hardware emulation was invented as a means to connect a yet-to-be-built chip—the design under test or DUT—to the target system (the testbench) where the silicon chip will eventually play. “This configuration supports testing with live data to some extent,” said Lauro Rizzatti, vice president of marketing and general manager of EVE-USA. “Since the emulation system runs at a lower speed than the real silicon, you have to buffer the two speed domains to avoid losing data via a speed-rate adapter. When an emulation system is deployed this way, the setup is called in-circuit emulation (ICE).”

Connected to this, speed-rate adapters were developed by each emulation provider and typically they were not compatible. Then, around 2000, Ikos Systems introduced the notion of synthesizable transactors used for emulation. The company was acquired by Mentor Graphics in 2002.

The Standard Co-Emulation Modeling Interface (SCE-MI) was first introduced at that time as a way to standardize the communication between the hardware portion running in the emulator and the software portion running in the PC of a transactor.

SCE-MI1 is the equivalent of the “data link layer” of the International Standard Organization’s Open System Interconnect (ISO/OSI) model for networking protocols. SCE-MI2, at best, is the equivalent of the “transport layer,” although all the complexity of a transactor resides in the equivalent of the top three layers, Rizzatti said.

“SCE-MI2.0 raised the abstraction level of the communication scheme between the hardware and software (using mainly DPI calls between C and SV). But it still did not address the way hardware and software were developed to create the fully synthesizable transactors, and ultimately failed to address the way transactors were simply used in a C or a SV testbench. SCE-MI2.0 does not guarantee any compatibility between platforms. No other layers are defined by SCE-MI. This is probably the biggest challenge, since the communication layer is actually defined in the SV standard with DPI,” he pointed out.

Rizzatti compared transactors with verification IP (VIP) for complex software and hardware. There is no standard to create VIP, whether it is synthesizable (transactors) or not. For example, VIP from Cadence is unlikely to be compatible with VIP from Synopsys, despite complaints from large customers.

“There are two levels of transaction issues here,” explained Erich Marschner, product manager for Questa Power Aware Verification at Mentor Graphics. “One is the transactor that maps from records representing transactions to pin wiggles on the bus. This generally involves code that is synthesizable and therefore can be loaded onto an emulator. There shouldn’t really be any reason why you can’t share that kind of code between different emulators from different sources because it is basically the same as what you would run in simulation. As far as I know most of the VIP that we provide and that others provide, at least if it’s open source, can run on any simulator.”

The problem is sending a collection of transactions from the host to the emulator to be executed on the DUT side. That requires a connection between the host and emulator, and it may differ from one vendor to another. “There is a hardware connection there that is being negotiated and that is almost certainly dependent upon the kind of emulator you are dealing with,” Marschner said.

It’s important to understand that it takes no less than few weeks all the way to years to develop synthesizable transactors, depending on the complexity of the protocol. The UART is a simple transactor while the PCIe is a very complex transactor. Each and every company cannot afford such a large investment , which is the reason why the emulation providers need to offer a catalog of transactors, Rizzatti said.

“While it’s not realistic to ask competitors to work together to make the transactors fully compatible, one possibility would be at least to ask them to normalize the API level of each transactor (for each protocol) so that the customers could re-use the same C or SV test bench for different emulation platforms,” he added.

Different companies have different mindsets of what the API could be. Michael Young, director of product marketing for the Palladium product group at Cadence, related the situation to a software giant. “If you look at Microsoft and the API that they offer, in the beginning maybe they have 100 API calls. Now we are talking about thousands. So, can we do that? We can probably do that, but over time each API becomes a customization of a particular environment of all customers. The minimum thing that we want to give the customer is the flexibility and the knobs that they need to create the environments for the best productivity that they can achieve. What we overlay on top of that is what we call the accelerated VIP that would be a pre-cooked, off-the-shelf kind of solution for a particular protocol, so whether it is AXI, AHB or PCI Express, those things will be off the shelf. Then we would give them knobs within that.”

He added that everyone is trying to standardize this, but that’s not so easy.

“The difficulty is really more of a personality than style. Specific preferences become very difficult to resolve when you have multiple companies trying to optimize it from their perspective. Some of the customers that we talk to are looking for some transportability. I think over time the industry will mature and as we participate in the SCE-MI committee those items will try to cover that in the near term as well as the long term,” he concluded.

By Ed Sperling
Talk with any large systems vendor about power modeling and, with very few exceptions, they’re still using a mix of spreadsheets and lower-level models—no matter how far along they are in ESL adoption and in modeling other parts of an IC.

Power has crept up on even the biggest companies, which have never really figured out how to implement it into their design flows. For one thing, the tools are still evolving. But so is an understanding of how to effectively deal with it.

Smaller companies, meanwhile, are just getting a taste of how challenging this can be as 65nm and 40nm become mainstream process nodes. Density, shrinkage, and competitive requirements have made power a critical issue, and while many are used to dealing with power gating and multiple power domains, the complexity of multiple voltage islands, multiple states between on and off and different strategies for maximizing energy efficiency add a mind-boggling array of choices and complexity to designs.

It’s well known among companies in the mobile IC market—those that have the greatest history of dealing with power issues—that power has to be dealt with at the architectural level. What is less well known is that it requires adjustments throughout the design cycle, and the tools even the most advanced companies are using are a direct reflection of that.

“The only reliable level for measuring power has been the gate level,” said Barry Pangrle, a solutions architect for low-power design at Mentor Graphics. “Above that it’s a relative measure. But to take advantage of the 80% impact on power that you can have at the architectural level you want to take advantage of everything you can. For that most customers are still using spreadsheets.”

This approach has worked fine so far. Modeling can be done on spreadsheets as well as being automated. The problem is that it can’t be updated easily, and there’s no way of testing that the numbers are realistic as the design progresses. “You really want a sanity check throughout the flow,” Pangrle noted. “You estimated the block and you need to make sure it’s right.”

What if…
The lack of automation causes other problems, as well. Because most flows are automated to some extent, being able to update various parts throughout the design process are critical. Virtual models, for example, allow changes in software to be reflected in hardware. But updating models manually with a spreadsheet is cumbersome, made worse by the fact that the amount of data that needs to be added and updated on a regular basis is ballooning. Some libraries are now measured in terabytes.

“At 28nm and 20nm, you’ve got to start dealing with electromigration and other effects caused by heat,” said Aveek Sarkar, vice president of product engineering and support at Apache Design. “You need to create models to capture all of these effects, but these models also have to be consistent and they have to replicate what’s really going on at the electrical or mechanical level. You need to understand the parasitics using linear and non-linear models, and then abstract from there.”

Getting those models right is no simple task. And what happens when an IP block is replaced with another IP block, or a signal is rerouted from one memory to another?

“You need chip models that create power models,” said Sarkar. “That’s one of the top integration focus areas according to feedback we’ve received from system design houses.”

Power everywhere
But is one power model really enough? Power is a global issue, and it affects everything from the software that’s written to a virtual platform to the IP blocks that are being integrated into a design. There are two diverging issues. One is that the classic divide-and-conquer strategy is essential for being able to design and verify complex chips. The second is that power budgets need to be fixed, and they can be affected by everything from those individual blocks to the way they are integrated and used.

“Power modeling is key,” said Philippe Magarshack, group vice president for technology R&D at STMicroelectronics. “Otherwise we will never be able to tackle designs going forward.”

He noted that ST has been using dynamic voltage scaling for several process nodes, along with dynamic voltage frequency scaling. Power islands are well understood, as well. But automating the power remains a challenge.

“There are no standards for this,” noted Ghislain Kaiser, CEO of Docea Power. “This is a problem because we need a common way to capture this data and have the same kind of modeling. The most important thing is to get power models into the design flow.”

And because power generates heat, primarily through leakage, thermal models need to be developed in sync with those power models—something that will become critical as stacking of die becomes more mainstream over the next few years.

But internally developed spreadsheets have reached their limit for adding new data. There literally are no rows and columns left for more data. And existing TLM 2.0 models are too far removed from the power/heat to be useful.

“An accurate power model should have no more than a 5% error,” said Kaiser. “That way it can be used to speed up the debug of power management software.”

Power continuity
Another reason for automating power goes well beyond just the technical capabilities of the tools. It has to do with the way designs are created. Designs have become so complex that even the best and brightest engineers can no longer comprehend the whole design.

“What this means is that you may have an issue in power and not even know about it,” said Qi Wang, technical marketing group director for low power and mixed signal at Cadence. “Verification will become a very big challenge in the future. We’re used to doing functional verification. But power verification to measure power consumption needs to be considered, as well.”

In addition, he said that each step along the way of a design, starting with placement, clock tree and routing, need to be optimized for power. That, in turn, needs to be reflected back into other models that have been developed because the changes can affect all parts of the design.

By Ed Sperling
There are many ways to measure power and heat in an IC, and each one of them adds tremendous value to a design. But there are still holes, and those holes are just beginning to get filled.

Power and heat have emerged as two of the most persistent problems in advanced designs, and there is no single or simple way to tackle either of them. Nevertheless, there is at least progress on this front.

“Power is a side of complexity that has many, many dimensions,” said Aart de Geus, chairman and CEO of Synopsys. “We have multiple power domains and we now have states between on and off. How do you deal with that with ones and zeros?”

At the highest level, high-level synthesis can be used to provide generalizations about whether one processor versus another, or one piece of IP versus another will save power. The challenge there is to link those HLS models with other models to make them useful. This has been an ongoing challenge for startups such as Calypto and Forte Design Systems, as well as Synopsys and Cadence. (Mentor Graphics spun off its Catapult C platform to Calypto last year.)

At the lowest level, starting with RTL and even down to the gate, measurements are extremely accurate and useful. The problem is that once RTL code is written, it’s more difficult to change. Providing that kind of information early, and in context, has been a major challenge. Apache Design has created an RTL Power model, for example, as well as an RTL power flow and a chip-package-system model and flow to extract that information early enough to include it in the RTL.

The big missing piece, however, has been even earlier in the design process. What happens, for example, if a processor from one vendor is substituted for a processor from another vendor? Or what if signal traffic is routed one way in a design versus another? These are important tradeoffs at the architectural level, and there has been only scattered progress in this area. That’s partly because most of the complex thermal and power modeling for advanced is still being done with spreadsheets rather than with automation tools.

Docea Power jumped into the market this week with what should be an interesting first step. Its new AceThermalModeler software is aimed at architectural-level exploration and analysis for heat and power. The focus is on early system floorplanning or partitioning, system packaging, integration architectures and power management policies. It’s a certainty there will be other entrants into this space of the next year or two. All of the major EDA companies and their customers have been talking about the need for this kind of technology since designs reached 40nm.

But Docea CEO Ghislain Kaiser said the spreadsheets literally have run out of room at advanced nodes. They cannot handle any more data. What’s needed now is a way of raising the level of abstraction with accuracy, and he says there is an opportunity between the complex algorithmic approaches used for signoff and the packaging data sheets that are too far from reality. It remains to be seen just how quickly this market will ramp up as a result of that, because the next challenge will be to integrate this kind of information—all of it, from the high level to the pathfinding architectural models—into existing flows. That includes companies designing chips, as well as the ESL flows that are created by the Big Three EDA vendors, and the modeling standards groups such as OSCI, which developed TLM 2.0.

All of this will take time, of course. Standards groups move cautiously and large companies don’t make rapid changes to flows that work. Still, the need for more analysis that can be integrated throughout the design process is clearly needed.