By Pallab Chatterjee
Mobile and handheld gaming platforms are gaining lots of attention these days, and from a low-power engineering standpoint it poses a challenge that dwarfs any game played on the devices.

Unlike mobile phones, these handheld platforms don’t have the luxury of trading off between multiple operating modes to extend battery life. Even worse, they have to perform at the highest level of performance for the entire use cycle, while also supporting game sensors and actuators. Consider the new Nintendo 3DS, for example. It features dual daylight-readable auto-stereoscopic 3D displays. The system supports the same button interface as the standard DS, but pays a penalty for the displays.

The initial Nintendo DS, which featured a single screen system, operated for five to seven hours of gaming based on backlight levels. Compare that to the DSi, introduced in 2009, which ended up reducing the operating time to three to four hours. This reduction was not primarily due to the power for the second LED backlit display, but for the graphics processing needed to support the second display. For the 3DS, the performance of the core chipset and the graphics processing was once again increased. The advances in design partitioning, retiming of the input controls and better leakage power management, allow the new handheld, even with the compute complexity of the S3D display, to still provide three to four hours of battery life.

The Sony PSP and its companion product the PSP Lite are also in the long-play handheld arena. The larger battery PSP sports an eight-hour playback life in movie mode, and a six-hour operating life in gaming mode. The smaller PSP Lite targets six-hour and four-hour operation, respectively. The two models use similar graphic and processor cores, but sport slightly different displays and batteries. The main difference in operating performance is the battery.

In the handheld gaming market the target usable life between charges is four hours, and then the unit is in off mode. Most mobile handsets (smart phones, etc.), never utilize “off” as a design state. Instead they have multiple on states, including full power display + RF, text-only display + RF, audio playback (MP3), streaming video support (codecs + RF), camera mode, video-camera mode, and gaming mode. In these phone-based designs, the user interface is through the low-power touch screen and internal gyros. On the gaming handhelds, there is additional tactile feedback to the button controls, and socket-based interfaces (games, media input, display output) that operate at high sensitivity.

These same power specifications have been passed on from the gaming units to peripherals for the consoles. The highest-use wireless peripherals are the Wii controllers. They are targeted at six to seven hours of use on rechargeable battery kits, or more than 40 hours on a set of AA batteries. The replacement controllers and other components to the system – musical instrument controllers, the balance board, etc., must also have this long off-mode storage time and then full-power operations cycle. This has led to the use of a new series of high efficiency DC-DC converters from National Semi and Linear Technology. With the availability of these parts, the Xbox and PS3 wired controllers have started to be replaced by high-performance wireless versions from third parties.

The new wireless controllers, have modern MEMS based position controls, high data rate RF interfaces, and general LED lighting options. The controllers are targeted for 10-plus hours on a charge from built-in batteries. The majority of these controllers have their functionality in FPGAs or small platform ASICs, and utilize linear standard parts for sensor control and power management. This partitioning allows them to address both the price point and the power cycle requirements.

By Pallab Chatterjee
Design partitioning for power in an IC is driven by which functions are on simultaneously. The new generation of “smart” power management chips introduces new constraints to the task.

Case in point: The new LP8725 from National Semiconductor. These chips have multiple DC-DC converters and both analog and digital low-dropout regulators (LDOs), with a common I2C interface for control and thermal management.

Single chip regulators mean that SoC designers have to account for peak power available, channel-to-channel matching on their power grids, data- and operation-dependent dropout on the various LDOs, and timing for the startup/shutdown of the power regulation that drives the SoC. The logic and ESL tools that work on lowering dynamic power by creating voltage islands, switched/gated power and reduced operating voltage levels make the assumption of stability and availability of these global signals. The IC tools work on the design considerations from the bond pad IN towards the logic and I/Os. And the new power management chips, due to their multi-function and multi-channel characteristics, make the design if the SoC external power source is part of the SoC design architecture.

Portable and multimedia designs have multiple modes of operation to extend battery life. The operations generally require several high current paths (600mA+), some mid-current paths (250mA+) and some low current paths. To accommodate these current levels, the SoC block partitioning needs to manage the peak current available with a tolerance, not just an IR-drop specification.

The current limits have an associated voltage dropout and absolute target limit. On the voltage targets, +/- 2% is a typical level. On the voltage dropout, levels below 200mV are considered aggressive. With target operating voltages in the 1.2v to 3.3v range, this dropout can be a significant delta in the supply. It is important to make sure that the power-down blocks have both signal tolerance to support these dropouts without either switching into the “powering down” sequence or losing information that has passed thru by reloading from non-current state retention registers.

The timing loop for power-up and power-down inside the SoC now has to accommodate “system power modulation” as additional states. To extend operational and standby time for portable devices, the various regulators can started and stopped. This function is generally controlled by state and operational logic contained in the SoC.

There are two major challenges with this design. The first is making sure data and logic that control portions of the regulator system are part of shutdown blocks that might put the design in a non-functioning mode (such as a block being turned off, which controls a regulator that is off, and not getting the control loop closed to restart one or more of the blocks). The second is the timing loop for restarting a shutdown block. The timing has to include the I/O time through the package to the board level, onto the data load and turning on of the regulator block, the stabilization of the supply, and then the completion of the block restart inside the SoC. The external portion of the loop, including the time to stabilization, can take a millisecond. This extended turn-on time may affect the transient power use in data retention and reload logic, as well as on tri-state circuitry that is waiting to turn on. These same constraints affect SoC block turn-off, as well.

If the end system, primarily portable systems, are going to use these centralized control blocks, the power grid design and application has to take into account the interconnected nature of the power rails external to the SoC. The benefits of centralized dynamic control of the application power, as well as the ability to thermally monitor the use and distribution, outweighs the added design task. These new power management chips are key drivers for low-power systems and their feature set is growing rapidly.

Low-Power Design sat down with Richard Zarr, chief technologist for the PowerWise Brand at National Semiconductor; Jon McDonald, technical marketing engineer in Mentor Graphics’ design creation business unit; Prasad Subramaniam, vice president of design technology at eSilicon; Steve Carlson, vice president of marketing at Cadence Design Systems, and David Allen, product director for power at Atrenta. What follows are excerpts of that conversation.

By Ed Sperling

LPD: How important is it to be green?
Zarr: In the past, when our customers plugged something into the wall they didn’t care. They pushed the problem off. But with some of the legislation, people are starting to care. No system is ever loaded 100% all the time. Even data centers are not always busy. Typically 50% to 80% of the power is wasted. They’re running at high speed and consuming power when they don’t need to be. But they’re not doing anything about it because it’s adding complexity or it’s adding cost. You’re designing the hardware, but someone is taking that and using in ways that you didn’t design it.
Carlson: I wrote a paper on the effects of virtualization. One of the things they would do in data centers is offload the servers, but the servers would have to go into standby mode when they’re not being used. They didn’t stand-by very well because they were never designed to stand-by. An improvement in the architecture at the macro level would be a big benefit, but people aren’t doing that unless they’re forced to do it or unless it becomes a competitive advantage.
McDonald: Where people have been investing the time—in the handhelds and at the micro level and device-level optimization—we’ve squeezed a lot of benefit out of that. Things can be made better, but a lot has already been done. At the macro level, almost nothing has been done.
Allen: The great thing about the handhelds is they’re proof points that it can be done. There’s a lot of work going on in the networking companies now, but you’ve got to start at the IC level. Once you’ve got the infrastructure there, then you can start layering on energy efficiency in the lighting, the HVAC in the data center and controlling of peak power.
McDonald: Cisco did a study in 2006 where they determined that if they saved 1% on the power for a network router it was the equivalent of taking tens of thousands of cars off the street. But when you’re designing it, no one cares. They just want to get it out the door and meet performance.
Zarr: Education is a big thing here. Designers are not educated in the vehicles to reduce the power consumption in their designs. It hasn’t been a priority for them.
McDonald: It’s also the delayed benefit. It’s not a benefit to the designer or even the company making the chip.

LPD: If it came down to hitting a deadline for getting a design out the door or cutting power, what’s the likely response?
Carlson: In the case of a very large printer company, it’s getting the chip out the door—even if it ultimately costs more money.
McDonald: Power is not really what most people care about up front. You care about the economics. You care about power only insofar as it affects the economics.
Zarr: It may have more of an impact as we go forward.

LPD: What happens if we trim the margin in designs? Do we gain power savings?
Carlson: There’s incredible waste. If you look at design methodologies for front-end design teams, there was a 5% margin. Now it’s typical to see 20% to 25% margin. One company we’re working with is going to use a 50% timing margin on the design for a battery-operated application. You start to explain what the impact will be on the overall logic architecture and the response you get is, ‘I hadn’t thought of that.’ You need to look at timing and power together. That’s where the real increases in margin occur.
Subramaniam: Margin is an issue, but it’s even more than that. Today we’re overdesigning chips because we are designing for the worst-case scenario that may never occur. So how do we take advantage of the process itself? You need to monitor the chip and lower your voltage accordingly. You’ve designed the chip for the slow corner, but you know that in normal conditions the chip is going to work much faster.

LPD: We’ve been adding cores and power domains on a regular basis. Now we’ve got a bunch of this stuff. How do you manage all these pieces?
Allen: You need to start at the architectural level. You can’t retrofit designs on the chip. There are a small number of power architects who can do this. They understand what the tradeoffs are, and from an EDA perspective you have to arm them with the right tools.

LPD: How small?
Allen: At ST there might be four. At TI there might be a half dozen. Maybe that’s enough. You don’t need a whole new power architecture for each derivative. You need a power architecture for the first one, and then you may get 30 or 40 derivatives out of that. But can every small company afford to have one of those guys? No. But big companies do have this expertise.
Carlson: There are sources of expertise to bridge the gap.
Allen: With external expertise, there’s a question of how much the design team learns.
Carlson: It depends on how you structure the engagement. If it’s a turnkey operation, they’re not going to learn much. But you can also teach them how to fish.

LPD: Do we ever get to the point where it’s no longer economical to do this stuff?
Subramaniam: You can probably go quite low on voltage for digital logic. We had a customer running digital logic at 600 millivolts. They could afford to do that because the chip runs at a very low frequency. If you’re willing to go with low performance, you can go to very low voltage on digital logic.
Allen: We’re not quite at the end of this road. Another thing to think about is how much charge is in a battery. That’s not really going to change that much. But there is still a lot of potential for architecture at the high end of the spectrum. Those guys can probably learn a lot.
Zarr: Even architectures that scale frequency will find benefit.

LPD: Is there a limit to how far down we want to go down the Moore’s Law roadmap, though?
Subramaniam: There is definitely a tradeoff. Only those with high-volume products will be willing to go to the next step.
Zarr: You never know until the next materials come out. They’re just continuing with strained silicon techniques and SOI.
Subramaniam: There are still a lot of designs done in 0.25 micron and 0.18 micron today. TSMC has not retired a single process since its inception. People will be willing to go back to older nodes if it helps them, but it doesn’t really help with power because they consume more power.

LPD: How do more restrictive design rules affect all of this?
Carlson: That will drive a renaissance in architecture. The process guys will quit solving the problem for you, and you have to be more clever about everything. You can’t just say you’re going to use the next-generation LP process and think you won’t have a problem with it.
Allen: There have been a number of times where the design guys said, ‘Leakage is going to kill us,’ and the process guys said, ‘Don’t worry about it.’ Then it scales to the next generation and it’s something else. The process guys may save us, but they won’t be able to save us forever.
Zarr: Somewhere along the line we’ll have to change materials, whether it’s carbon or something else. Everyone’s trying to avoid making that kind of investment.

Low-Power Design sat down with Richard Zarr, chief technologist for the PowerWise Brand at National Semiconductor; Jon McDonald, technical marketing engineer in Mentor Graphics’ design creation business unit; Prasad Subramaniam, vice president of design technology at eSilicon; Steve Carlson, vice president of marketing at Cadence Design Systems, and David Allen, product director for power at Atrenta. What follows are excerpts of that conversation.

By Ed Sperling

PD: Some of the suppliers of IP have eliminated a low-power version because they assume everything will be low-power in the future. Is that the norm?

Allen: It’s a question of how much time the IP supplier has put into trying to reduce the power. There’s a large body of IP where it’s designed as one monolithic thing, but very often when it’s put into an SoC the whole thing can be shut off.
Zarr: A lot of the IP is on a block, so you cannot dynamically scale it down.
Subramaniam: Some of the IP also relies on a certain level of voltage. You cannot indiscriminately lower the voltage to lower the power. Analog blocks need a higher voltage for noise margin and all their special requirements. Memory is another one of those. Every process has a VDDmin associated with the bit cell. You cannot expect the memory to work below that VDDmin. At best you can split the memory into two power domains and have a power domain for the bit cell and another for the periphery. But these things make it more complicated. If all of this increases the complexity by 100% and increases the risk of not meeting the schedule, I’m going to be reluctant to implement it.

LPD: How real is the risk?
Carlson: A lot of the risk is perceived risk. Faraday did a study where they took out 20 chips of increasing complexity with some analog content mixed in. They found they were actually closing faster using some of the advanced automation techniques for low-power designs. Doing a big SoC is complicated, no matter what. Adding another power domain doesn’t double complexity. What people have to do in power grid design and analysis is already hard. You have these analysis loops and you’re specializing in power. There’s plenty of experience behind this to say, ‘It can get done and it can get done efficiently.’ It’s the people who haven’t done it who say, ‘ I don’t know how to do it and I don’t know what the impact is going to be.’ And by the way, it’s 2008 to 2009, and I’m not going to do anything that increases risk. No manager is going to put their program on the line with something they’ve never done before for an unknown benefit.
McDonald: My customers push that problem down to the implementation side. They’re worried about pulling enough of the system together to accurately characterize the workload. Using large blocks of IP is a good example. One of the customers we dealt with recently had a large graphics processor. They had designed it and it worked great, but they couldn’t use it in the SoC because it killed the power consumption. They didn’t have the modes available to control it and turn it off when it wasn’t needed. The guys who designed the graphics processor had no idea how this thing was going to be used. They needed to have the foresight to put in the controls to be able to turn it off.

LPD: So that graphics processor was being designed for multiple applications?
McDonald: Yes, and if it has multiple applications how it needs to be designed from a power perspective is completely different.
Carlson: I agree. You need to be overlay different power structures.
McDonald: If you can overlay those using the same core function and changing the power characteristics, that becomes very valuable. But the tools aren’t there to do that today.
Allen: The modeling languages aren’t quite there to do that today, either. An IP supplier may have in mind several different ways to configure the power strategy, but a user of the IP can’t come along and arbitrarily impose their own. They don’t have enough information about what the IP actually does. If analog is required to maintain a certain voltage, and a processor designer or IP supplier knows there are three different blocks that could be independently powered, they need to be able to present a menu of the available ways to configure it. Both CPF and UPF are starting to represent that as a list of possible configurations.
Carlson: It’s an orthogonal purpose. You may want timing constraints and power constraints to go hand in hand.
Allen: Right. So what are the possible different ways these things can be configured? The IP suppliers have been requesting this, and they’re driving these IP standards in that direction, but they’re not there yet.

LPD: Is there a minimum amount of battery life customers are asking for?
Zarr: There are two requests we see. It’s not battery life in particular. They’re looking for other things in handheld devices. One is thermal management, and they’re running out of vehicles to do that. Battery life is part of that. The other one we’re seeing, which is even bigger, is total power dissipation. In infrastructure types of applications, where there’s a lot of processing power, people are hitting the limit of how to get the feed out of the device or the current in. There’s also legislation being pushed for data centers to get power consumption down. They’re running out of simple approaches, so now they’re looking at architectural approaches to say, ‘What can we do to redesign what we’ve done in the past to lower the energy?’ One is frequency scaling or clock gating. What’s interesting is it’s not as much of an issue with the small handhelds as the larger power consumers.
Allen: The middle of the spectrum doesn’t care as much. It’s the low-power and high-power guys who care.
Carlson: What we see, irrespective of where they are on the spectrum, green is competitive. I haven’t talked to anyone doing 65nm or below who doesn’t care about power. Some of that can be mitigated just by going to a low-power process.
Allen: The corollary question is whether anyone would delay their tapeout if they didn’t meet their power budget. A lot of people say, ‘No.’ They’ll delay for timing, but if they had a 2-watt power target or a 10-watt power target and they knew they were going to miss it, they would still tape out.
Carlson: This is an area that really needs improvement, too—the way the specs get done. In timing we have to meet the specification. In power, it’s 50% or more. There’s a printer company that didn’t meet the envelope, so they added in a $1 heat spreader. That’s 50 million units, but when they got the chip back they found out they didn’t need the heat spreader, so they wasted $50 million. It’s overdesign. We used to have this in performance. Now we have it in power.
Subramaniam: People only think about timing and performance as their No. 1 goal. Power is never considered a primary goal in any design. We see the problems more on the high end of the spectrum. At the low end, most of these handles can be turned off, so leakage power is the problem. At the high end, you don’t have too many choices about turning off portions of the chip. In supercomputers, graphics accelerators and telecom chips, performance is the No. 1 criterion. Power is secondary.
Allen: The low-power design guys have been dealing with that. At the high end of the spectrum, they’re just starting to deal with green laws and the cooling problems in data centers.

Low-Power Design sat down with Richard Zarr, chief technologist for the PowerWise Brand at National Semiconductor; Jon McDonald, technical marketing engineer in Mentor Graphics’ design creation business unit; Prasad Subramaniam, vice president of design technology at eSilicon; Steve Carlson, vice president of marketing at Cadence Design Systems, and David Allen, product director for power at Atrenta. What follows are excerpts of that conversation.

By Ed Sperling
LPD: What’s the big problem in low-power design?
Subramaniam: The biggest issue is that power has to be done at the architectural level. Most of the time people have their architectural design already finished and then they try to optimize power. They’re already too late in the game. They’re going to get some optimization, but it’s not enough.
Allen: It’s practically impossible to retrofit power domains into an existing design.
McDonald: That’s where the big gains are. You have to tune the hardware and software to the workload. Then you can save a tremendous amount of power. At the RTL level or below, the most you can hope for is about 20%. That’s stripping out gates. When you go process node to process node, you get a little bit of a savings, too. But the big gains are when you change the architecture and the way the system works. That’s where everyone’s struggling right now, because to get there you have to have good architectural models.

LPD: Is there resistance to that among design engineers?
Allen: There’s a big hurdle to get to your first power domain design. Chip designers in the 1980s and 1990s were trained to deal with global power. To get to the point where you have two power domains is a big hurdle. We have to help people get over that hurdle. Once you get to two domains, you can accept the risk and go to five or more domains and get these really big savings.
Subramaniam: Even at the architectural level people are reluctant to use multiple power domains in their design because they don’t want to complicate their system.
They don’t want to have multiple voltage regulators. A chip already requires two voltages, one for the I/O and one for the core. They don’t want to go beyond that. We need to get that mindset changed.
Allen: That’s certainly a hurdle. But it’s possible to do a multiple power domain design where blocks switch off. Once you have multiple power domains, you can get huge power savings by turning off blocks in your design. That doesn’t complicate the board design, but it does complicate the chip physical design.
Zarr: There is always an issue of moving between domains, especially if there’s dynamic scaling. You need level shifting or isolation cells.
Subramaniam: Level shifters are designed to go one way, either low to high or high to low. You need to take extra pains to make sure level shifters can go in either direction. You may be operating on two power domains, and either one of these can go lower than the other. The level shifter has to be able to manage that.
Carlson: It’s still a small percentage of designs that are taking advantage of all the techniques that are available. There is the educational component and there’s also a risk component. People don’t understand how to do it, what the impact will be on the methodology, and when they start looking at the risk they’re not sure what they’re going to get in terms of a payoff. They know energy efficiency is becoming a competitive imperative, but time to market may be more important than battery life because they can re-spin and refine over time and take advantage of an LP process next time.

LPD: Still, isn’t the real key writing software differently to take advantage of individual cores?
Carlson: There’s a non-obvious tradeoff. There’s a 1000 to 1 efficiency gain in the software versus the hardwire. There’s leakage issues, and all of this is non-obvious. It requires looking deep into your target process.
McDonald: There are two levels of problems. One is the details of the implementation—the level shifters and what it takes to actually implement the power domains and be able to shut things off. Then there’s the tradeoff of what that means. If you don’t really understand what your architecture needs to do, then it’s difficult to know what you can take advantage of and what the benefit is.
Carlson: Yes, what’s the overhead of the level shifters and the isolation logic and the power switches? What’s the reliability impact? And how does that compare to another strategy that might offer the same power? What’s the relative cost and the schedule difference?
Subramaniam: People are looking for a simple solution. One of the reasons multiple power domains are not generally used is it’s too complicated. The simpler the solution, the easier it is to implement, both in terms of physical design and architecture. People are trying to figure out what is the best simple solution that can optimize their power. Even though these techniques are available, people don’t seem to be using them because they’re just too hard to use.
Allen: There is a lot of risk. People would like to push clock gating to another level so they don’t need to go to multiple domains, but that approach runs out of steam.
Subramaniam: People are relying on the tools to do the job. Here’s the RTL, let the tools do the clock gating and manage the power.

LPD: Is there any model that can encompass these kinds of complexities?
Carlson: Yes. You can specify different power strategies across your chip and estimate the impact, both from an overhead and a power-savings standpoint. And you can do this very early in the process. You can address floor planning, different voltage levels, shutoffs, and frequency scaling, and you don’t need to be a power expert to figure out what the tradeoffs will be. At the TLM level, you have to start figuring out what effect this will have on the functional aspects and look at the contours of the dynamic voltage.
McDonald: But the static side does tie into that, as well. You need to know where you can shut it down.
Allen: When we work with some of the cell phone manufacturers, there’s a power architect guy, and that guy uses a tool like this to make these tradeoffs.

LPD: Let’s do a reality check. What do the chipmakers think?
Zarr: I work directly with our customers that implement our technology, which is adaptable to voltage scaling. It’s a dynamic voltage scaling technology. The first issue we find is people don’t want to create voltage islands. They want one voltage and they want it simple. Once you get over that hurdle, the next problem is integration of a lot of third-party IP that’s not compliant with this type of architecture. One thing that we need to fix as an industry is to ensure IP blocks have the ability to sit in independent voltage islands. One of the big offenders is RAM, because RAM has a problem with retention at lower voltages. You always have to isolate RAM, and in most of the systems I see RAM is very important. Maybe it’s a standardization, or maybe it’s an option that companies provide in their IP.

By Brian Fuller

The nation’s power grid hasn’t been upgraded in a century, but suddenly there’s a sense of urgency.

In high-profile meetings from Washington to Santa Clara in the past two months, industry executives, scientists, engineers and government officials have ratcheted up the dialogue about modernizing how energy is generated, distributed and used. The movement, helped by an expected $4.5 billion in government stimulus money, has its roots in the national concern over fossil fuel resources and heightened focus on energy efficiency.

“They’ve moved really fast throughout the month of April and May,” says Lucian Ion, strategic marketing manager for smart grid and energy technology solutions at National Semiconductor. “There’s a tremendous amount of work that’s public already from substation generation to customer’s home.”

The ideal vision, shared by many, is a truly energy-efficient system in which home appliances talk wirelessly to a device that lets consumers understand their power usage and control their consumption; in which utilities talk to homes to manage energy loads at times of peak demand, and in which utilities better manage the distribution of new, “bursty” modes of power generation such as solar and wind.

Two things make electricity unique and a challenge for smart grid: Lack of flow control and electricity storage requirements

“Change either of these and the grid delivery system will be transformed,” says Dick DeBlasio, chairman of the IEEE SCC21 Group, which oversees the P2030 Smart Grid standardization effort.

Updating a system that has worked well and consistently and remained essentially unchanged for 100 years would appear a daunting, time-consuming task, but participants are taking their cue from the Internet, another complex technology infrastructure that has grown and evolved with a focus on standards.

“The Internet was built on open standards ranging from communications and software protocols to standard microprocessors and memory,” says Adrian Tuck, CEO of Tendril, a provider of residential energy ecosystem technology and a ZigBee Alliance vice chair. “So too it can be with the smart grid.”

The focus on standardization is already yielding benefits. Shortly after a smart grid standards workshop April 28-29, Energy Secretary Steven Chu and Commerce Secretary Gary Locke hosted a Washington meeting with the National Institute of Standards and Technology (NIST) and announced 16 standards that are essentially locked down—no debate necessary.

These include:

• ANSI C12.19/MC1219-Revenue metering information model
• DNP 3-Substation and feeder device automation
• IEC 61850-Substation automation and protection
• IEEE 1686-2007-Security for intelligent electronic devices
• Open HAN-home area network device communication
• ZigBee/Home Plug Smart Energy Profile-Home area device communications.

The second big meeting Intel hosted at its Santa Clara headquarters June 3-5. Closed to the media, it was a forum for government organizations and groups such as NIST and the IEEE to begin to lay the foundations for near-term standardization work.

The goal was, among other things, to stimulate the development of a body of IEEE 2030 smart grid standards and or revise current standards applicable to smart grid body of standards.

“Our goal coming into the meeting was to get the process started and people together and in active dialogue,” says Lorie Wigle, general manager of Intel’s Eco-Technology program.

Intel’s interest is largely based in the fact that its core industry, information technology, accounts for 2% of global energy use.

“There was a really good outcome in the willingness and desire for the companies to continue to talk between meetings to make forward progress,” she adds.

At the conclusion of the meeting, three task forces were formed to tackle the next stage of standards work: Task Force 1 (Power Engineering Technology), Task Force 2 (Information Technology) and Task Force 3 (Communications Technology).

The near-term roadmap, according to NIST’s George W. Arnold, includes the initial phase between now and September in which existing consensus standards (including the 16 identified) are recognized; the establishment between now and 2010 of a public-private standards panel to provide recommendations for new and revised standards to be recognized by NIST; and testing and certification later in 2010.

While there are many existing standards and emerging technologies to work with, there are many unresolved issues.

Gaps in some of the standards—notably IEEE power engineering specs—need to be filled, according to Arnold. These include IEEE 1547 (physical and electrical interconnections between utility and distributed generation), IEEE 1588 (precision clock synchronization) and IEEE C37 (standard electrical power system device function, originally published in 1928).

The third task force’s work (communications) may be more challenging, according to Arnold, who described the communications infrastructure for the smart grid as “the Wild West.”

While most of mac/phy layer standards are IEEE’s, guidance will be needed on their application to the smart grid, and additional standards may be needed as well, Arnold says.

Within the home, ZigBee seems to have emerged as the leading wireless communications factor, although powerline and other approaches haven’t been dismissed.

The interface between the home and the utility, though, may or may not emerge as a point of contention. While it’s generally up to individual utilities to choose their communications backhaul (since they own that customer relationship), there are a number of competing ways to update the technology, according to National’s Ion. These include looking at cellular, WiMax or hybrid mesh/wired configurations—even FM radio, he adds.

“There isn’t a clear standard from how you get it from the home. That’s more of an issue of a biz model of how each utility is able to secure a backhaul spot,” Ion says.

In addition, engineers and industry leaders will be examining how to handle emerging technologies that will add load to the grid—plug-in electric vehicles, for example, that charge in a garage overnight. That requires coordination among a number of standards bodies (see chart).

Security throughout the smart grid will remain a constant as the standardization process evolves. “When it comes to running things on the Internet, things can be hacked,” Ion says. “What regulators, independent system operators and utilities are trying to make sure is that things are mission-critical.”

San Francisco—It’s no surprise that different sections of the electronics supply chain see the low power challenge from different perspectives. But the similarities and differences are changing as the low power problem becomes the driving force behind today’s mobile devices.

At the recent Globalpress event, Portable Design’s editor in chief John Donovan moderated a panel on low power: “Portable Power Management – Dodging Moore’s Law?”

Donovan said low-power design faced a turning point in 2008, thanks to three converging issues: The growth of portal devices, power consumption costs at data centers, and changes in process technology, which are the result of Moore’s Law. A 45nm chip contains more than 400 million transistors, which equals a lot of power generation and dissipation.

Wally Rhines, CEO of Mentor Graphics, talked about system-level power issues in a speech at the event. The focus of this panel was at the chip level, which has a 20% to 50% impact on the overall board-package lever power budget.

One Theme – Differing Views

The first question addressed by panelists involved emerging trends in low power designs.

Richard Zarr, chief Powerwise technologist at National Semiconductor, said a new generation of user interface technology combined with the consumer’s desire for higher bandwidth content will drive the need for increased local processing power in mobile devices.

User interface technology has come a long way since 1983, when Motorola introduced the DynaTAC 8000X – the first FCC approved mobile phone (see Figure 1). This phone boasted an alpha numeric LED screen that was a single row in length. Since that time, phones and other mobile devices have gotten smaller while the displays have gotten larger. The larger, higher resolution displays are needed, in part, to support the customer’s desire for multimedia data such as MP3 music and video streams.

“By 2014, Cisco forecasts that 64% of mobile traffic will be video,” said Zarr, adding that other high-bandwidth applications would include online gaming, where cloud computing will move most of the intensive processing tasks to the server while pushing video to the personal mobile devices. All of this will increase the need for local and remote low processing technology.

Figure 1: In 1983, Motorola introduced the DynaTAC 8000X – the first FCC approved mobile phone. (courtesy of Wikipedia)

Instead of the typical power-to-clock equation for chip power, Zarr used the energy dissipation equation to show how energy (power given a certain amount of delta time) is really a function of process and temperature variations, plus aging and the clock frequencies of the device. This lead-in was tailored to National’s Powerwise Adaptive Voltage Scaling (AVS) products, which addresses – you guessed it – process and temperature variation, plus frequency via voltage scaling. AVS touts energy efficiency by eliminating the need to pre-identify voltage levels via voltage lookup tables for various performances modes.

Next up was Bruno Kranzen, Ultra-Portable product line director for Fairchild Semiconductor. He built upon Rhines’ keynote comment that energy storage technology innovation was at a standstill. According to Kranzen, this means power innovation has to accomplish more while using the same power afforded by today’s batteries. That “more” includes 5.0 GBits/data rate support for USB 3.0 interfaces that are so common on today’s mobile devices. It also means support for 10 megapixel image sensors in today’s cameras, multicore processors, 3D MEMS sensors for touch-screen displays and 8 RF bands, to name only a few of the power consuming technology requirements.

All of these power-intensive features must be met with battery technology that has improved at a snail’s pace, as Rhines pointed out in his keynote presentation. He observed that innovation in lithium-ion battery capacity had essentially stalled, with capacity improvement increasing by less than 5% per year (Figure 2). So how can the electronics industry meet the demand for increased feature sets that use today’s battery technology?

Figure 2: Innovation in lithium-ion battery capacity has stalled. (courtesy of Mentor Graphics)

Kranzen answered that question by taking a system view. He explained that while Fairchild is a chip company, it is collaborating with partners in both the operating system and applications space. He emphasized that merely making energy-efficient chips is not enough. Instead, software designers must be engaged to meet the demands of low-power system. Fairchild’s Mobile Power Systems platform is one way to achieve this end, by utilizing power management hardware components that are tightly integrated with the operating systems and even applications that run on a mobile device.

The final panelist was Pravin Madhani, general manager of the Place and Route Division at Mentor Graphics, who represented the EDA side of the low power equation. Madhani spoke in unison with the other panelists in terms of the need for a systems view for the design of low-power devices. Specifically, Madhani defined the system process as starting with an architectural-level specification that takes into account PCB, package and component-level design. Each step in this process affords different opportunities to impact the overall power budget for a device.

Taken together, the total impact can be significant, with potential power reductions of more than 50%. Mentor’s low-power platform addresses each of these design stages, from optimal hardware architectural design through power integrity and predictability at the PCB level through the capture of the designer’s power intent at the component level via the Unified Power Format (UPF).

Devil is in the details

So what are the real-world applications of these ideas?

Mentor’s Madhani shared his experience with a recent multicore design project in which a graphics company couldn’t meet power and performance requirements for two graphic engines on one core. The solution required moving to a smaller process geometry, in this case 45nm, which afforded significant power savings but with slightly lower performance. The key in this design was clearly understanding the tradeoffs of each scenario, as well as being able to simulate and verify all of the hundreds of operation modes for the chip.

Fairchild’s Kranzen challenged the drive toward increasing number of cores. He said transistor leakage was the culprit, which drastically increased the level of static power drain for multicore designs at the low process nodes. Leakage current is the result of the small amount of current that continues to flow even when the transistor is off. This challenge must be address by device-level physicists and material ngineers.

Conversely, having just a single core is often impractical, since that core must run so fast to perform all of the processor-related tasks that it consumes unacceptable amounts of power. So designers must find the “sweet spot,” which is the optimal number of cores needed to balance the power-performance constraints of their design. One solution is to turn-off unneeded cores. Such an approach requires close operation between the cores and the systems operating system, explained Kranzen. Cores could be turned off by the software kernel, but that activity must be closely coordinated with the Real Time Operating System (RTOS).

National Semiconductor’s Zarr agreed that part of the low power problem must be solved at the transistor device level, probably with improvements with high K dielectric materials and designs. But the bigger challenge is to clearly understand the goal, the intention of a given design. He cautioned that just “throwing transistors at the problem,” as with multicore and/or lower process node technology, is not the best approach. Instead, a top-down architectural solution is needed. One outcome of such an approach would be to divide different blocks of system functionality into different voltage islands to better manage the power usage of the system.

So is the ESL-to-RTL design problem still the biggest challenge for low-power design teams? Madhani believes that most people have a better handle now on low power design, thanks to improved architectural power modeling and better tools to verify the numerous power modes for a given operational scenario.

Kranzen stressed the need to run software models, as well. These models would execute the drivers, OS and application-level code to provide a gauge of related power consumption. Running both hardware and software simulation or co-simulation would provide a system-level view of the overall system power usage.

Finally, Zarr believes the best way to address the top-to-bottom low power design is with an energy tax on the operating system, in other words, placing a real emphasis on energy management of the entire hardware-software system.

The bottom line: The power problem is too big for a point solution. Only a system-level approach that incorporates the co-simulation, co-design and co-verification of both hardware and software will be sufficient to meet the demands of lower-power electronics. This is hardly a revelation, but the growing consensus by EDA and semiconductor companies of the importance of software design in the hardware equation looks encouraging.