Low-Power Engineering sat down to discuss parasitic extraction with Robert Hoogenstryd, director of marketing for design analysis and signoff at Synopsys, and Carey Robertson, product marketing director for Calibre Design Solutions at Mentor Graphics. What follows are excerpts of that conversation.

LPE: What changes with at 22nm and beyond with structures like FinFETs?
Robertson: It’s not only parasitics. It’s also BSIM (Berkeley short-channel IGFET Model) or PSP (Penn State Philips) models. They’re going to have to change, as well. We will start seeing DOE’s this year, including version 1.0 of SPICE manuals from foundries. Is there going to be a paradigm shift? I don’t know. But their aspect ratio is different. We have to respond.

LPE: It’s also a lot more data, too, right?
Robertson: Yes, it’s a lot more data, as well as new dielectrics. We don’t have the full picture about what are the dielectric constants, are they going to be conformal, what are they going to look like. And part of it is what rules are going to be mandated. The more we can constrain the problem to say, ‘This is how you’re going to implement contacts around the FinFET region and you have to do it maximally contacted,’ that’s good news for us. It allows us to constrain the problem. If you want to let designers be as creative as they want, so you have one contact here for the source and another contact here for the drain, that’s great for them but difficult for us to deliver the accuracy.
Hoogenstryd: We’re already working with foundries in that area. It’s going to impact the model and what’s important from an extraction point of view. We seem to have the problems at every process generation and bright people always figure out how to get through the noise—even though it takes time—and model what’s important. One of the challenges for new structures like FinFETS is that as EDA vendors we have to make investments ahead of the curve. This is an area that is potentially costly. Customers want us to experiment with them at our expense. Hopefully by the time things get settled, they want us to be there with commercial solutions. But we still don’t have it as bad as the litho vendors. The lead time on getting lithography ready for production is long, and there’s a lot more experimentation at that end. They may take 20 different approaches knowing that one or two will work out, and they want all their suppliers to investigate with them.

LPE: How does 3D stacking affect parasitics?
Hoogenstryd: From a practical point of view you can look at each chip, but instead of between packages you now have things like TSVs (through-silicon vias). You have to model that. There’s a lot of investigation about what’s going on between the TSV layers and the bottom side or top side of the chip that’s being connected. People are not convinced yet that the economics are there for this to be a mainstream packaging solution. There are a lot of companies doing investigation and test chips.
Robertson: There is a modeling issue beyond the traditional metal stack. It can be accounted for. But it’s not just the interaction of the various layers. It’s also what is the model of this TSV. It could be modeled like a MOSFET. It could be modeled as a parasitic. But its geometries are much different than the interconnect around it. There are inductive effects that most customers are not taking into account when they develop standard chips. Unless you’re in analog or mixed signal you don’t really think about the magnetic field. TSVs have that. There’s also a big netlisting and integration issue. If you’re compartmentalizing and building things up and here’s a memory above a core to get the proximity benefit, you can model them differently with some interaction. But when you try to do critical-path analysis and that path spans multiple TSVs, you need an extraction that will span different die and potentially different technologies if you mixed 65nm with 40nm. Where this may go is, if customers are designing L1 and L2 cache among four dies and getting the extraction/simulation done correctly, that is going to have profound impact on the entire infrastructure. That includes extraction, netlisting and simulation. That is probably very cool for the designers.

LPE: Is heat a big problem with that?
Robertson: Thermal is a big deal. The other problem on the device extraction side is stress. How big of a contribution is silicon stress? And as we get to TSVs, stress is an even bigger problem. Stress impacts both leakage and power consumption. Sometimes it’s beneficial and sometimes it’s not. So both stress and thermal are going to require more of a focus.

LPE: So looking out ahead what are the big problems that were likely to encounter at 22 nm and beyond?
Hoogenstryd: We’re already in the midst of 32/28 nm modeling. We’ve been working on that for quite a while. I don’t think the work is quite done there because this node is not in full production. There is constant work going on at the silicon foundries. They find new things they need to model to get a more accurate silicon representation. We’re already working with some foundries at 22nm, where the FinFET is going to be first introduced. It’s that constant challenge of keeping up with the modeling. The 3D IC has some implications on the modeling. Another challenge is just helping customers be more efficient. Right now the pressure on the design team of doing a bigger chip with the same resources is a problem. The answer is not throwing more CPUs at a problem. Capacity is in many ways a bigger issue than CPU runtime. These chips are bigger and you have to run your software in the same memory footprint constraints. And it’s working more with customers to focus beyond this one tool.
Robertson: What customers have been saying is they want more accuracy. Even though design is getting more complicated they can’t deal with capacitance and coupling capacitance. They want more accuracy even with all those challenges. Both Synopsys and Mentor have initiatives to change the way we do extraction and bring in field-solver technology to have the best accuracy possible. That’s a first step, but it becomes harder. If you can deliver accurate R’s and C’s, you have to put that into a system. But that system becomes more and more unruly. It’s not just one effect. It’s capturing the variation. It’s capturing what’s happening in the transistor. And then it’s providing that information. We can provide gigabytes of data, but the issue is whether you can provide the right amount of information for the analog designer to do impedance matching and rotate the device and get highly accurate SPICE-like simulation. And can we also provide the right level of information and abstraction for the digital engineer or the rail analysis person with high accuracy?

Low-Power Engineering sat down to discuss parasitic extraction with Robert Hoogenstryd, director of marketing for design analysis and signoff at Synopsys, and Carey Robertson, product marketing director for Calibre Design Solutions at Mentor Graphics. What follows are excerpts of that conversation.

LPE: Does parasitic extraction get more complex as we move into multicore chips? And if so, why?
Hoogenstryd: Yes, and the challenge is that customers are trying to deploy hierarchical methodologies on chips. The goal is that you’d like to be able to re-use as much as you can in circuits that you duplicate, but you have this challenge where you need to be able to accurately model the effects between the block interactions. For example, coupling capacitance is a big thing in that area. You need be able to model the effects of this block connecting with this block, but you’ve done extraction in isolation because you did it as part of the IP development. The big challenge today is people coming up with effective hierarchical methodologies that don’t double count or don’t miss the data when you put these things together and analyze everything in context.
Robertson: Multicore means more hierarchy, and hierarchy makes sense from an intuitive perspective because you can build things up. But what you’re going to do is create a model for your cores in isolation, and that’s not how they’re going to perform. You can’t do things things flat, so you have to make some tradeoffs. How the circuit performs in isolation isn’t the same as having four or eight of these put together. The noise and the coupling are much different. Getting beyond timing signoff or some other analysis to say you’re not going to have coupling or noise issues is going to require some combination of heuristics, guard-banding and extraction to make some estimation of how these cores are going to operate on a chip. What we really want to do is characterize them by themselves. They may all behave the same, but you need to analyze that, as well.

LPE: How much does dropping the voltage affect all of this?
Robertson: Customers aren’t just dropping the voltage. They’re also really pushing on voltage analysis, IR drop and power rail analysis to identify at this low voltage node what really is Vdd for every one of the devices. And at what time? They may need a very accurate RC network of the power line, which is humongous. Then you have reduction techniques or simulation techniques on top of that to identify what’s the Vdd at what time for every one of these MOSFETs. It’s very difficult.
Hoogenstryd: There is no consistency among customers. We see some customers in design teams pushing the limits where they’re trying to get the voltages as low as possible. They need to do all this analysis to make sure the IR drop doesn’t force this thing to drop to a voltage where a device doesn’t work anymore. And then there are others who want to employ hierarchical design methodology but they don’t want to think about hierarchy. They just want to put things together and have it work. And then there are others who take much more practical approaches. I’ve been with customers doing low-power designs and we talk about IR drop analysis and they say they don’t need it. They just design really good power rails. They guard-band. They over-design because yield is a concern. There are companies today doing multicore design where they guard-band their IP blocks. They shield them. So they try to solve the problem through a design technique rather than trying to rely on after-the-fact analysis to make sure that everything is going to work in an environment that was unpredictable. They use design techniques to try to make things predictable. There are various levels of that. I’ve even seen companies that are very concerned about area using some of these design-for-practicality techniques. They know they might lose a little in silicon area but they get better yield. There is really a lot of variability in how customers are trying to solve this problem. Some use more analysis, more details, more information. Others are just trying to design the problem out.

LPE: How much time is parasitic extraction taking? Is it increasing?
Hoogenstryd: It’s still miniscule compared to the verification. I hear from customers that they want parasitic extraction to run faster. Every year they’re asking for 2x, 3x or 5x increases. For some reason they think we can magically change our code and run it 5x faster even though we’re extracting more data. But they are spending a lot more time on the analysis side. Where they’re really feeling the pressure on the digital side, particularly with extraction driving place-and-route flows, is in the ECO (engineering change order). They want to do an ECO overnight. That means they want to take the place-and-route data, go through timing analysis, ECO optimization, and back into place and route within a day. They’re pushing on every one of the tools in that tool chain to be faster. It’s the same on the analog side. They want to be able to turn around their simulation analysis or other types of analysis very quickly. The natural thing is to push the tool faster. What we’ve been trying to do is change the customer’s mindset to focus on the end goal and how to make the whole flow faster. You need to look at how you’re running your extraction, what you’re using that data for, and how to make that data accurate but more efficient. It’s a multi-prong approach. Extraction is part of the analysis flow.
Robertson: People are budgeting a lot more time for LVS turns or DRC turns because they understand they need to iterate through those until it’s clean, and then you go into downstream extraction and simulation. The amount of time budgeted is definitely more on the verification side. But people aren’t only pushing this for performance. They’re being asked to do more. It’s not just timing closure, and it’s not just timing closure on one corner. Customers want to do 5 or even 25 corners, but they don’t have the time. Getting raw performance isn’t necessarily the answer. It is intelligence around your overall methodology. You won’t get more time. If you get four weeks for verification and two days for extraction, you’re not going to get two weeks for extraction. But if they’re going to fit in these various tasks around corner simulation and rail analysis and signal integrity it is about how we feed those analysis tools appropriately. That’s a real struggle. We need to step back and say, ‘How do we come up with an intelligent corner methodology approach and power analysis, and can we perhaps do one extraction to feed all these other goals?’

LPE: There are two forces at work here. One is that everything is closer together. The other is there’s more real estate, which means you can cram more on a chip. So don’t you have to analyze more simultaneously?
Robertson: Yes, you do have to crunch all of these polygons and the electrical field is more complex and there are more of them and there are more R’s and C’s. And there are more analysis tools downstream, so it is more analysis in less time. But we do find customers, whether they realize it or not, customizing it themselves. Everyone is following foundry rule decks and foundry device models. There are plenty of things the foundry will do. In that extra time, customers are coming up with design flows that are custom to them. If you look at five fabless companies, they have different ways of doing designs to optimize what they think they do well. It may be low power or wireless methodologies. We’re doing more on the verification side to accommodate their design styles with customized verification flows, even though underneath that there’s been a standardization of rule decks, extraction methodologies and device models. They need new design techniques, new verification techniques as well as new extraction flows.

LPE: Are companies getting to the point where they’re looking at good enough instead of checking every corner case?
Robertson: No one has ever said that to me. Inside of companies, I’m sure that’s happening. But what we’re hearing is always more accuracy, more reduction, more speed—either now or for the next node.
Hoogenstryd: Customers are using multiple approaches. One is to push on their suppliers to make the tools faster so they can do a chip that’s four times bigger at the next node in half the time they did it at the previous node. In Japan the mantra is 5x. They’re struggling with a chip that’s 2x bigger. With their budget constraints they have to stick with the computers they have. They can’t buy any more hardware. But this new chip is going to have more functional modes. Therefore they have to do twice as much simulation on a chip that’s twice as large with the same hardware resources. So they ask us to make the tool four to five times faster so they can do it in the same time with the same resources. That’s one prong. The other approach is to come up with practical solutions to get their arms around the problem. Say you have four voltage islands in a design. If you want to capture all the end cases with static timing and each one can turn on or off, or go from a high voltage to a low voltage, to find the critical path across the blocks you have to simulate or analyze 16 different voltage combinations. They come up with methodologies to model around it, coming up with different scenario combinations. They may spend more time up front doing some analysis to figure out what are the critical corners they have to analyze at the chip level or the block level to guarantee you capture the boundary techniques. Each customer has a different threshold of risk, too. Some companies have multiple spins built into their strategy. They know the third spin is the one that goes into high volume.

LPE: Are companies worried about problems they can’t solve?
Hoogenstryd: Yield is the big thing customers are worried about. In my opinion, this push to get everything closer and closer together while being worried about 90% yield seems to be a crazy tug of war. The closer you put things together, the more likely you are to have a yield problem. For customers, density is not the issue. The average chip size hasn’t changed much in the past 20 years. But at 22nm, how many companies can come up with IP to fill that chip other than putting more and more memory on board. The rules in DRC have exploded to compensate for the lithography and CMP effects. There’s a debate about whether we continue pushing things closer together or whether we go to restrictive design rules, which may not be as efficient from a silicon area, but it does simplify the flow and make it more productive.
Robertson: When a customer does a DOE at the leading edge and the silicon is varying 20% or 40% vs. simulation, they usually ask us to help find the error and figure out whether they’re compartmentalizing the problem appropriately. We have all of these techniques to identify how the silicon performs. There is geometric variation that needs to be captured. Is it simulation-based or table-based? Is that the source of the error? Is it silicon stress? There are all of these effects. Some are in the device model. Some are printing of the wiring and the devices around them. And then there’s the actual calculation of the parasitics in the simulation. In the past, 65nm or 90nm, if you had a DOE with poor performance you could find the tall nail. Now when customers ask, it’s a combination of these effects. It’s probably 5 or 6 things that need to be fixed. And that’s at 32nm. At 22nm, with FinFETs, that’s going to be really interesting.

By Ed Sperling

Like everything else in semiconductor engineering at advanced process geometries, parasitic extraction is getting much more difficult at each node.

There’s more circuit data to analyze, less distance between wires and much more to sort through. In addition, a 10% error in accuracy at 90nm might have been tolerable, while at 28nm it can completely change how a chip works. And that’s only the beginning. Extraction now has to be done further up in the design cycle, with rising concerns for lower power, thinner layers of metal, new structures, and stress.

“In my opinion, this is one of the real big issues in design going forward,” said Andrew Brotman, vice president of design infrastructure at GlobalFoundries. “The parasitics associated with wires at advanced nodes is getting worse. If you deal with them too late, it hurts with time to tapeout.”

At the very least, parasitic extraction has to be moved up further in the design flow. The current thinking is that it should be part of place-and-route, but some chipmakers say it really should be considered at the architectural level for advanced designs.

“Some companies that are sensitive to these issues are addressing it,” Brotman added. “Qualcomm already is doing redundant vias. The next step is to add fill, which is extra metal to make metal densities more uniform. At 65nm and above, that was taken care of by the foundries. It was easy to keep metal away from other metal. At 45nm, the interconnects are more difficult.”

There are also a lot more of them. The harsh reality of Moore’s Law is that while it pushes transistors and wires closer together at each process node, it also adds many more of them. There’s twice as much data to crunch at each successive node even if everything worked as planned. But when it comes to interconnects, the closer they are together the greater the number of parasitic interactions. And with the emphasis on low-power designs and devices, those parasitics become even trickier to deal with effectively.

Electromigration
Physics isn’t helping the situation. Put an interconnect near a transistor, run current through it, and some of the ions strip away from the wire and move. With thicker wires, this isn’t a big problem. As wires get thinner at each process node and the spaces between them shrink, it can become a big problem.

That was one of the main reasons that chipmakers moved from aluminum interconnects to copper at 130nm. Aluminum is more prone to electromigration than copper. But even copper is showing its limits at advanced nodes. (see Figure 1)

“The problem at 40nm and below is that metal layers are thinner and electromigration is becoming a tremendous problem,” said Mahesh Tirupattur, executive vice president at Analog Bits. “We get the data from the foundries about this, but we still need to check it all. A lot of times it even requires manual checking.”

Tirupattur noted that while the existing tools and rules can handle the parasitics, the electromigration has never been effectively addressed. Electromigration has been a problem at higher currents, and it has been a problem at smaller geometries. But lowering the current to save power isn’t enough to stop the process when everything is more densely packed onto a piece of silicon.

In fact, sometimes cutting the power and creating power islands makes the issue even more complex. It’s harder to figure out where the electromigration will occur in chips if all the parts aren’t always on and not all the interconnects are in constant use.

Figure 1: Electron microscope scan of failure caused by electromigration in copper interconnect. (Courtesy of Wikipedia)

Into the future
At 22nm and beyond, makers of SoCs are looking at new structures such as FinFETs and possibly even 3D stacking of chips with through-silicon vias. While 3D, in particular, may ease some issues such as analog process integration, timing closure and IP re-use, it also will dramatically raise the amount of circuit data that needs to be crunched during parasitic extraction to be able to simulate a design.

How that will affect thermal envelopes within the stacked die, what effect it will have on electromigration, which will be able to move in 3D, and how the parasitics will be mapped and removed are all big questions marks. So are the costs associated with these tasks and the time it will take to get a chip to tapeout.

Low-Power Engineering sat down with two of the top experts—Robert Hoogenstryd, director of marketing for design analysis and signoff at Synopsys, and Carey Robertson, Calibre product marketing director at Mentor Graphics—to talk about what changes at 28nm and 22nm and why parasitic extraction is becoming so important.

By Ed Sperling
Low-Power Engineering sat down to discuss parasitic extraction with Robert Hoogenstryd, director of marketing for design analysis and signoff at Synopsys, and Carey Robertson, product marketing director for Calibre Design Solutions at Mentor Graphics. What follows are excerpts of that conversation.

LPE: As we move into 32/28nm, are the parasitics getting worse and is it getting harder to synthesize?
Hoogenstryd: At a high level, it’s more of the same. It’s getting harder and more detailed with every generation, but the challenges are no more difficult than what we had to address at 65nm and 45nm. It’s those second- and third-order effects coming into play that have to be modeled. There’s a little more complexity in the structures the foundries are trying to make at these geometries, which leads to having to model things that may not have been in those structures in previous technology generations. One thing we are seeing that’s new is more interaction between the devices and the interconnect, which has to be modeled. Those are often called advanced device parasitics. Things that were built into the SPICE models based on high-level device parameters are being modeled more directly through extraction than actually being in the SPICE model. We’re seeing more of that from generation to generation.
Robertson: The interconnect lines are getting smaller and smaller, and now every effect is important. Previously we ignored effects around the device and it was lost in the wash. Now customers are concerned about every attofarad. What is the contact capacitance? What is the infringing capacitance of the gate? We’re trying to understand that a lot better, not necessarily modeling it in the device and then separating it out. Several technologies ago, anything under a femtofarad was noise. Now customers are looking at 10s or 100s of attofarads to do their standard cells and SRAMs and analog IP very accurately. They’re looking at every little effect. In addition to looking on the total capacitance values, they’re pushing very hard on coupling accuracy. They want to do timing as well as signal integrity impedance matching, which means every component is now critical. The other things we’re wrestling with are new devices. FinFETs have much different cross sections than traditional MOSFETs. We’re looking at what’s going to be in the SPICE model and different parasitics, and those are things we didn’t have to consider before.

LPE: Is there too much data to deal with effectively?
Hoogenstryd: Yes. It’s not specific to 32/28nm or 22nm, though. We’ve been wrestling with this at every node. In my opinion, extraction is a means to an end. It’s a way to try to model the interconnect for analysis. That’s really the end goal. The customer needs to analyze their design accurately. The challenge is that they want to be able to do it in their lifetime. So you have to model the interconnect accurately and efficiently. At Synopsys, we’ve been wrestling with the right amount of detail for a specfic problem and then providing techniques to extract the right information, provide only the level of detail for what’s needed, and to be able to take advantage of all the tools that are out there. Take rail analysis, for example. In rail analysis what’s important is that you model the capacitance on the signals and you model the resistance on the power rails. Those become the dominant factors. We saw situations where customers would try to extract everything on the signals and the power rails with brute force. You can’t simulate it. The solution is to extract the right level of detail from those structures, which might seem very similar, so you can drive an efficient analysis. If you’re on the tenth decimal place on the power rail, it doesn’t buy you much on accurately modeling the current through the power rails.
Roberston: There are different levels of abstraction. If you’re just worried about timing signoff, there’s more data so you reduce it and you get accurate R’s and C’s and the smallest netlist possible to do simulation. That’s not what customers are looking at. They’re doing timing signoff, signal integrity signoff and power analysis. There is more data, but just reducing it to deal with higher levels of abstraction is not enough. You need to compartmentalize the problem. There is a timing signoff flow that employs very heavy RC reduction for total capacitances. But there’s also signal integrity where that’s not going to work. You need to preserve coupling capacitances, and then you definitely need a different coupling reduction paradigm to still achieve signal integrity. If you’re looking at power analysis or electromigration, the reduction techniques or approaches that were used for timing analysis don’t apply here because you need to find current density for every segment. There’s not only more elements, but there’s more information to do some of these analysis tasks. You’ve got different flows downstream of extraction, and that drives different extraction needs, whether it’s for timing, current density or corners. Information has to be dealt with differently, depending upon the end goal, but it is still a means to an end. It tells you more about your circuit.

LPE: What you’re talking about is divide-and-conquer and layering strategies. Does that cause problems later on when you have to integrate all of this stuff back together?
Robertson: Absolutely. One of our customers is trying to avoid double counting, which is a classic problem in parasitic extraction. We have this paradigm of building up, then trying to do some analysis at a higher level without double counting or missing effects inside. We’ve gotten more sophisticated. We have schematic simulation with estimates of post-layout effects in our device models. But when you get to complete post-layout how do you turn that off effectively without missing anything or double counting? That’s going from device model to parasitic model, and then you go from parasitic model of the transistor to cell model and higher and higher levels. As people go from blocks to chiplets to signoff, identifying what you captured the first time and how you account for the new effects is very, very difficult. The electrical field doesn’t operate hierarchically. It permeates them both and understanding white box, gray box, black box methodologies to get accurate simulation is very, very tricky.
Hoogenstryd: I agree.

LPE: Is the barrier to entry into this space getting harder for independent tools vendors?
Robertson: My biased answer is yes. There have been difficulties in the past for (Magma’s) QuickCap and Raphael as a field solver to play in the design flow space. Not only do you need accurate R’s and C’s, but it’s a means to an end. They need to be hooked up to the device model, they need to avoid double counting, they need to work hierarchically and flat. That means they need to work with an LVS infrastructure, a place-and-route infrastructure, leading into static timing or SPICE-like flows. It’s not enough to do R’s and C’s. You have to provide a circuit model to the downstream simulation tools, which means you have some integration to design environments, device extraction flows and simulation.
Hoogenstryd: The challenge for any startup is it’s easy for them to focus on a niche but tough to grow beyond that. It’s easy to attack a small problem or application and be very good at it, but to handle the next application and tool flow takes a lot of effort. If an extraction company doesn’t think about the analysis at the end and they’re just focused on the most accurate R’s and C’s then they’re going to have a problem.
Robertson: Historically the market has answered this question. Name the standalone extraction tools that have survived. It’s miserable as a business. Simplex did well because they tied to VoltageStorm and some of their analysis. It was a means to an end. But as standalone extraction entities like Ultima or Sequence can’t survive. Even QuickCap, the industry leader for reference software, has done okay in scientific communities but not gained much market share. And it’s even harder at the newer nodes.

LPE: As we move into power islands and multiple states, does it get harder to build a model.
Robertson: From a parasitic extraction standpoint, no. But this is a means to an end. As a solutions provider, the answer is yes. You can say it’s a simulator problem, but as a solution provider we have to provide integration. It’s not just about R’s and C’s. We have to do something intelligent with them. It’s either integration with simulation or integration with verification. At different voltage nodes or power domains you potentially have more critical circuitry. You need higher-accuracy parasitics vs. the digital domain where you may not need the coupling accuracy.
Hoogenstryd: We’ve had some customers say they want to do different extractions at different voltages. The real challenge is how you integrate that into your verification methodology. This is back-end verification for performance to make sure you meet timing, power goals, signal integrity goals. People are doing more extraction and more analysis. They’re trying to be practical in their approaches. Some are doing it well, some are throwing up their hands and saying they have to run 25 corners times X number of modes. They run out of time. People are running more extraction across more environmental parameters and then trying to integrate that into the verification methodology.