By Ed Sperling
For the better part of a decade talk about signal integrity in mixed-signal designs has been noticeably absent. That’s about to change.

Prior to the adoption of a 130nm process, many semiconductor companies actually went on record saying they were considering abandoning plans to ever put analog and digital on the same chip because the noise on digital would interrupt signals. The issue seemed to die down after that. But at 32nm it has shown up again, driven this time by a multitude of problems—some new, some old, and all of them made worse because there are fewer alternatives.

“The problem has always been there,” said Navraj Nandra, director of analog/mixed signal marketing at Synopsys. “But it has suddenly gotten worse because of the design interfaces at higher speeds. At 40nm and 28nm transistors switch faster. We also have 8 Gbps PCI Express [generation] 3 and DDR3. You have multiple lane configurations with PCI Express. Graphics cards use eight lanes. We’re connecting by 16s. But PCI can use 96 lanes.”

That’s a lot of noise on an advanced chip, where the wires are thinner and thinner at each node and components are packed together more tightly. If a single atom of deposition can change the functionality of a transistor, imagine what can happen when you start adding in parasitics and electromigration.

Power corrupts
If the only thing that changed in an SoC was the manufacturing process—doubling the number of transistors on a piece of silicon for every rev of Moore’s Law—then lowering the voltage would actually improve signal integrity. It isn’t that simple, however.

Adding in multiple voltage supplies increases the noise level on the chip. “At 28nm and beyond we’re seeing 800 millivolt supply voltages and threshold voltages of 300 millivolts,” said Aveek Sarkar, vice president of support at Apache Design Solutions. “Not only is the noise on the supply voltage increasing at each node, but the sensitivity is also magnified.”

The current is faster, the drive strength is higher, and voltage noise is higher. And the problem gets worse as you add in power gating and multiple power islands, all turning on and off unpredictably and intermittently in close proximity to each other.

It also gets worse when you bring the voltage regulators onto the chip from the PCB.
“That becomes a problem if you want multiple power domains on a chip,” said Qi Wang, technology marketing group director at Cadence. “The regulator is analog and noise becomes a problem. You’ve got big digital areas that generate noise. That can be a big issue, especially for the voltage regulator. People are now overdesigning chips and that’s creating more of a problem as more and more analog is put on the die.”

What’s in the package?
At least part of what will have to change in many designs is the package, which frequently is an afterthought for the total design and most often based on price rather than its effect on the operation of an SoC.

“People want to put in a cost-effective package to cut their costs, but that kind of package was not designed to handle high-speed I/O,” said Synopsys’ Nandra.

That can create a huge problem for signal integrity. But packaging is typically the victim of a silo effect. It’s not part of the up-front architectural decision and it’s not part of the SoC model being created.

“The focus is on the semi design, but the package design is just as important,” said Apache’s Sarkar. “There are no so many different packages that it’s confusing. You have to worry about whether it’s four layers or two layers, and if you have 80 different power domains the package can get very complex. We’re seeing wireless chip packages now that are not uniform.”

Living in a material world
The substrate material is equally important in signal integrity. CMOS has been getting mixed reviews, in part because it’s a proven low-cost material with excellent conductivity. But it’s not especially good for mixed-signal applications at advanced nodes. So while Intel may get away with using it for a predominantly digital processor, an SoC has completely different needs—and different economics.

Materials such as silicon on insulator and gallium nitride do improve signal integrity, but that improvement comes at a price. SoI is the less expensive of the alternatives, and has been proven to work in designs since 65nm by IBM, AMD, and some of the partners in the Common Platform ecosystem.

The problem is that architects and designers don’t necessarily know what kind of substrate or package they will need up front because the IP they buy from third parties doesn’t include information about noise.

“IP vendors need to provide enough data constraints in their libraries to say how the IP can be used properly,” said Cadence’s Wang. “You need to know, for example, ‘For this ping it can be this close to a digital component,’ or ‘Do you put this within this distance of I/O.’

He noted this is an important new wrinkle in IP integration. “’We need a holistic solution for the ecosystem of IP providers. We need a better model, and we need EDA tools that are better and faster at noise analysis.”

3D stacking
What has many experts particularly worried is the effect of 3D stacking on signal integrity. While most of the focus has been on thermal effects—hot spots caused by putting two or more chips together—there is a magnified effect for noise.

Vendors such as Qualcomm, Freescale and IBM expect 3D stacking to begin rolling out in late 2011 or early 2012—roughly one year from now. From there the approach is expected to grow rapidly, in large part because it shortens the distances that signals need to travel, which in turn boosts performance while lowering the power needed to drive those signals.

But moving the mass SoC market in this direction compounds many of the issues for signal integrity that exist with packaging, substrates and proximity—while adding new ones.

“With a through-silicon via, the power noise is much worse,” said Apache’s Sarkar. “TSVs brings signals closer together, but the silicon substrate is not stacked in terms of coupling with the TSV. So how do you model this?”

Synopsys’ Nandra noted that 3D shifts the problem from the packaging inside the SoC. “With a stack die you’re communicating inside the die, so the I/O problem is less,” he said. “But within the die now you have interactions between platforms. Basically you’ve just shifted the problem.”

Conclusions
None of this has been lost on the tools vendors. Many are scrambling to bring new tools to market that can analyze noise, heat, IP integration problems, as well as the ability to model all of it.

But these are complex issues. There is no single tool that can do everything, and so far these are well outside of existing design flows. Moreover, there are no standards that effectively address the dynamics of using IP in a high-density, highly noisy environment that includes voltage changes, rapid power-up and power-down modes, SerDes and high-speed I/O, and the effects of packaging and substrates.

These are challenging problems that have to be deal with up front and together, both by design teams and by ecosystems that include IP vendors and foundries. And so far, semiconductor makers have merely scratched the surface.

By David Lammers
Over the past year, key technologists in the semiconductor industry have come around to believing that EUV lithography will be available for critical mask layers in the next three to five years. What is still up for debate is whether EUV will be cost-effective for low-power consumer SoCs. To penetrate that cost-sensitive market, EUV must overcoming hurdles presented by masks, damage to the collector optics, power consumption, and other costs of operation.

Memory makers, particularly the DRAM vendors with less-regular 2D structures than the more one-dimensional NAND devices, are fully on board the EUV bandwagon. However, several SoC makers such as Texas Instruments are on the fence. At the Sematech Litho Forum, TI’s Jim Blatchford, manager of lithography development and process simulation, argued that double and triple patterning with 193i scanners will better meet TI’s cost and performance objectives over the next five years.

TI seeks a 30% to 40% reduction in the node-to-node cost per die. For the 60nm routed pitch layers, corresponding to the 22/20 nm node, double patterning “is the only economically feasible solution,” Blatchford said in a detailed presentation on “lithonomics.” For the 14nm node, triple patterning will be required for the gate, contact, and metal 1 layers. “Double and triple patterning will be cost effective for die with a routed pitch of about 40nm,” he said.

“Triple patterning at the 44 nm pitch provides a 25% better cost reduction,” Blatchford said, adding that TI expects to use “aggressive” double patterning to meet its cost objectives at the 20nm node and “multi-patterning” at the 14nm node.

“The choice of lithography is an economic decision,” Blatchford said at the Sematech meeting. On the technical side, TI requires an overlay specification of 6nm to 10nm for triple patterning to work out. “We need another click in the overlay improvement from the scanner manufacturers,” Blatchford said.

Samsung expects EUV lithography to be less than half as expensive as double patterning. (Source: Samsung at the 2010 Sematech Litho Forum)

Most logic companies are cheering on the EUV technology to be ready for introduction at the 14nm node, giving designers more freedom from the restrictive design rules that would be required for extensive double patterning. Gary Patton, vice president at IBM’s semiconductor R&D center in Fishkill, N.Y., said “power is the new issue” facing device makers.

For IBM’s 15/14 nm technology, where the pitch will be about 80 nm, IBM may be forced to rely on double patterning, a variable light source, source-mask optimization, and continued imposition of design restrictions. If EUV were to be available for critical layers, Patton said IBM and its Fishkill partners could “relax the constraints on the light source and the mask, and avoid the need for design restrictions and double patterning.”

“At the 11 nm generation, we will certainly need EUV,” Patton said.

Jim Clifford, senior vice president of manufacturing at Qualcomm, also said the industry needs EUV to continue scaling, which he defined as increasing the transistor density within a set power budget. Costs are the main worry. “Is it going to be cheaper to scale if lithography is half the wafer cost?”

During a June 30th briefing at the ASML facility in Wilton, Conn., ASML vice president Noreen Harned outlined ASML’s efforts to get EUV ready. At its Netherlands facility, ASML has “completely built” one NXE 3100 pilot production scanner, with “another one right on its heels.” While Harned did not disclose which companies will get the six NXE 3100 systems, she did say that ASML had more than six companies queuing up to order the 3100 scanners. ASML decided to limit the 3100 to six units so it could move on the NXE 3300B volume production scanner by the first half of 2012. (ASML’s Harned describes the NXE 3100 as a pilot production machine that can be used for early production.)

Boosting the source power to >350 Watts is key to acceptable EUV wafer-per-hour throughput. (Source: ASML)

With IMEC as the expected first customer, other likely recipients of 3100 systems include Hynix, Intel, Samsung, Toshiba, and TSMC. One 3100 customer is expected to reach wafer-out status by the end of this year.

ASML installed the Cymer laser-produced plasma (LPP) source on the first 3100, but ASML is working with other source vendors. At the Wilton briefing, Harned announced that in early July ASML achieved the “first light” milestone on the first NXE 3100 platform, with a thermally controlled housing and mechanical dynamic stability. However, she said the source currently provides only 30-40% of the power ASML needs to achieve the 60 wph throughput target for the 3100 systems. The source power can be upgraded in-place, through various techniques, she said.

While Cymer appears to have the inside track at ASML thus far, Harned said the ASML EUV NXE platform was designed to be source neutral. Japan’s Gigaphoton Corp. is working on an LPP source that Harned said is similar to Cymer’s but which takes “a different approach to debris mitigation.” Among the discharge-produced plasma (DPP) vendors, Ushio Corp., working at its Aachen, Germany site, has made the most public progress so far. “All three have plans in place to meet the scanner needs. They all have credible roadmaps to intersect with high-volume production,” she said.

Asked about cost-of-ownership considerations, Harned said the lifetime of the collector optics is one concern. Unless mitigation efforts are improved, debris from the interaction of the laser and the tin droplets can damage the mirrors used to collect the source power. “The collector optics are the most-expensive consumable. Our target is a year, but it must be six months at the start. Fortunately, the collector optics are refurbishable,” she said.

Responding to a presentation by TSMC’s Burn Lin at the IEDM last December, in which Lin claimed that power consumption of the EUV scanners would make them impractical, Harned said ASML’s data shows that an EUV scanner and source will consume about 3X the power consumption of a 193 immersion scanner. “Power consumption is dominated by the source, and to a lesser extent by the need for vacuum operation. But it is about 3X, and that is a real measurement,” she said.

This just in: A low-power transmission of NBC’s Washington, D.C., broadcast via TV translators is going away. Residents in Virginia received a notice from Qualcomm—which specializes in low-power chips—that the service interferes with new wireless services. Thank the Northern Virginia Daily for reporting this one.

Freescale has jumped into the gallium arsenide world with four chips optimized for base-station equipment. Yes, it really is true. Bulk CMOS is running out of steam for many applications at advanced nodes.

Apple’s iPad reportedly is getting a memory boost. AppleInsider reports that at the heart of the device is an ARM processor. That explains the 10 hours of battery life.

By Pallab Chatterjee
Until recently, low power engineering has been defined by the automated use of EDA tools in the design flow to help cut back on peak dynamic power. The new generation of mobile and video products has forced a change in that methodology.

There are two other fast rising architectural approaches. The first is multicore, which is prevalent in new product introductions from Nvidia, Samsung SLSI, Imagination Technology, NetlogicMicro, Broadcom, and Qualcomm. To address the usability specs required by e-readers, mobile Internet devices and other mobile information products, a new compute architecture was needed that did not just rely on “function disabling” as a power reduction technique. All of these companies introduced designs that are focused on multicore architectures, where there is complete functionality available at all times even though the process has been optimized for low power.

This low power optimization has to do with custom library design creation, modification of internal clocking schemes, datapath and buffer optimization, memory segmentation and placement, and most importantly dynamic control of the design’s power use and speed based on the data content of the information being processed on a per-packet basis. This re-architecture of products was the key enhancement with the new dual Cortex Nvidia Tegra, which is targeted to e-readers and tablet PCs, as well as the high-performance Alchemy multicore and multithreaded processors for automotive and navigation applications, and the many new video and communications appliances from Broadcom and Qualcomm.

The basis for most of these systems are ARM processors cores (A8 or A9 primarily) or MIPS cores. This shift has allowed both a performance increase in the end systems as well as a nearly doubling of the operating battery life.

The second prevalent low-power methodology is the segmentation of design to a CPU and a GPU rather than a single compute engine. While the initial impression is, this takes more power, the GPU is actually more power-efficient on graphics and some video data than the CPU, and on general use functions, the CPU is more power-efficient than the GPU. For most of the smart phones and media processing chips, this approach has replaced bigger single-processor cores with clock-gating and multi-voltage device process solutions.

These architectural changes were implemented to address both the data dependence of the power use and the yield-process variability of sub-wavelength manufacturing. As most of the applications have a very thin and small form factor, they are bound by a fixed or diminishing power envelope. To address the longer term of operation the components can lower the operating voltage, but this does not take into account the associated reduction in performance in the power envelope that is associated with it. In order to address this aspect of design, the mobile handset and mobile computing requirements have driven to the smallest geometry process flows available.

The utilization of these processes (45nm and 40nm, currently) requires restricted design rules, restricted topologies and limited device size diversity to yield well. These designs are optimized with new RTL and physical libraries, new floor plans, and power routing to highlight the data path symmetry that is required by the data sets being processed. Examples of this are new 3dmedia processor in 40nm by Samsung for mobile phones that utilize the IMG Tech 3D video and graphics engine and a high-performance ultra low power ARM CPU.

The distributed multicore approach also has been utilized in high performance for lower power products. AMD/ATI introduced the 5970 Radeon graphics card at the Consumer Electronics Show. The card has two GPUs and is a Direct X11 product with more than 4.6TFlops of peak performance. The restructuring of the device/cell library, its reliance on proven 40nm bulk CMOS processing and the use of GDDR5 memory allows the product to operate with a peak power of about 300 watts but only requires 51 watts for nominal operation. The design was optimized for power and a data control flow to support the 3200 parallel stream processors and the 160 texture units. Dynamic power is managed based on how many streams and texture units are needed at any time based on the contents of the data that being processed on any given cycle.

Most of these new systems are targeting use of Samsung’s low-power DDR3 memory, which operates at 1.3v vs. 1.5 volts and offers higher densities than DDR2. These higher-density, low power solutions can provide in excess of 35% overall power footprint reduction for the design, if used with 32nm low-power flash memories in SSD applications rather than rotating media.

The takeaway from CES this year is that architectural engineering and new firmware control methods are now seen as essential to address the functional requirements of the new mobile communication and processing platforms. This is an intelligent shift from recent years, when only feature size reduction and blind tool-based selection of power gating and power routing were in vogue.

By Cheryl Ajluni

The quest for low power in electronic devices is one that shows no sign of abating any time soon. Pressure for it comes from many different sources, such as the continual drive to pack more functionality into ever smaller, mobile electronic devices.

To try and maintain a decent battery life for today’s power-hungry “road-warriors,” engineers have to reduce power consumption. To achieve that, they must spend more time and care in choosing the components, materials and techniques they will employ to drive down power consumption. They also must look closely at the wireless communications protocols they choose to employ.

One protocol that has received a great deal of attention of late is IEEE 802.11n—one in a long line of standards to emerge from the alphabet soup that is the Wireless Local Area Network (WLAN). Its improved performance and enhanced reliability over previous WLAN standards is thought to be the critical component in finally enabling WLANs to function as predictably as their wired counterparts. It’s no surprise than that a recent study from ABI Research predicts that by 2012 shipments of 802.11n technology will account for a full 60 percent of the market. Today, virtually 84 percent of the WLAN market stems from 802.11 a/g technology accounts.

Unfortunately, as is typical with any new technology, 802.11n faces a slew of challenges. In the Wi-Fi enabled, battery-sensitive market, for example, a key challenge to 802.11n’s widespread proliferation is power consumption. Meeting this challenge demands an ultra low-power technology, but can 802.11n deliver the low power necessary to take the battery-sensitive mobile by storm? Let’s take a closer look.

802.11a, b, g…n?

Essentially, IEEE 802.11n is designed to enable Wi-Fi networks to do more, faster and over a larger area. Well suited for both enterprise and home networks, it has the potential to deliver up to twice the range and five times the throughput of traditional WLANs (e.g., 802.11a, b or g). To date, draft 2.0 of the 802.11n standard has been approved and forms the basis for Wi-Fi CERTIFIED 802.11n draft 2.0 products. Certification of such products began in June 2007 and is done by the Wi-Fi Alliance (www.wi-fi.org). The final 802.11n standard is expected in September 2009.

802.11n technology builds on previous 802.11 standards by adding 40MHz operation to the physical (PHY) layer (enabled in either the 5- or 2.4-GHz mode), and frame aggregation to the MAC layer. It is based on Multiple-Input-Multiple-Output (MIMO) technology, which employs multiple receiver and transmitter antennas to transport two or more data streams simultaneously in the same frequency channel. This allows MIMO to coherently resolve more information than possible using a single antenna.

Is low-power 802.11n possible?

While the use of MIMO gives 802.11n significantly increased data rates, its multiple transmit-and-receive chains also increase power consumption—turning MIMO-based products into potential power hogs and dramatically impacting battery life. That fact alone has raised many concerns. A full-featured 802.11n access point (AP) will typically consume much more power than a legacy 802.11a, b or g AP, although a device’s actual power consumption will depend heavily on the implementation and vendor involved.

To address this power concern, IEEE 802.11n has extended the power management capability of the 802.11 MAC to include the following mechanisms:

• Power Save Multi-Poll (PSMP). This mode is an extension of the Automatic Power Save Delivery (APSD) approach specified in the 802.11e standard for improved Quality of Service (QoS). With PSMP, the client schedules the frames that it transmits as the trigger for delivering downlink frames. This reduces the contention between clients and between the client and the AP, which in turn dramatically improves power conservation in the clients. As a dynamic method, PSMP immediately adjusts to changes in traffic demand by the clients using it. While this mode is often touted as a way for VoIP clients to save power, it is generally best used only in situations with relatively heavy traffic loads.

• Spatial Multiplexing (SM) Power Save. In contrast to PSMP, SM Power Save allows an 802.11n client to power down all but one of its radios and can operate in either dynamic or static mode. In dynamic mode, all but one of the client’s radios is turned off. The client can quickly turn on radios, as needed, when it receives a frame. After the frame reception is complete, the client can return to a low-power state by again disabling all but one radio.

  In static SM Power Save mode, the client behaves as an 802.11 a or g client by turning off all but a single radio. The client’s AP is notified that the client is operating in the static single-radio mode and that it must send only a single spatial stream to the client until otherwise notified.

  802.11n also specifies an optional power save mode—Dynamic MIMO Power Save. This mechanism essentially allows 802.11n devices to dynamically change the number of transmit-and-receive chains that are active when traffic loads are light, such as by downshifting from 3×3 to 1×1 MIMO.

  The wave of 802.11n products

  By employing the mechanisms previously specified, low-power operation of 802.11n is possible. Of course, it doesn’t end there. Today, 802.11n Draft 2 chip developers like Atheros, Broadcom, RedPine Signals, and Qualcomm, just to name a few, are employing their own advanced techniques and process technology to minimize power consumption. Their continued pursuit to develop low-power 802.11n chips is bolstered by announcements like Apple’s use of 802.11n in its next-generation iPhone and iPod Touch models.

  The Apple devices are said to use the Broadcom BCM4329 wireless chip, a complete IEEE 802.11 a/b/g/n system (MAC/baseband/radio) with Bluetooth 2.1 + Enhanced Data Rate (EDR), and FM radio receiver and transmitter (Figure 1). The chip not only adds support for 802.11n features, including the ability to find and join 5-GHz networks, but also incorporates new power savings, such as advanced design techniques and process technologies to reduce active and idle power consumption and extend battery life.

  

  Figure 1. Broadcom’s BCM4329 wireless chip supports a variety of 802.11n optional features such as SpaceTime Block Coding (STBC), Short Gual Interval (SGI), A-MPDU aggregation, Block Ack, Greenfield, and RIFS. During WLAN operation, it achieves low active transmit and receive power consumption and ultra-low power in standby and idle modes.

  Perhaps one of the most significant low-power 802.11n offerings to come to market recently hails from Qualcomm (www.qualcomm.com). Its new WCN1320 N-Stream WLAN chip is the industry’s first dual-band 802.11n standards-based WLAN solution with 4×4 MIMO technology (Figure 2). Based on 65-nanometer CMOS process technology, the chip combines an embedded applications processor, media-access controller, digital baseband, radio-frequency transceiver, and system power-management in a single compact 12×12 mm package. With its 4×4 MIMO technology, it uses four spatial streams to distribute multiple streams of concurrent voice, video and data in either the 5- or 2.4-GHz radio bands. The WCN1312 chip incorporates advanced power-management techniques to minimize sleep, standby, and active power consumption.

  

  Figure 2. With performance of 600 Mbps, Qualcomm’s WCN1320 chip enables the distribution of multiple simultaneous streams of high-definition video, voice and data throughout the home. Sophisticated algorithms take advantage of the chip’s multiple transmitters and receivers to increase data throughput, extend range and overcome interference with a spectrally-efficient solution.

  Conclusion

  IEEE 802.11n is a technology whose time has now come. Expected to be fully approved later this year, it will open the door to a wealth of high-performance mobile applications like HD video, high-resolution imaging and voice over wireless LAN (VoWLAN). Realizing this goal will require special attention to reducing power consumption. Many of the current 802.11n Draft 2 chips achieve this goal through use of advanced design techniques and process technologies, but they also take advantage of the standard-specified power saving modes. Future chips based on the final 802.11n standard will need to follow suit. Doing so will help ensure the success of 802.11n, while also driving continued growth of the wireless connectivity market.