By Ed Sperling
Wide I/O—both as a specific memory standard and as a generic approach for on-chip networking—has been looked at for the past couple of chip generations as a way of improving SoC performance. Increasingly, it also is being used as a key strategy for reducing energy consumption.

Wide I/O refers to a number of different approaches in on-chip networking, ranging from through-silicon vias in 3D stacks to interposers in 2.5D stacking. It also refers to a standard for memory communication being developed by JEDEC, as well as more dedicated channels for signals. In all cases, the added benefit is a reduction in power needed to drive a signal.

The tradeoff typically is between serial I/O and wide I/O. Serial I/O is simpler to design and works over longer distances, but it is far less power efficient. Wide I/O, in contrast, is higher bandwidth with big power savings—Samsung, for example, estimates its new 1Gbit mobile DRAM based on a 50nm process consumes 87% less power—but the technology is also more complicated to use. And in most cases, it’s also more costly.

Eliminating complexity while adding more
The concept of bigger pipes has always been a last resort for chip architects. It’s well known that shortening the distance a signal travels and reducing the resistance can drive down the amount of power needed for a signal. Reducing the overhead of serialization and deserialization can cut the power even further. But ironically, it has taken an explosion in SoC complexity for chip architects to seriously consider simplifying signal paths.

“We always go through this pendulum swing of what’s the optimal physical implementation vs. what’s the simplest way to do it even if it costs more silicon,” said Steve Roddy, vice president of marketing and business development at Tensilica. “So you can do things with 128 wires using serialized I/O, or you can do it with a lot fewer using wide I/O. The serialized I/O requires deserialization, which costs power. With wide I/O, which could simply be a lot of wires connected to the next block, you can lower the frequency and widen the channel.”

In a 2.5D stack, that extra silicon is easier to justify because it doesn’t add significantly to the overall footprint. In a system-in-package or package-on-package it may involve an interposer, which is another piece of silicon. It also can involve a through-silicon via in a 3D stack, which is wide enough to avoid any congestion.

“With a TSV you don’t need a standard I/O, which includes the I/O circuitry, patch and bond wire,” said Tom Quan, deputy director of design methodology and service marketing at TSMC. “So you get rid of all the I/O circuitry, and you have the same area, power and current. That results in a tremendous power savings. You also get a big boost in timing. And if you use an interposer, that’s silicon so it has the same resistance and capacitance of a standard IC. You can simulate them both together and get a predictable result.”

Eliminating bottlenecks
There are many good reasons for using wider pipes. One is that multicore and multiprocessor implementations generally are inefficient. The whole idea behind these implementations was that software would be able to run across multiple cores and multiple processors. That didn’t work out as planned, due to the inability to parallelize many applications, but cores were still designed to share the same memory.

That’s inefficient from a performance and a power perspective. Cores that are not in use should be turned off or powered way down. Moreover, when they need to connect to memory it should be along a clear path with as little congestion as possible and over the shortest distance possible.

“For some years to come we’re going to be seeing systems in package with interposers as the ideal solution,” said Joe Sawicki, vice president and general manager of Mentor Graphics’ Design-To-Silicon Division. “That will involve a lot faster interconnects, mostly to memory, and potentially to homogeneous logic. One of our customers was developing a digital chip and needed Bluetooth. They did it in a digital IC and they also did it in a SiP. The SiP destroyed the SoC in performance and power.”

But the question also is at what cost. While 2.5D approaches are relatively straightforward, the interposer does add some cost and the TSV can add even more.

“We are pursuing full 3D and so are most of the people in the phone business, primarily because of the form factor and cost,” said Riko Radojcic, director of engineering at Qualcomm. If you think about an interposer, you’re adding another die to the cost. Conceptually an interposer is an elegant solution and it works fine for someone who sells a product for $100. If you throw in a $1 interposer it’s no big deal. But if you’re making a $5 die and you throw in an interposer, it is a big deal.”

The same is true of through-silicon vias, although the ultimate advantages of this approach are expected to become more significant over time.

“TSV is expensive but is a good way of meeting the form factor,” said Navraj Nandra, senior director of marketing for Synopsys’ DesignWare Analog and MSIP Solutions Group. “You need to optimize for both low power and low cost packages. It’s like buying a $50k hybrid car that gives you 32mpg compared to a $22k 1.2L, 3-cylinder petrol engine car that gives you 50mpg. Everyone is excited about the hybrid car.”

Optimizing the signals
Behind the hubbub about the I/O technology is another often overlooked piece of the equation. The move to multiple processors and multiple cores was done largely as a knee-jerk response to the end of classical scaling at 90nm. What has happened since then is a much more measured response to how to use these cores more effectively, which requires much more granularity in the design process. Not all cores need to be on an ARM or MIPS processor, for example, and not all of them need to be in one place on an SoC—or even on the same die of a SiP or 3D stack.

In addition, not all of those cores or processors need to be the same size or run the same software.

“In addition to wide I/O there are dedicated point-to-point connections to relieve the system congestion,” said Tensilica’s Roddy. “Those can include general purpose memory and processor. When the system architect knows beforehand what’s going to be in the system they can add those connections up front. So you may have a video decoder and buffer and an audio decoder using separate memories, and those may change depending on whether they end up in a cell phone or a set-top box. But there are some things you don’t know at design time and you need the ability to generate system-specific interconnects, which is what’s being sold by companies like Arteris and Sonics.”

And finally, there is a simple mathematic principle behind the push to reduce power.

“The longer a signal has to travel, the more power it takes,” said Qi Wang, technical marketing group marketing director for Cadence Solutions Marketing. “A lot of issues in design come down to power. If you put the memory outside the chip, that takes power. If you want to speed up performance, that takes power.”

Bigger pipes over shorter distances can help solve that problem, and it’s a solution that is beginning to garner much more attention these days.

By Pallab Chatterjee
The theme for this years ISSCC (International Solid State Circuits Conference) is “Electronics for Healthy Living.” In addition to the new microprocessors, memory and data converter technologies, the focus and keynotes are directed toward health-care products.

The common theme between all the talks is that health-care is being driven by mobility, information flow, and power. The key to high quality data transfer is having enough power to complete it—either wired or wireless. The key to mobility is to have autonomous power for the devices for the duration of time that it does not impact the activity the user is involved with.

The keynotes cover the range of silicon’s impact on the health care. Medtronics is discussing the scope of implantable devices, the reliability, data transfer and the system architecture of the implanted and external portions of the system. IMEC then follows with a discussion of the invasion of specialized purpose sensors that are now possible, their inroads into health care and the creation and powering of body area networks. Samsung then speaks on a different twist for health care. Their angle is that the major cause of pollution is energy consumption and hence generation. The way to address this problem is through reducing energy use in the manufacturing process and in the design of devices that utilize less power and can take advantage of innovative packaging.

Following the keynotes is the inaugural Plenary RoundTable discussion on how to address the next 10X reduction in power. The discussion is is hosted by Jan Rabaey of UC Berkeley and features TSMC, Hitachi, STMicro, Infineon, IMEC and other senior experts from the semiconductor and university commnity. This challenge, encompassing process innovation, CAD, design flows for digital, RF, analog, and memory is one of the key drivers for the next generation of energy efficient electronics.

Energy efficiency has now earned its own session with Energy Efficient Digital, which will be detailing such projects as ultra-low-voltage standard cells that operate down to 62mv of supply. Other new technologies include a 28nm DSP from TI that can operate at 0.6V, and wireless sensor processor that utilizes only 10pJ per clock cycle.

The technology development sessions once again mix between high performance and low power. On the high-performance side, architectural design for Terahertz (300GHz to 3THz) imagers and associated device blocks—amplifiers/antennas are being shown. On the low-power side, a transceiver that can operate at 0.24nJ/b, and energy scavenging converters that are now up to 72% efficient and generating 95mv, will be presented.

Filling out the program are tutorials on ultra-low power digital design and a forum on ultra-low voltage VLSI for energy efficient ICs. These sessions are expecting large attendance as they are the dominant directions for the next decade.

The shift for the conference and the industry is dramatic. Historically over the past 40 years the conference has been the vehicle where the biggest and fastest semiconductors were debuted. These devices now have to share the spotlight with the smallest, highest-density and lowest-power devices. The show is focusing a lot more on architecture, device technology and the systems aspects rather than just circuit blocks. This focus accompanies the idea that SoCs are true systems, and the they need to be addressed as such with focus on function, performance, power and application. The body area network discussions and technology, which balance data transfer and power as the main tradeoffs, are representative of the future of the systems and IC discussions in the future.

By Ed Sperling

IBM-Samsung Development Deal
IBM and Samsung are working together on new technologies for reducing the power in processors, which is hardly surprising considering they’re both part of the inner circle of the Common Platform consortium.

What’s different is that Samsung researchers for the first time will join IBM at the Albany, N.Y., Nanotech Complex, which it just so happens is right down the road from GlobalFoundries’ new fab. GlobalFoundries is another member of the Common Platform. The goal is to develop new process technology for mobile and high-performance computing, which the companies say will be “smarter, connected and more mobile.”

Greener Plugs
Green Plug introduced what it calls a green power processor, which can detect how much voltage and power a device is drawing—both when it’s on and when it’s in standby mode.

This kind of technology is great for really understanding Min Power. Is a TV in standby mode really almost off? Or is it almost on? And how much does that computer draw when it’s up and running, idle, or powered down? As this kind of technology becomes more widespread it should have interesting implications for future system-level power architectures.

Swift Move
FCC Chairman Julius Genachowski said swift action is necessary to avoid a spectrum crunch caused by widespread wireless adoption. He said spectrum needs to be used more efficiently, which largely means keeping licenses moving from older technologies to new technologies.

The FCC has been sounding the warning bell on this for the better part of a decade. It’s nice to see they’re still at it.

By Ed Sperling
Chang-Gyu Hwang, national chief technology officer for South Korea, sat down with Low-Power Engineering to talk about the future trends in technology, global business and power. Prior to his current role, which was created by the Korean government in April, he ran the semiconductor business at Samsung, where he spent the last 20 years in top management positions. He also is the former CTO at Samsung. What follows are excerpts of that interview.

LPE: What do you see happening next in technology?
Hwang: Over the past 20 years we’ve gone from PCs to mobile and the Internet. That will go to the mobile Internet, which will dominate over the next couple years. Then we’re expecting some fusion type of industry. There is a lot of room to improve, technology-wise and business-wise, but to satisfy and raise customer demand there will have to be some fusion industry. Inside IT many technologies will be embedded. Biotechnology will be a future technology. So will nanotechnology.

LPE: How will these technologies be used?
Hwang: In green transportation systems, for example, every country has automobiles, express trains, battery technology and battery charger systems, a smart grid and even nuclear energy. All of these are related. We’re expecting these industries will converge. Korea is relatively late in the industrial revolution, but it is strong in IT, shipbuilding, nuclear power and smart grids. We are looking for synergy in different technologies. I’m spending a lot of time in the United States. It’s a big market, and there are interesting technologies. I’m looking for partnerships from an open innovation point of view.

LPE: There’s a huge emphasis on saving power these days. What will change and why, both from a technology and a business standpoint?
Hwang: Smart grids are about using energy more intelligently and optimizing it, both from the producer and the consumer point of view. Korea is doing both. Korea has a relatively good start. We’re educating engineers. From an industry point of view, we’re well balanced in terms of nuclear and other types.

LPE: You mentioned embedding technology and convergence. Can you elaborate?
Hwang: It started with semiconductors. Many functions are now embedded into a single chip. They’re more cost-effective and use less power. At Samsung we introduced fusion technology where we embedded SRAM logic into memory chips in the OneNAND chip. There was intelligence in the software. We improved speed, reduced the chip size, used less power and boosted overall performance. That chip is dominating all markets because of its many advantages and lower cost. That kind of trend will be more prevalent. But the whole concept of an SoC was introduced because other chips were too expensive. The future will be in the fusion of emerging technology into one chip in the mobile and multimedia area. That will happen in other industries such as energy savings for automobile applications and across other industries.

LPE: Will the boundaries change between who produces what?
Hwang: Korea is relatively strong in hardware. It has a good total solution for making components, with good engineering skills. It knows how to reduce cost while maintaining relatively high performance. In the United States, companies like Google, Microsoft and Apple have different strengths. They’re strong in business and technology. Google is good in search engines, but they need server, low-power and low-latency technologies. Korea is a major supplier of components for Apple. If you apply this to other industries, there are many opportunities for collaboration. The United States has a lot of creative ideas and is very good in software, but in Korea there is more application in new fields. The two working together will drive those industries.

LPE: How about China?
Hwang: China is another variable. They are not a first mover, but they are a very effective follower—especially with low labor costs and low-cost solutions. The United States and Korean collaboration is at a higher level than what China will offer. Korea spends a lot of money on R&D, and it’s strong in core technologies in several industries. At that level we can collaborate with the United States.

LPE: What is your big challenge?
Hwang: My goal is to become the No. 5 technology country by 2020. We also need to be a first mover in some technologies. I have to figure out which industries to target, from the early design and planning stage. These should be as unique as possible, whether it was started in Korea or whether it can be developed using open innovation from other sources.

LPE: Where does the government play vs. companies?
Hwang: When you look at major Korean companies like Samsung, LG or Hyundai, they have their own plan. They are investing in R&D for the next era. But from a national R&D point of view, there’s more risk taking involved. We try to find areas that are not easy to get into, consolidate whatever research is out there, and then create new projects. Eventually companies will get involved, but initially this will be a government effort.

LPE: So this is pure research?
Hwang: Yes. More long-term research and more fundamental. I call it R&BD—research and business development. Otherwise we will not consider it seriously.

LPE: Can companies afford this kind of research on advanced SoCs?
Hwang: Normally a company cannot afford to initiate a project by itself. But at this moment we need to collect all the ideas, not only within a company. It also has to come from research laboratories, institutes and university research. There needs to be consolidation from the initial stage to the planning stage. That’s the reason we are initiating this from a national level. That’s our role.

LPE: How much of this is done through universities?
Hwang: We don’t involve them much, but we are inviting leading institutes and universities to collaborate at the initial stage.

LPE: Is there a lot of opportunity in fixing the Internet?
Hwang: The Internet still needs a lot of new technology. It’s handling massive storage. It needs low power technology. But most consumers are still asking for more speed. Low power and high speed are a contradiction, so we need to bridge these two extremes. There is an opportunity for technology. There’s also an opportunity from a business standpoint for using new technologies.

LPE: Where is the United States lagging?
Hwang: The United States is quite late for biotechnology. But there are opportunities for merging biotechnology with information technology with things like protein chips or chips that can check the status of your heart. There are many applications to find disease in the early stage at a very low cost. Korea is one of the leaders in this kind of hardware, as well as mobile phones and TVs—which are all linked to each other.

By Pallab Chatterjee
The trend in consumer electronic devices is toward a multimedia-centric data flow, forcing changes in the memory interface needed to handle it.

The increased compute resources needed for video signal processing, along with high-definition audio, used to be the exclusive domain of mainstream desktop computers and servers due to their access to memory and high data throughput. The evolution of mobile processors since has pushed these tasks into battery-operated devices, which have a low dynamic operating requirement.

These devices, which include everything from tablet PCs to netbooks, smart phones, and handheld gaming systems, are becoming the platform of choice for playback of these multimedia data sets. Progress has been made in the power/performance envelope for the processors, and now SPMT (Serial Port Memory Technology) is bringing a comparable advance to memory architecture.

To address the needs of these mobile devices, the SPMT solution has embraced the shift from parallel to serial. As has happened with computer I/O ports (parallel I/O and serial 25 pin to USB), PCI to PCI Express, and parallel ATA to 1.5G, 3G and 6G SATA, device memory is also changing. The reduced pin count and the ability to build local high-speed SERDES up to 12.8GB/s is the mainstay of the SMPT technology. The serial memory solution uses a small voltage swing, so it features differential signaling for increased reliability. The challenge has been the incompatibility with legacy systems, which has slowed adoption because of increased risk.

To remedy that, the SMPT group has created and adopted a SerialSwitch technology to address the power penalty at low bandwidths over parallel interfaces and the legacy interface issue. SerialSwitch is a technology that operates in parallel mode, with the low power factor of LPDDR2 at low data rates, and then switches to the power performance characteristics of the serial interface. This eliminates the startup latency of the memory as well as the traditional PLL lock times when switching to active mode. The technology specifically works by multiplexing an eight-lane bi-directional serial interface and an x16 LPDDR2 parallel interface onto the same pads. The parallel interface also ensures backward compatibility with existing LPDDR2 connections and system designs, making the transition to the new memory format easier. (See figure 1.)

Fig. 1

SPMT is the first serial data specification that is targeted specifically for memory. Its initial version supports 6.4Gb/s bandwidth per chip using standard 400MHz clocks. The backward compatibility includes both pin assignments and signals, as well as the command bus & commands and the system timing. As the target market is the mobile application space, special attention was paid to making sure the memory has a very low latency exit from power-down states, and can integrate with existing memory cores in current revision designs.

The new memory format supports four times the bandwidth as LPDDR2 for a given pinout, and half the power for a given bandwidth. Consider, for example, LPDDR2 memory with 800Mbps data rate per lane, 400MHz interface logic, an x128 (4×32) memory width needs 56 address pins and 176 data pins to yield a total bandwidth of 12.8GB/s at 720 mW. By comparison, the SMPT memory yields an 8Gbps data rate per lane, the same 400MHz interface logic, 32 lanes of interface width (equiv to x64 LPDDR2), and only needs 28 address pins and 88 data pins for a total bandwidth of 25.6GB/s for the same 720mW.

The SPMT memory will fit in a manufacturing-proven PoP216 package. With any new interface format, especially those directed as power savings, the issues of manufacturability and test always come into play. SPMT is no exception. The specification calls for the chips to use the same die and package test as parallel memory, utilize BIST for the serial interface and result in the same testing time as standard LPDDR2 parallel memory.

The format is being backed by ARM, Hynix, LG, Marvell, Samsung and Silicon Image. It is expected to appear in products in the marketplace in near term.

By David Lammers
Over the past year, key technologists in the semiconductor industry have come around to believing that EUV lithography will be available for critical mask layers in the next three to five years. What is still up for debate is whether EUV will be cost-effective for low-power consumer SoCs. To penetrate that cost-sensitive market, EUV must overcoming hurdles presented by masks, damage to the collector optics, power consumption, and other costs of operation.

Memory makers, particularly the DRAM vendors with less-regular 2D structures than the more one-dimensional NAND devices, are fully on board the EUV bandwagon. However, several SoC makers such as Texas Instruments are on the fence. At the Sematech Litho Forum, TI’s Jim Blatchford, manager of lithography development and process simulation, argued that double and triple patterning with 193i scanners will better meet TI’s cost and performance objectives over the next five years.

TI seeks a 30% to 40% reduction in the node-to-node cost per die. For the 60nm routed pitch layers, corresponding to the 22/20 nm node, double patterning “is the only economically feasible solution,” Blatchford said in a detailed presentation on “lithonomics.” For the 14nm node, triple patterning will be required for the gate, contact, and metal 1 layers. “Double and triple patterning will be cost effective for die with a routed pitch of about 40nm,” he said.

“Triple patterning at the 44 nm pitch provides a 25% better cost reduction,” Blatchford said, adding that TI expects to use “aggressive” double patterning to meet its cost objectives at the 20nm node and “multi-patterning” at the 14nm node.

“The choice of lithography is an economic decision,” Blatchford said at the Sematech meeting. On the technical side, TI requires an overlay specification of 6nm to 10nm for triple patterning to work out. “We need another click in the overlay improvement from the scanner manufacturers,” Blatchford said.

Samsung expects EUV lithography to be less than half as expensive as double patterning. (Source: Samsung at the 2010 Sematech Litho Forum)

Most logic companies are cheering on the EUV technology to be ready for introduction at the 14nm node, giving designers more freedom from the restrictive design rules that would be required for extensive double patterning. Gary Patton, vice president at IBM’s semiconductor R&D center in Fishkill, N.Y., said “power is the new issue” facing device makers.

For IBM’s 15/14 nm technology, where the pitch will be about 80 nm, IBM may be forced to rely on double patterning, a variable light source, source-mask optimization, and continued imposition of design restrictions. If EUV were to be available for critical layers, Patton said IBM and its Fishkill partners could “relax the constraints on the light source and the mask, and avoid the need for design restrictions and double patterning.”

“At the 11 nm generation, we will certainly need EUV,” Patton said.

Jim Clifford, senior vice president of manufacturing at Qualcomm, also said the industry needs EUV to continue scaling, which he defined as increasing the transistor density within a set power budget. Costs are the main worry. “Is it going to be cheaper to scale if lithography is half the wafer cost?”

During a June 30th briefing at the ASML facility in Wilton, Conn., ASML vice president Noreen Harned outlined ASML’s efforts to get EUV ready. At its Netherlands facility, ASML has “completely built” one NXE 3100 pilot production scanner, with “another one right on its heels.” While Harned did not disclose which companies will get the six NXE 3100 systems, she did say that ASML had more than six companies queuing up to order the 3100 scanners. ASML decided to limit the 3100 to six units so it could move on the NXE 3300B volume production scanner by the first half of 2012. (ASML’s Harned describes the NXE 3100 as a pilot production machine that can be used for early production.)

Boosting the source power to >350 Watts is key to acceptable EUV wafer-per-hour throughput. (Source: ASML)

With IMEC as the expected first customer, other likely recipients of 3100 systems include Hynix, Intel, Samsung, Toshiba, and TSMC. One 3100 customer is expected to reach wafer-out status by the end of this year.

ASML installed the Cymer laser-produced plasma (LPP) source on the first 3100, but ASML is working with other source vendors. At the Wilton briefing, Harned announced that in early July ASML achieved the “first light” milestone on the first NXE 3100 platform, with a thermally controlled housing and mechanical dynamic stability. However, she said the source currently provides only 30-40% of the power ASML needs to achieve the 60 wph throughput target for the 3100 systems. The source power can be upgraded in-place, through various techniques, she said.

While Cymer appears to have the inside track at ASML thus far, Harned said the ASML EUV NXE platform was designed to be source neutral. Japan’s Gigaphoton Corp. is working on an LPP source that Harned said is similar to Cymer’s but which takes “a different approach to debris mitigation.” Among the discharge-produced plasma (DPP) vendors, Ushio Corp., working at its Aachen, Germany site, has made the most public progress so far. “All three have plans in place to meet the scanner needs. They all have credible roadmaps to intersect with high-volume production,” she said.

Asked about cost-of-ownership considerations, Harned said the lifetime of the collector optics is one concern. Unless mitigation efforts are improved, debris from the interaction of the laser and the tin droplets can damage the mirrors used to collect the source power. “The collector optics are the most-expensive consumable. Our target is a year, but it must be six months at the start. Fortunately, the collector optics are refurbishable,” she said.

Responding to a presentation by TSMC’s Burn Lin at the IEDM last December, in which Lin claimed that power consumption of the EUV scanners would make them impractical, Harned said ASML’s data shows that an EUV scanner and source will consume about 3X the power consumption of a 193 immersion scanner. “Power consumption is dominated by the source, and to a lesser extent by the need for vacuum operation. But it is about 3X, and that is a real measurement,” she said.

By Pallab Chatterjee
Recently Samsung gave an update on the status and availability of its advanced 32/28nm process technology for use in foundry. The process is targeted for shipping designs to customers at the end of this year, with a road map that continues through the 22/20nm nodes and down to 15nm.

What was particularly interesting were several key innovations that have made this all possible, as well as the company’s statement that the real driver is reduced power.

The new processes, co-developed with IBM, follow the large commercial success of the Intel achievement of using a Hafnium “Hi-K” metal gate process. Although this terminology has been around for a few years and is the dominant technology in the microprocessor marketplace, there has been some “uncertainty” in the design community about what it actually buys the designer. The Hi-K gate technology is a process development that directly addresses the leakage current problem that arose in CMOS technology at the 90nm node and has persisted through the 45nm node. The scaling on process technology using Moore’s law is a three-axis scaling—x and y for the length and width of the transistor used to make the basic devices, and also z or the vertical dimension. Z is the thickness of the gate dielectric, which controls the intrinsic speed and performance of the device by setting the difference between “on” and “off.”

Since the late 1960′s the scaling of all three axes has taken place concurrently—until the 90nm node, that is. At 90nm the complexities of lithographic processing, planarization, materials used for interconnect, isolation between devices and reduction in application power supply were moved up from third- to fourth-order issues to become the dominant drivers. This made the leakage current and capacitance issues with the z-direction scaling the secondary challenge. This focus on the other processing issues caused the gate scaling to stall, and not continue proportionately with the x and y scaling, resulting in leakage, multi-power islands, high electric fields, and high-stress devices and designs that have dominated the past few years.

The lithography solution is staying optical with multiple patterning solutions through the 22/20nm node. The planarization, interconnect and device stacking for “multi-die” technologies are progressing to address the function vs. density vs. space requirements going forward, which allowed time to develop the new materials needed to make the gate dielectric (replacement of standard SiO2 with an Hf based material) and re-start the z-dimension scaling. At the 32/28nm node, the reduced leakage and increased device performance (difference between “on” and “off” states) brings a new level of design capability.

Results using the process in foundry-type circuits (embedded processors with memory, custom logic, and standard commercial interface connectivity) are showing as much as a 35% power reduction for the same operation specification as existing circuits. This power reduction comes from both the ability to drop the operating supply voltage for the same performance specification and from an overall reduction in leakage/standby state power for “idle” modes in a design.

The new process technology, now starting to become available from multiple suppliers, does bring an opportunity to create a new generation of mobile appliances. There is a significant challenge to the design community to address these benefits as a mainstream technology solution. The cost of entry into the design game at these nodes is very high. A typical 32/28nm SoC is probably going to contain more than 500 million devices, including embedded memory, and will likely have a very high pin count. This will require a big design team to architect, design, assemble, and test, not counting the very aggressive 20-plus man-years of IC design (5M devices/man year for the flow X 20 people = 100M devices + 400M in third party embedded memory), and application software development.

These design costs are on top of the fab costs, which are targeted at more than $4M for masks, plus the wafer fab, package and test. And it is looking like the big boys at the $30 million-minimum per design are the only ones who will be left at the table for real “low power” process game.

By Pallab Chatterjee
Until recently, low power engineering has been defined by the automated use of EDA tools in the design flow to help cut back on peak dynamic power. The new generation of mobile and video products has forced a change in that methodology.

There are two other fast rising architectural approaches. The first is multicore, which is prevalent in new product introductions from Nvidia, Samsung SLSI, Imagination Technology, NetlogicMicro, Broadcom, and Qualcomm. To address the usability specs required by e-readers, mobile Internet devices and other mobile information products, a new compute architecture was needed that did not just rely on “function disabling” as a power reduction technique. All of these companies introduced designs that are focused on multicore architectures, where there is complete functionality available at all times even though the process has been optimized for low power.

This low power optimization has to do with custom library design creation, modification of internal clocking schemes, datapath and buffer optimization, memory segmentation and placement, and most importantly dynamic control of the design’s power use and speed based on the data content of the information being processed on a per-packet basis. This re-architecture of products was the key enhancement with the new dual Cortex Nvidia Tegra, which is targeted to e-readers and tablet PCs, as well as the high-performance Alchemy multicore and multithreaded processors for automotive and navigation applications, and the many new video and communications appliances from Broadcom and Qualcomm.

The basis for most of these systems are ARM processors cores (A8 or A9 primarily) or MIPS cores. This shift has allowed both a performance increase in the end systems as well as a nearly doubling of the operating battery life.

The second prevalent low-power methodology is the segmentation of design to a CPU and a GPU rather than a single compute engine. While the initial impression is, this takes more power, the GPU is actually more power-efficient on graphics and some video data than the CPU, and on general use functions, the CPU is more power-efficient than the GPU. For most of the smart phones and media processing chips, this approach has replaced bigger single-processor cores with clock-gating and multi-voltage device process solutions.

These architectural changes were implemented to address both the data dependence of the power use and the yield-process variability of sub-wavelength manufacturing. As most of the applications have a very thin and small form factor, they are bound by a fixed or diminishing power envelope. To address the longer term of operation the components can lower the operating voltage, but this does not take into account the associated reduction in performance in the power envelope that is associated with it. In order to address this aspect of design, the mobile handset and mobile computing requirements have driven to the smallest geometry process flows available.

The utilization of these processes (45nm and 40nm, currently) requires restricted design rules, restricted topologies and limited device size diversity to yield well. These designs are optimized with new RTL and physical libraries, new floor plans, and power routing to highlight the data path symmetry that is required by the data sets being processed. Examples of this are new 3dmedia processor in 40nm by Samsung for mobile phones that utilize the IMG Tech 3D video and graphics engine and a high-performance ultra low power ARM CPU.

The distributed multicore approach also has been utilized in high performance for lower power products. AMD/ATI introduced the 5970 Radeon graphics card at the Consumer Electronics Show. The card has two GPUs and is a Direct X11 product with more than 4.6TFlops of peak performance. The restructuring of the device/cell library, its reliance on proven 40nm bulk CMOS processing and the use of GDDR5 memory allows the product to operate with a peak power of about 300 watts but only requires 51 watts for nominal operation. The design was optimized for power and a data control flow to support the 3200 parallel stream processors and the 160 texture units. Dynamic power is managed based on how many streams and texture units are needed at any time based on the contents of the data that being processed on any given cycle.

Most of these new systems are targeting use of Samsung’s low-power DDR3 memory, which operates at 1.3v vs. 1.5 volts and offers higher densities than DDR2. These higher-density, low power solutions can provide in excess of 35% overall power footprint reduction for the design, if used with 32nm low-power flash memories in SSD applications rather than rotating media.

The takeaway from CES this year is that architectural engineering and new firmware control methods are now seen as essential to address the functional requirements of the new mobile communication and processing platforms. This is an intelligent shift from recent years, when only feature size reduction and blind tool-based selection of power gating and power routing were in vogue.

By Pallab Chatterjee
As a follow-up to the recent California legislation to impose new energy standards on large screen TVs, most of the flat panels on display at the Consumer Electronics Show this year were on a significant energy diet. To get into the thin form factor, the biggest power draws of the backlight schemes had to be changed.

Samsung’s LCD division demonstrated a number of power savings methods that were similarly implemented by other TV manufacturers. The first area was with traditional CCFL backlight products. Samsung changed the light channels in the set to allow two CCFL bulbs to provide the same brightness and intensity as previous six-CCFL bulb models. There was also work done on the power reduction for “RGB” reference displays that produced 100% Adobe colors. For these models, a reduced bulb set and different power management was used to provide some power savings while maintaining the true color display.

The big buzz has been around “LED” TVs. These are actually LCD flat panels, with LED backlight systems. Some of the models replace the six-CCFL array with a full array of LEDs that cover the back of the panel. In addition to the increased product life, you also get a tremendous power reduction. The big enhancement to these products was the addition of data-sensing circuits that turn these LEDs on and off depending on whether the LCD is displaying light or dark information.

Some of the very-low-power displays have eliminated the full sheet of LEDs and replaced them with edge-based LED strips. These sets have either two strips on opposite sides, or four strips – one on each side. These behave similarly to the two-CCFL backlight designs and are starting to incorporate the data-dependent dynamic control circuitry that will turn tiles of the light on and off to both reduce power and increase contrast.

These enhancements also will be implemented into the 3D models, including the lenticular, glass-free sets targeted for digital signage as they progress in features.

By Pallab Chatterjee
With the release of the EnergyStar rating for servers, there have been a number of approaches to meet the requirements for increasing density and performance. Standards communities such as JEDEC and the 40G/100G networking associations are currently finalizing adoption of the Isolation Memory Buffer (iMB) technology for new high-performance memories.

The use of this technology creates a new class of memory module called the LRDIMM, or load-reduced dual inline memory module. This technology was developed by Inphi, a 10-year-old high-speed analog semiconductor company from Sunnyvale, Calif.

The key issue for modern data centers is how to address growing performance needs while decreasing power budgets. LRDIMM technology is supported by a custom logic controller chip that handles buffering through a standard load interface. The key is a high signal integrity-based memory buffer that has a fixed load to the bus independent of the memory depth behind it. This allows configurations that would be using one bank of memory to support up to eight banks of memory in the same speed and bus power. For compatibility and optimization with multicore CPUs, the iMB interface includes task-based duty-cycle reduction and deep memory idle states.

The iMB parts use dynamic termination of the memory banks to manage power for DDR3 operation at 800, 1066, 1333 bus speeds at both 1.35v and 1.5v operation. These features are also supported through the new JEDEC 1600 spec and will be scalable to DDR4 3200 applications.

The LRDIMMs will be built in Q1 by Hynix, Samsung, Micron, Naya and others using the Inphi chips. The products are currently only for enterprise-class EnergyStar applications as the Inphi chip that is being used costs about $25 in quantities of 100,000. The advantage of the technology is the power reduction and density/performance improvement while still maintaining the 10-12 BER and supporting a single chip/single cycle load for both command and address signa