By Ed Sperling

It was a good week for the low-power world. Synopsys introduced low-power USB 2.0 PHY IP for 28nm processes, which uses 30% less area than previous incarnations. By the way, most foundries and chipmakers believe 32/28nm is a slam-dunk process node/half node. Some have even seen the green light at 22nm, but at 20nm all bets are off. And it looks like low power will be part of the equation at all future nodes.

Actel’s numbers showed the benefits of low power, as well. Q3 revenue was up 4.5% from the previous quarter to $47.2 million—probably the best gauge for digging out of the downturn—and net income rolled firmly into positive turf vs. the previous quarter (as well as the comparable quarter in 2008). These are the kinds of earnings reports everyone likes to see, with the arrow pointed up and to the right of the chart.

Cadence reported its Q3 numbers, which still showed a bottom-line loss, but a much, much smaller one. The loss in Q3 2008 was $171 million. That loss shrank to $14 million in 2009 even though revenues were down $16 million. The company is expecting another loss this quarter as it solidifies its product lineup and gets back on its feet.

Mentor Graphics introduced the latest version of its Open Verification Methodology (OVM) Cookbook for functional verification. Written by Mark Glasser, methodology architect at Mentor, it should at least warrant a response from the Verification Methodology Manual (VMM) crowd, whose last foray into this space was a book on VMM for Low Power. We know all the standards groups will attack us for even bringing up this stuff because there has been a lot of work on interoperability between the two environments, but don’t tell that to the verification engineers who firmly believe in one or the other.

Virage Logic teamed up with MIPS and Open-Silicon to create high-performance test chips at 65nm running at 1.1GHz. They’re also working on 40nm versions that can run at 2.5GHz. What’s interesting for us speed junkies is these also run at much lower power than previous versions of these kinds of chips.

Mentor was touting its analog/mixed signal simulators for verifying wireless hearing aid chips. We’re expecting to see more of these kinds of announcements as chip developers start putting more functionality onto a single chip at advanced process nodes. What else can you do with all that real estate? This is like a nano version of the Oklahoma land grab.

Synopsys recorded a couple of market wins, as well. Nvidia adopted Synopsys’ Yield Explorer technology, which is a significant pre-manufacturing win. Nvidia is calling it DFx, as in design for yield, manufacturability, test, or whatever else might fit in as the third word in that acronym. In addition, Juniper Networks signed a multi-year deal to expand its use of Synopsys tools.

Cadence and SMIC unveiled a 65nm low-power reference flow. The big question in the foundry business is when SMIC will get to 40nm. The company appears to have stalled at 65.

By Ed Sperling

The market seems to be picking up on all sides, even if the hiring hasn’t started in earnest yet. After months of depressing news, there are all sorts of deals being made and had, almost all of them with a low power angle even if that’s not prominent in the announcements. These days, low power is a prerequisite.

The FPGA world seems to be getting lots of attention these days. Aside from a slew of prototypes being built in China with FPGAs, the tools for developing FPGAs are are improving. In fact, they look a lot like the tools being used for ASICs and SoCs these days.

Mentor Graphics introduced logic and physical synthesis support for Xilinx’s Virtex-6 and Spartan-6 lines. Cadence and Xilinx also joined forces to add encrypted simulation models of Xilinx IP with complementary simulation models from Cadence. Xilinx, it appears, has been very busy.  And Actel and Synopsys renewed their OEM relationship for design software for Actel’s low-power FPGAs.

Design activity seems to be picking up in China in recent months. Synopsys inked a deal with Shanghai-based foundry SMIC for a 65nm reference flow. Synopsys contributes the Eclypse Low Power technology and Galaxy and SMIC contributes…well…the customer base to use the stuff. What’s interesting is just how quickly SMIC got to 65nm. Last we heard, their volume market was 180nm.

In the processor world, Intel’s purchase of Wind River passed another regulatory hurdle and the company signed a development deal with Nokia. Those are foundational moves. Whether Intel can break into new markets with this strategy is still in question, though. It depends on just how low it can get the power requirements for Atom.

And if anyone has doubts that there is still money in the consumer market, Apple sold 1 million of its new iPhones in the first three days of its launch. That’s a lot of electronics. If Apple begins designing its own chips, that’s going to require a lot of system-level design tools, as well.

By Ed Sperling

Intel will pay $884 million to buy Wind River, a move that will open all sorts of new doors for Intel’s new Atom processor in markets demanding much lower power. By writing software directly to cores, this could prove a huge gain for Intel—sort of like owning your own fab. But what else will the company have to buy as we head down to 22nm and beyond? 

Maybe the printed circuit board technology? They aren’t laughing about that at Mentor Graphics. The company continues to invest in its PADS 9.0 flow for board-level design, which increasingly is become part of the extended SoC design. If you can’t build it on the chip, you’d better account for it somewhere and figure out what the penalties are. 

China seems to be on a technology acquisition kick—and making major strides in chip design. Shanghai-based foundry SMIC is using Synopsys’ HSPICE Simulator for 45nm physical IP and standard-cell development, and the Chinese Academy of Sciences is using Cadence’s Incisive Xtreme III System for next-generation multicore processor validation. Put the two of these together and you have an interesting picture of what’s been going on behind the scenes during the downturn.

Synopsys unveiled the first DDR3 IP verified in silicon at 1.6Gbits per second. That’s the maximum data rate of the JEDEC DDR3 spec. Who needs muscle cars when you can rev up your phone? Do they have an application for that, too? Synopsys also introduced multi-corner, multi-mode capability for design closure in IC Compiler. Things are getting very complicated, indeed. You can’t even describe that upgrade without taking a breath.

And meeting our intrepid blogger Markus Levy’s complaints head-on, ARM announced support for the EEMBC CoreMark Benchmark. It’s always nice to have some metrics that work, and it doesn’t hurt that ARM has been on EEMBC’s board since 1997.