By Ed Sperling

Doing Business In 3D
IMEC, the Belgian research house, and Synopsys have teamed up to create 3D vertically stacked chips. This topic has received a lot of attention of late, in large part because analog engineers are nearing open rebellion over the need to keep pushing their technology down each process node. A good analog process can last a decade or more, and just re-doing it to put it on the same chip doesn’t make sense.

The missing piece in all this is the through-silicon via, which has been under development for several years. The collaboration is aimed at speeding the development of TSVs and saving the design world from having to re-do everything at 28nm and 22nm. The thought of analog at 11nm is entirely too much to comprehend.

Greener Marines
Green is sort of a natural color for the U.S. Marines, but you don’t exactly associate Marines with green technology. As it turns out, though, battery life in war is critical. According to an announcement issued by the U.S. Marine Corps, “Reducing resupply needs also keeps Marines safer. Fewer trucks on the road decrease Marines’ exposure to the improvised explosive device and other dangers.”

At least part of the effort is on renewable energy at Marine bases. But experiments by the Marine Corps Warfighting Laboratory are now fusing together off-the-shelf technology for renewable energy and lower energy consumption military equipment. The Laboratory, according to the release, “conducts concept-based experiments and integrates operational concepts with how the Corps operates and fights. Experiments coupled with other research improve the expeditionary warfighting capabilities of the Marine Corps today and far into the future.”

End Of The Roll?
Kimberly-Clark has been closely watching the printed electronics market, according to IDTechEx, a British consultancy working in this market. Kimberly-Clark, which makes a variety of paper-based products such as tissues, says that printed electronics would are very useful in controllable heating and electronic sensing. But there are still a couple of hurdles to work out. First, the price is too high. Second, most of the company’s products are disposable, which makes electronics “just not practical, safe or cost-effective.”

By Ed Sperling
Think about any mobile Internet device today. Batteries typically last all day, applications shut down with ease, and the number of things it can do has reached the point where many people typically carry one device on the road rather than multiple devices they used to lug around several years ago.

Perhaps even more astounding is the price drop on these devices. A basic cell phone five years ago cost hundreds of dollars. Add to that an MP3 player for a few hundred dollars, a GPS system for a few hundred more, and portable gaming systems fore even more. All of that now runs on a single chip, often at the most advanced process nodes where real estate is plentiful.

But getting to this point, and moving further is showing pain points across the supply chain—particularly as power becomes a critical part of every facet of the design. What used to be a simple tradeoff between area and performance is now tilted heavily in favor of power. Software that used to be written independently of the hardware now must be written in conjunction with the hardware—even at the application level.

All semiconductors begin with the architecture and the design. But devices like a mobile Internet device begin in reverse—they gauge user demand, weigh the cost of development, and develop the spec that feeds into the supply chain all the way down to the semiconductor.

No pain, no gain
What’s interesting is just how many pain points are scattered throughout the supply chain that are affected by power. At the uppermost level, the biggest issues are business context and time to market. The Blackberry, made by Research In Motion, developed a killer application for corporate e-mail that allowed it to initially sew up the corporate market. The Apple iPhone added a slew of other applications, with e-mail initially almost a secondary issue.

But what plagued both devices, at least initially, was the limited battery life. Those issues are improving, thanks to some enormous leaps in engineering in every facet of the devices. Even PCs can now last most of the day, depending upon the applications being used.

Sandwiched between the high-resolution screens and the lithium-ion batteries, though, those gains haven’t come easily—and they may be significantly tougher to achieve at each future rev of the components inside those devices.

“Our biggest challenge isn’t even in the engineering,” said Nick Ilyadis, chief technology officer for Broadcom’s enterprise networking group. “It’s customer requirements changing on the fly. OEMs come in and change the features very late in the design cycle—sometimes right before tapeout. They’re developing Brand Y and they see Brand X change their product at the last minute.”

One solution is being agile—making changes whenever possible in firmware or software. A second is being aware of the market trends. “Our customers tell us what they want to tell us, but their holding back can create a problem,” Ilyadis said. “Our solution has been to talk to the end user. We need to get to the end user to be pre-emptive.”

On mobile platforms, Broadcom has developed its own power management capabilities. It also has been working with power islands for several generations, allowing changes in performance and power on a per-cell basis.

But at each node, there is more to put on the chip—and a far greater number of issues such as leakage and mixed-signal integration and verification. Lisa Su, senior vice president and general manager of Freescale’s networking and multimedia division, said the big challenge in her organization is how to put a base station on a chip.

“Integration is the problem,” she said. “Multicore communications processors are quite different from a PC. You’ve got up to eight cores and some of them are used for accelerating the other cores. So you’ve got to integrate those accelerators. The question is how do you optimize the processing performance and the acceleration without adding more power. You can put eight cores on a piece of silicon, but the challenge is to get eight times the performance.”

Su said that the challenge is figuring out what to integrate and what not to ingegrate. “How do you get 24 hours of battery life,” she said. “There’s a very complex tradeoff between hard wired and programmable. For this, hardware-software co-optimization is critical, and there’s a lot of momentum in this area. We’ve grown by leaps and bounds in this area. If you take the same piece of hardware and software and you optimize the software, you can increase battery life by two times.”

Doing more with less
The problems felt at the board-level and the SoC-level are only magnified as you move down a couple of notches into the blocks and technologies that reside on a piece of silicon.

“Low power touches on everything you do, from the logic through the physical process and up into the software,” said George Zafiropoulos, vice president of solutions marketing at Synopsys. “You can do everything to make the hardware efficient, but power efficiency also now depends on the behavior of the software.”

Zafiropoulos noted that even at the top of the product development cycle, power is now a major consideration. “It’s often a question of cost and the difficulty of implementation vs. the benefit of low power,” he said. “To make a chip with 30% less power is great, but if you leave the iPhone modem on you’re going to blow the power budget. You have to address this at the system and the software level as well as the component level.”

Chipmakers also have to bring together teams of hardware and software developers to work in tandem rather than independently, which is not something that comes easily to them. Broadcom has created what it calls “chip leads,” who are engineers that can bridge the gap between the hardware and software engineers. They basically work as translators back and forth between the teams as they move down the line toward tapeout.

Zafiropoulos said that has been a big barrier for some companies. “Power is forcing conversations between software and hardware development teams,” he said. “This started on the process side with CMOS. Then it moved to logic. In the last 10 years, the design circuit was gate clocked. The next wave will be software. The problem is that every time you push the limit on power, the response from engineers is to guard band. They over-engineer, which takes more power.”

Connection overload
Part of what has made devices so power hungry also is a result of the I/O—the connection to the outside world. Every device needs to be connected, and the more bandwidth the less wait time for downloading everything from text to videos.

“One of the grand challenges we’re facing is layer one in these devices—the radio receiver and transmitter,” said Chris Rowen, Tensilica’s CTO. “Bandwidth is an order of magnitude higher, but the power budget is 50% lower. How do you get a factor of 15 in energy efficiency and still include the supporting standards.”

He said this is particularly troublesome with LTE, which holds the promise for lower power but so far has never been implemented. “The challenge is how you get there in the first place, how you get there quickly, and how you get there within the power envelope.”

Part of the challenge is also in the basic wiring structure. Charles Janac, chairman and CEO of network-on-chip vendor Arteris, said that from a physical design standpoint there simply are too many wires. “That’s causing congestion points and problems with timing closure,” Janac said. “Then we’re stuffing hundreds of thousands of transactions per second down those wires.”

Those wires also get thinner at each new process node. Janac said the solution is a single point-to-point connection rather than a multiple wire mesh structure. While the mesh bus structure sufficed at older process nodes, it doesn’t have the speed or the flexibility if changes need to be made to the design—which they often do.

Hot spots
One issue few people are talking about—but which many companies are watching, somewhat warily—is what happens when there are too many connections. Connections internally are problematic, but the ones outside the chip generate heat.

“Down the road, there are still serious concerns about temperature,” said Jim Davis, vice president of software and systems engineering at Actel. “The parts are getting bigger and bigger because we’re basically getting gates for free, but the I/O’s don’t scale with the gates.”

Add to that static power leakage, which is becoming worse at each new process node, and the amount of heat that needs to be dealt with can cause serious problems.

Some of these problems, most notably the analog design portions of a chip, are actually better dealt with at older process geometries. In fact, there is almost no advantage to doing analog at advanced process nodes except to keep it on the same piece of silicon. That has prompted a variety of different responses—everything from programmable analog on an FPGA to high-speed interconnects between chips and research into 3D stacking.

The low-power crystal ball
The list of pain points goes on and on. But what is becoming clear to more people—and companies like IBM have been preaching this for most of the decade—is that design needs to become more holistic. That’s easier at an integrated device manufacturer like IBM or Intel, however, than in a disaggregated commercial chip development world.

“Low power has to be dealt with in a holistic manner,” said Nizar Abdallah, Actel’s director of engineering. “You need to deal with all possible angles at the same time, starting with the technology and the process. Then you have to look at the features, fabric and modes.”

For fabless companies, this requires coordination not only of internal hardware and software teams, but with the architectural teams of all companies in the supply chain and all the tools vendors that service the supply chain—something that points firmly toward an industry filled with more standards.

“In the beginning of chip development, the only people who could attack the problem were the ones who could design from scratch,” said Cary Chin, director of technical marketing for low power solutions at Synopsys. “Standards allowed more companies to create chips. Low power is headed in that direction. And what is successful is not always at the bleeding edge.”

By Ed Sperling

Low-Power Engineering moderated a panel featuring Bhanu Kapoor, president of Mimasic; John Goodenough, director of design technology at ARM; and Prapanna Tiwari, CAE manager at Synopsys. What follows are excerpts of their presentations, as well as the question-and-answer exchange that followed.

Bhanu Kapoor: There are two types of power you need to consider: Dynamic power, which is consumed because you are doing some useful activity, and leakage power, which gets consumed whether you’re doing something or not.

The dynamic power has dependence on switching activity, the frequency, the capacitance and the supply voltage. There are two components of leakage—sub-threshold and gate tunneling. Gate-tunneling is addressed by advances in process technology such as metal gates. Sub-threshold leakage grows exponentially with the decrease in threshold voltage. At 90nm it was significant, at 65nm it was equal to the dynamic power, and it grows from there.

If you look at the typical smart phone, it’s the same system-on-chip that is running different applications. These different modes of operation have different performance requirements. You can use different voltages to achieve those different levels of performance.

A typical power-managed SoC includes a power-management IC that provides different cores. One core can be a processor. And if it’s an ARM Cortex A9, there is power management in that core, as well. A second core might be for mixed signal, which potentially could require higher performance. And then this power controller, which is on all the time.

All of these power techniques have an implication on verification.

If you look at standby leakage, one of techniques is power gating, which is cutting off power to certain regions. If you don’t need portions of the chip to be on, you can completely shut it down. That is power gating. But that has an effect on performance, because turning on and off a function is a long event compared to a clock cycle. You need to sometimes retain the state so you can come up fairly quickly.

All of this has an effect on verification, as you can see from the following chart.

If you can do gate-level simulation, that is very helpful. You need input/ouput and power connected and you need to have appropriately modified your library definitions so power is one of the variables. With domain isolation, once you shut down you have to make sure you are not sending floating values to other regions. You have to isolate it to proper ones and zeros, which you can check with isolation gates using a rule-based checker.

If you have power in your simulation, a lot of rule-based issues can be addressed right up front. Over the years, simulation was not power aware. In the future, simulation will take a more and more important role. Simulation, by default, will incorporate power.

John Goodenough: We are verifying systems on chip. They’re large. They have lots of power domains to match all the application workloads that are going to be demanded on those devices. They have processors and software. Some of the domains are being switched on and off to meet the energy profile. They have virtually every technique available. The state space you’re trying to validate is therefore exploding by an order of magnitude.

One of the things we think about a lot at ARM is that it’s not so much the techniques that you can apply. It’s how you’re going to scale them to tackle these problems. There are lots of clever ways to validate, but not all of them scale effectively into workflows and onto your infrastructure. Power verification is not just about logical verification.

If you get a chip like the one below, you can mess it up in a lot of different ways.

Usually, you can fix it in software. But you also can mess up the connectivity between the power domains. If you get your level shifter or always-on buffer or retention register wired up wrong, it’s not going to work. It’s going to be D.O.A. on the bench. A lot of chip failures are being caused by the failure to verify the integrity of the power network.

That’s a non-standard piece of verification, particularly where that interacts with the logical function of the chip and you’re trying to measure the maximum in-rush current and the average in-rush current. If you’re switching domains on and off, what’s the power domain going to look like from an electrical perspective? Is turning one domain on and turning another domain off going to put the voltages on either side of a level shifter into a pathological state that will damage or degrade the transistors and the level-shifting buffer?

There are some very interesting cross-coverage issues between what is traditionally more of the analog verification space on the power network and the logical verification space. We need, when considering power simulation, to run abstracted analog simulations, SPICE-level simulations, and cross between the two.

Unfortunately, the explosion in power states is also increasing because of the number of software states or the number of field configuration states. From a verification standpoint, not only are you adding a multiplier due to power states, you also have things like a secure or non-secure state. Will they work when a chip is configured for a single package and pinout if it uses another package and pinout? There’s an explosion in these operating modes.

The other pressure we have is making sure you’re going to hit a given schedule. In looking at the power metrics it’s important to see how they can be applied into practical workflows and how you can feed performance metrics from wherever you are in the process back up into reporting and closure reporting. If you combine the need for those two, one of the things it leads to is enterprise scaling, both in terms of infrastructure to support the simulation and how you scale this across workgroups that are not co-located.

The other problem you face is that if you do all of the verification, you’re never going to get the chip out the door. You’ve got to have a verification plan and really narrow down which of the power modes are going to be pathological and which ones can be worked around in software. A major part of thes power verification is the integration of a VP of engineering risk-reduction play into a more mainstream verification practice.

We’ve come a long way in a lot of the techniques, but at the end of the day you have a block diagram that needs to be simulated. Today that block diagram consists of RTL and some way of describing the power network or the power intent and power state space of the design. You also have to support the verification IP and transactors. You need coverage across the RTL and the power descriptions. It’s not rocket science. It’s just a more complicated block diagram.

By Brian Fuller
Silicon CMOS is a tough act to follow. The workhorse building block for the world’s electronics has been delivering for system designers for a half century. Despite hand-wringing over its apparent scalability limits, it shows only vague signs of slowing down.

For nearly as many years, it seems, the next great material or alternative to silicon CMOS has popped into the industry’s consciousness promising to be the next big thing—next year. Gallium arsenide, for example, has been next year’s hit technology for four decades.

The latest “it” material, however, could actually deliver on its early hype, and in the process enable the industry not only to continue scaling but to drive deep into previously unexpected depths of low-power design. Graphene—the two-dimensional crystalline form of carbon—first emerged as a term in the late 1980s and gained traction in 2004 when researchers at the University of Manchester extracted graphene layers from graphite—basically using Scotch tape—and then placing on silicon dioxide on a silicon wafer.

This time it’s different (maybe)
The material exhibited fantastic characteristics, including high electron mobility compared to silicon, twice the storage capacity of ultracapacitors, and it was rugged to boot. What’s more, its characteristics apparently remain stable down to the molecular level, unlike other materials used in semiconductor design. The graphene promise is such that in just the past three years, research papers are being written on graphene at the rate of one a day.

“There are two features that make graphene exceptional,” Kirill Bolotin, assistant professor in the Vanderbilt Department of Physics and Astronomy, said in a recent interview. “First, its molecular structure is so resistant to defects that researchers have had to hand-make them to study what effects they have. Second, the electrons that carry electrical charge travel much faster and generally behave as if they have far less mass than they do in ordinary metals or superconductors.”

Where some see glowing walls made of graphene circuitry and other exotic applications, people like James Meindl see an answer to scaling. Keynoting at the recent ISSCC (International Solid State Circuits Conference) in San Francisco, Meindl, director of the Joseph M. Pettit Microelectronics Research Center at the Georgia Institute of Technology in Atlanta, said: ”We will continue to scale vigorously for the next 15 years. Beyond silicon microchip technology, revolutionary developments in nanoelectronics, perhaps centering on graphene, may evolve.”

That’s music to the ears of many who, despite CMOS’s dogged determination, seeing scaling hitting a wall in the next decade.

“Look at Intel’s roadmap. They’re looking at 4nm in 2022,” said Michael Keating, a Synopsys Fellow. “As long as they’re charging down that road, graphene’s going to be a second-class citizen. But my guess is 2022 is not realistic for 4nm. Silicon will be seriously in trouble in that decade.”

“The reason graphene’s interesting is so much progress has been made in such a short time frame,” he added.

What’s all the fuss?
Graphene—a one-atom-thick planar sheet of sp2-bonded carbon atoms that resembles chicken wire—has a lot going for it.

Meindl, speaking at ISSCC, gave a half-dozen reasons graphene is going to win in the marketplace, including:

• No other known material has a higher mechanical strength-to-weight ratio.
• Carrier mobility exceeds 200,000-cm2/Vs.
• The capacity to conduct current densities as large as one thousand times greater than copper without electromigration.
• Graphene can serve as a source, channel drain regions of a field effect transistor (FET) and as an interconnect.

In addition to all the big talk, there’s been action.
• Fujitsu Laboratories Ltd. has developed a method to form graphene transistors directly on the entire surface of large-scale insulating substrates at low temperatures while employing popular chemical-vapor deposition (CVD) techniques.
• IBM in 2007 fabbed graphene field-effect transistors (FETs) using a single layer of carbon atoms atop a silicon wafer at its T.J. Watson Research Center at Yorktown Heights, N.Y.
• In February, IBM built, on 2-inch wafers, RF graphene transistors running at 100-GHz and operating at room temperature.
• At around the same time, Penn State researchers announced they have developed a way to fabricate graphene sheets on 4-inch wafers.
• Last year, Bolotin, working with colleagues at Columbia University, managed to get graphene to exhibit the fractional quantum Hall effect, where the electrons create new particles with electrical charges that are a fraction that of individual electrons, according to work published in the journal Nature.
• A venture-backed Austin, Texas, company, Graphene Energy, is working to commercialize graphine for energy storage.
• Javad Rafiee, a doctoral student at Rensselaer Polytechnic Institute developed a method of ultra-efficient hydrogen storage based on graphene. His approach stores hydrogen with 14 percent efficiency, better than any other material attempted to date.

What’s the catch?
There’s always a catch. While graphene is easier to manufacture than its cousin, the carbon nanotube, it’s no slam dunk yet. To date, there hasn’t been a simple way to create the p- and n-type devices required for CMOS transistors. But Georgia Tech recently reported it has used an electron beam doping process that simplifies the transistor manufacture.

In addition, graphene has no band gap so there’s no way to turn them “off.” But even that hurdle is being brought down. Researchers at Lawrence Berkeley National Lab last year engineered a controllable band gap in bilayer graphene—at room temperature.

When will we know when graphene gets the “next-year’s technology” monkey off its back for good?

Maybe relatively soon, suggested Synopsys’ Keating.
“CMOS has had an incredible run. It’s foolish to bet against CMOS. (But) graphene every year makes significant progress. It’s absolutely the promising thing right now. We’re a decade away.”

Today’s advanced process technologies and faster time-to-market schedules are pushing the limits of verification tools. Post-layout simulation runtimes are increasing 2x to 4x with every new process generation as chip transistor counts double and new parasitic effects come into play. Designers of custom digital, analog/mixed-signal (AMS) and memory integrated circuits (ICs) must now manage an ever-increasing volume of post-layout data while meeting the razor-thin design margins and tight project cycle times. These conflicting challenges are driving the need for more accurate and efficient parasitic extraction and simulation solutions to accelerate verification and achieve first time right silicon. The Synopsys StarRCTM extraction solution offers a wide range of features to boost the simulation performance and capacity of transistor-level designs while preserving signoff accuracy. This paper presents these innovative extraction techniques for high-performance and high-capacity simulation.

Actel set the FGPA market ablaze with its new SmartFusion device, which combines programmable analog with a complete microcontroller subsystem and an integrated programming environment, including tools. This is an interesting move, and it will be equally interesting to see how long it takes Actel’s top rivals to respond. Actel insiders, most of whom came from Xilinx and Altera, say the catch up period may be quite lengthy. They may have a bone to pick, but the low-power angle is definitely interesting. This also should grab some attention from the companies that have been developing multichip solutions because they don’t want to deal with integrating analog and digital.

Mentor Graphics announced its fiscal Q4 financials for the full year ending Jan. 31. Revenue was $802.7 million, up 2% from fiscal 2009. Non-GAAP earnings per share more than doubled to $0.47 per share, while the GAAP loss was $0.23 per share. That’s a lot better than a loss of $0.99 per share. For the fiscal Q4 Mentor revenues of $237.1 million, non-GAAP earnings per share of $.30, and GAAP earnings per share of $.39. As Mentor chairman and CEO Wally Rhines pointed out, “the electronics industry recovery seems to be well underway.” Break out the champagne—but don’t spend more than $8 a bottle or the corporate accounting department won’t approve it.

Synopsys bolstered the capabilities of its System Studio C/C++ analysis and simulation environment. The product now includes support for matrix and vector data types, which the company says significantly reduces coding and debugging efforts.

The Taiwanese earthquake earlier this week registered 6.4 and cost about 1.5 days in wafer movement from TSMC’s fabs in Tainan. This was a big earthquake, but the impact was slightly less near the Tainan fabs.

You have to wonder about Wall Street. Marvell beats estimates by $500,000 and the stock tumbles. According to analysts, the company didn’t beat estimates by enough. Isn’t the whole point to meet estimates?

Intel added the Atom processor to the networked small office/home office storage market. What’s interesting about this announcement isn’t Intel’s push into this market. It’s that there is now a dual-core version of Atom available. This should make for a nifty ultra-low power solution.

Low-Power Engineering sat down to discuss parasitic extraction with Robert Hoogenstryd, director of marketing for design analysis and signoff at Synopsys, and Carey Robertson, product marketing director for Calibre Design Solutions at Mentor Graphics. What follows are excerpts of that conversation.

LPE: What changes with at 22nm and beyond with structures like FinFETs?
Robertson: It’s not only parasitics. It’s also BSIM (Berkeley short-channel IGFET Model) or PSP (Penn State Philips) models. They’re going to have to change, as well. We will start seeing DOE’s this year, including version 1.0 of SPICE manuals from foundries. Is there going to be a paradigm shift? I don’t know. But their aspect ratio is different. We have to respond.

LPE: It’s also a lot more data, too, right?
Robertson: Yes, it’s a lot more data, as well as new dielectrics. We don’t have the full picture about what are the dielectric constants, are they going to be conformal, what are they going to look like. And part of it is what rules are going to be mandated. The more we can constrain the problem to say, ‘This is how you’re going to implement contacts around the FinFET region and you have to do it maximally contacted,’ that’s good news for us. It allows us to constrain the problem. If you want to let designers be as creative as they want, so you have one contact here for the source and another contact here for the drain, that’s great for them but difficult for us to deliver the accuracy.
Hoogenstryd: We’re already working with foundries in that area. It’s going to impact the model and what’s important from an extraction point of view. We seem to have the problems at every process generation and bright people always figure out how to get through the noise—even though it takes time—and model what’s important. One of the challenges for new structures like FinFETS is that as EDA vendors we have to make investments ahead of the curve. This is an area that is potentially costly. Customers want us to experiment with them at our expense. Hopefully by the time things get settled, they want us to be there with commercial solutions. But we still don’t have it as bad as the litho vendors. The lead time on getting lithography ready for production is long, and there’s a lot more experimentation at that end. They may take 20 different approaches knowing that one or two will work out, and they want all their suppliers to investigate with them.

LPE: How does 3D stacking affect parasitics?
Hoogenstryd: From a practical point of view you can look at each chip, but instead of between packages you now have things like TSVs (through-silicon vias). You have to model that. There’s a lot of investigation about what’s going on between the TSV layers and the bottom side or top side of the chip that’s being connected. People are not convinced yet that the economics are there for this to be a mainstream packaging solution. There are a lot of companies doing investigation and test chips.
Robertson: There is a modeling issue beyond the traditional metal stack. It can be accounted for. But it’s not just the interaction of the various layers. It’s also what is the model of this TSV. It could be modeled like a MOSFET. It could be modeled as a parasitic. But its geometries are much different than the interconnect around it. There are inductive effects that most customers are not taking into account when they develop standard chips. Unless you’re in analog or mixed signal you don’t really think about the magnetic field. TSVs have that. There’s also a big netlisting and integration issue. If you’re compartmentalizing and building things up and here’s a memory above a core to get the proximity benefit, you can model them differently with some interaction. But when you try to do critical-path analysis and that path spans multiple TSVs, you need an extraction that will span different die and potentially different technologies if you mixed 65nm with 40nm. Where this may go is, if customers are designing L1 and L2 cache among four dies and getting the extraction/simulation done correctly, that is going to have profound impact on the entire infrastructure. That includes extraction, netlisting and simulation. That is probably very cool for the designers.

LPE: Is heat a big problem with that?
Robertson: Thermal is a big deal. The other problem on the device extraction side is stress. How big of a contribution is silicon stress? And as we get to TSVs, stress is an even bigger problem. Stress impacts both leakage and power consumption. Sometimes it’s beneficial and sometimes it’s not. So both stress and thermal are going to require more of a focus.

LPE: So looking out ahead what are the big problems that were likely to encounter at 22 nm and beyond?
Hoogenstryd: We’re already in the midst of 32/28 nm modeling. We’ve been working on that for quite a while. I don’t think the work is quite done there because this node is not in full production. There is constant work going on at the silicon foundries. They find new things they need to model to get a more accurate silicon representation. We’re already working with some foundries at 22nm, where the FinFET is going to be first introduced. It’s that constant challenge of keeping up with the modeling. The 3D IC has some implications on the modeling. Another challenge is just helping customers be more efficient. Right now the pressure on the design team of doing a bigger chip with the same resources is a problem. The answer is not throwing more CPUs at a problem. Capacity is in many ways a bigger issue than CPU runtime. These chips are bigger and you have to run your software in the same memory footprint constraints. And it’s working more with customers to focus beyond this one tool.
Robertson: What customers have been saying is they want more accuracy. Even though design is getting more complicated they can’t deal with capacitance and coupling capacitance. They want more accuracy even with all those challenges. Both Synopsys and Mentor have initiatives to change the way we do extraction and bring in field-solver technology to have the best accuracy possible. That’s a first step, but it becomes harder. If you can deliver accurate R’s and C’s, you have to put that into a system. But that system becomes more and more unruly. It’s not just one effect. It’s capturing the variation. It’s capturing what’s happening in the transistor. And then it’s providing that information. We can provide gigabytes of data, but the issue is whether you can provide the right amount of information for the analog designer to do impedance matching and rotate the device and get highly accurate SPICE-like simulation. And can we also provide the right level of information and abstraction for the digital engineer or the rail analysis person with high accuracy?

Low-Power Engineering sat down to discuss parasitic extraction with Robert Hoogenstryd, director of marketing for design analysis and signoff at Synopsys, and Carey Robertson, product marketing director for Calibre Design Solutions at Mentor Graphics. What follows are excerpts of that conversation.

LPE: Does parasitic extraction get more complex as we move into multicore chips? And if so, why?
Hoogenstryd: Yes, and the challenge is that customers are trying to deploy hierarchical methodologies on chips. The goal is that you’d like to be able to re-use as much as you can in circuits that you duplicate, but you have this challenge where you need to be able to accurately model the effects between the block interactions. For example, coupling capacitance is a big thing in that area. You need be able to model the effects of this block connecting with this block, but you’ve done extraction in isolation because you did it as part of the IP development. The big challenge today is people coming up with effective hierarchical methodologies that don’t double count or don’t miss the data when you put these things together and analyze everything in context.
Robertson: Multicore means more hierarchy, and hierarchy makes sense from an intuitive perspective because you can build things up. But what you’re going to do is create a model for your cores in isolation, and that’s not how they’re going to perform. You can’t do things things flat, so you have to make some tradeoffs. How the circuit performs in isolation isn’t the same as having four or eight of these put together. The noise and the coupling are much different. Getting beyond timing signoff or some other analysis to say you’re not going to have coupling or noise issues is going to require some combination of heuristics, guard-banding and extraction to make some estimation of how these cores are going to operate on a chip. What we really want to do is characterize them by themselves. They may all behave the same, but you need to analyze that, as well.

LPE: How much does dropping the voltage affect all of this?
Robertson: Customers aren’t just dropping the voltage. They’re also really pushing on voltage analysis, IR drop and power rail analysis to identify at this low voltage node what really is Vdd for every one of the devices. And at what time? They may need a very accurate RC network of the power line, which is humongous. Then you have reduction techniques or simulation techniques on top of that to identify what’s the Vdd at what time for every one of these MOSFETs. It’s very difficult.
Hoogenstryd: There is no consistency among customers. We see some customers in design teams pushing the limits where they’re trying to get the voltages as low as possible. They need to do all this analysis to make sure the IR drop doesn’t force this thing to drop to a voltage where a device doesn’t work anymore. And then there are others who want to employ hierarchical design methodology but they don’t want to think about hierarchy. They just want to put things together and have it work. And then there are others who take much more practical approaches. I’ve been with customers doing low-power designs and we talk about IR drop analysis and they say they don’t need it. They just design really good power rails. They guard-band. They over-design because yield is a concern. There are companies today doing multicore design where they guard-band their IP blocks. They shield them. So they try to solve the problem through a design technique rather than trying to rely on after-the-fact analysis to make sure that everything is going to work in an environment that was unpredictable. They use design techniques to try to make things predictable. There are various levels of that. I’ve even seen companies that are very concerned about area using some of these design-for-practicality techniques. They know they might lose a little in silicon area but they get better yield. There is really a lot of variability in how customers are trying to solve this problem. Some use more analysis, more details, more information. Others are just trying to design the problem out.

LPE: How much time is parasitic extraction taking? Is it increasing?
Hoogenstryd: It’s still miniscule compared to the verification. I hear from customers that they want parasitic extraction to run faster. Every year they’re asking for 2x, 3x or 5x increases. For some reason they think we can magically change our code and run it 5x faster even though we’re extracting more data. But they are spending a lot more time on the analysis side. Where they’re really feeling the pressure on the digital side, particularly with extraction driving place-and-route flows, is in the ECO (engineering change order). They want to do an ECO overnight. That means they want to take the place-and-route data, go through timing analysis, ECO optimization, and back into place and route within a day. They’re pushing on every one of the tools in that tool chain to be faster. It’s the same on the analog side. They want to be able to turn around their simulation analysis or other types of analysis very quickly. The natural thing is to push the tool faster. What we’ve been trying to do is change the customer’s mindset to focus on the end goal and how to make the whole flow faster. You need to look at how you’re running your extraction, what you’re using that data for, and how to make that data accurate but more efficient. It’s a multi-prong approach. Extraction is part of the analysis flow.
Robertson: People are budgeting a lot more time for LVS turns or DRC turns because they understand they need to iterate through those until it’s clean, and then you go into downstream extraction and simulation. The amount of time budgeted is definitely more on the verification side. But people aren’t only pushing this for performance. They’re being asked to do more. It’s not just timing closure, and it’s not just timing closure on one corner. Customers want to do 5 or even 25 corners, but they don’t have the time. Getting raw performance isn’t necessarily the answer. It is intelligence around your overall methodology. You won’t get more time. If you get four weeks for verification and two days for extraction, you’re not going to get two weeks for extraction. But if they’re going to fit in these various tasks around corner simulation and rail analysis and signal integrity it is about how we feed those analysis tools appropriately. That’s a real struggle. We need to step back and say, ‘How do we come up with an intelligent corner methodology approach and power analysis, and can we perhaps do one extraction to feed all these other goals?’

LPE: There are two forces at work here. One is that everything is closer together. The other is there’s more real estate, which means you can cram more on a chip. So don’t you have to analyze more simultaneously?
Robertson: Yes, you do have to crunch all of these polygons and the electrical field is more complex and there are more of them and there are more R’s and C’s. And there are more analysis tools downstream, so it is more analysis in less time. But we do find customers, whether they realize it or not, customizing it themselves. Everyone is following foundry rule decks and foundry device models. There are plenty of things the foundry will do. In that extra time, customers are coming up with design flows that are custom to them. If you look at five fabless companies, they have different ways of doing designs to optimize what they think they do well. It may be low power or wireless methodologies. We’re doing more on the verification side to accommodate their design styles with customized verification flows, even though underneath that there’s been a standardization of rule decks, extraction methodologies and device models. They need new design techniques, new verification techniques as well as new extraction flows.

LPE: Are companies getting to the point where they’re looking at good enough instead of checking every corner case?
Robertson: No one has ever said that to me. Inside of companies, I’m sure that’s happening. But what we’re hearing is always more accuracy, more reduction, more speed—either now or for the next node.
Hoogenstryd: Customers are using multiple approaches. One is to push on their suppliers to make the tools faster so they can do a chip that’s four times bigger at the next node in half the time they did it at the previous node. In Japan the mantra is 5x. They’re struggling with a chip that’s 2x bigger. With their budget constraints they have to stick with the computers they have. They can’t buy any more hardware. But this new chip is going to have more functional modes. Therefore they have to do twice as much simulation on a chip that’s twice as large with the same hardware resources. So they ask us to make the tool four to five times faster so they can do it in the same time with the same resources. That’s one prong. The other approach is to come up with practical solutions to get their arms around the problem. Say you have four voltage islands in a design. If you want to capture all the end cases with static timing and each one can turn on or off, or go from a high voltage to a low voltage, to find the critical path across the blocks you have to simulate or analyze 16 different voltage combinations. They come up with methodologies to model around it, coming up with different scenario combinations. They may spend more time up front doing some analysis to figure out what are the critical corners they have to analyze at the chip level or the block level to guarantee you capture the boundary techniques. Each customer has a different threshold of risk, too. Some companies have multiple spins built into their strategy. They know the third spin is the one that goes into high volume.

LPE: Are companies worried about problems they can’t solve?
Hoogenstryd: Yield is the big thing customers are worried about. In my opinion, this push to get everything closer and closer together while being worried about 90% yield seems to be a crazy tug of war. The closer you put things together, the more likely you are to have a yield problem. For customers, density is not the issue. The average chip size hasn’t changed much in the past 20 years. But at 22nm, how many companies can come up with IP to fill that chip other than putting more and more memory on board. The rules in DRC have exploded to compensate for the lithography and CMP effects. There’s a debate about whether we continue pushing things closer together or whether we go to restrictive design rules, which may not be as efficient from a silicon area, but it does simplify the flow and make it more productive.
Robertson: When a customer does a DOE at the leading edge and the silicon is varying 20% or 40% vs. simulation, they usually ask us to help find the error and figure out whether they’re compartmentalizing the problem appropriately. We have all of these techniques to identify how the silicon performs. There is geometric variation that needs to be captured. Is it simulation-based or table-based? Is that the source of the error? Is it silicon stress? There are all of these effects. Some are in the device model. Some are printing of the wiring and the devices around them. And then there’s the actual calculation of the parasitics in the simulation. In the past, 65nm or 90nm, if you had a DOE with poor performance you could find the tall nail. Now when customers ask, it’s a combination of these effects. It’s probably 5 or 6 things that need to be fixed. And that’s at 32nm. At 22nm, with FinFETs, that’s going to be really interesting.

By Ann Steffora Mutschler

The responsibility of semiconductor test has long sat solely with the test engineer as the chip designer focused on the functionality of the device. However, particularly in low-power designs, when the device is being tested, much higher power levels are applied than normal functional operation – sometimes causing the device to fail.

This ‘false failure’ can lead to unnecessary yield loss on the production line requiring significant time and effort to diagnose because the extra power applied to the device may indicate incorrectly that the device is bad when it is not.

The goal of the test engineer is to reduce the cost to test a device. Therefore, they want their automatic test pattern generation (ATPG) tools to generate a lot of activity and test a lot of the chip. As a result, a lot of power is being consumed—typically exceeding the functional power budget between 7x to 10x.

This occurs because the chip is designed with a power budget in functional mode. “If you think about the design of a chip, most chips aren’t operating all parts of the chip at the same time and ATPG doesn’t look at functionality — it just looks at the structure and to minimize the cost or minimize the patterns it’s trying to make as much activity happen in the chip in order to get test all simultaneously,” explained Robert Ruiz, senior product marketing manager for test automation products at Synopsys.

In the past, ATPG tools really didn’t need to look at power consumption — the chips were small enough, the power rails were big enough, and there wasn’t a big prevalence of low-power designs. On top of that, there weren’t compression techniques being used, which further exacerbates the problem because the goal of a low-power design is to minimize switching activity, while the goal of compression is to maximize it. This is a very big deal for test engineers, but it is not an issue traditionally highlighted in the design community given designers’ focus on functionality—even though designers may take partial ownership about how to implement some of the design-for-test solutions.

Ruiz indicated that approximately three years ago the impact of power on test became a big area of Synopsys’ R&D effort based on feedback from a number of customers. At that time, he said, there were some customers who reported power issues related to test. They did some redesign, which resolved the issues at hand, but believed it could be a problem in the future. “It has certainly evolved to the point where most customers say they definitely have found a power issue during test,” Ruiz said.

Test is tricky for low-power designs
Greg Aldrich, director of marketing for the Silicon Test Systems group at Mentor Graphics Corp. said one of the problems in test is how to create test patterns that have lower power profiles in terms of what data gets shifted in, which is dramatically complicated by the use of on-chip compression and on-chip test structures. Previously, test was performed by shifting data into scan chains, issuing the clock cycle, shifting the data out, and then comparing it to the golden response data, whereby the scan chains were directly connected to the tester.

However, most designs today utilize either built-in self test (BIST) or on-chip/embedded compression, which is still a deterministic process. But instead of the tester directly shifting data into the scan chain, there is a decompressor that it goes through that sits on chip. The tester shifts data into the decompressor, which is expanded internally, essentially creating the data on-chip, Aldrich explained.

What complicates the process is that since the data is being created on chip a new on-chip piece of logic must also be created, so Mentor invented a new low-power decompressor that allows the designer to control the stuff on chip, he said. “It’s not as simple as just changing what’s on the tester. You actually have to change some of the embedded test logic on chip to be able to control that. I think that is going to be primarily how switching activity is going to be controlled during the test—by controlling how the test patterns are created and then how the test patterns are loaded.”

Similarly, Synopsys rolled out an ATPG approach that doesn’t require any hardware or DFT change (which no customer really wants to do), Ruiz said. The company’s TetraMAX tool was enhanced about three years ago to allow the user to dial in a budget of the switching activity, which serves as a proxy for power consumption. And, if a customer wants to be more aggressive and active in managing power consumption, there are other hardware techniques including Synopsys’ DFTMAX tool as it puts off the scan chain.

Likewise, Mentor’s Aldrich noted that in terms of innovations both on the design side as well as on the test side to help deal with the impact of power on test, “It’s all focused on how to reduce the switching activity during the test. Historically, a lot of that has been done by partitioning the test and that is still the case especially as you move to designs that have multiple voltage domains or multiple power islands. Being able to just sequence the tests for each one of those allows you to test a smaller piece of the design. That has some implications on the test time and cost that it takes to test the device but that’s one approach.”

Mentor has also added more control into its tools as to how much is switching during the test process. For example in its ATPG tools, users can specify constraints to the test pattern generation tool to indicates how much switching is allowed during the test pattern.

“The more aggressive they are in terms of lowering the amount of switching during the test process, the higher it is in terms of test costs. It’s going to take more test patterns, it’s going to take more compute time to create the test patterns but it is a knob they will have control over now. They really have no other choice other than designing the power structures in the design such that they can handle 50% switching activity—that’s the only other alternative,” Aldrich said.

In the end, the objective of test is to create the highest coverage in the smallest number of test patterns. What that means from the perspective of the design, it means you want to try and switch on everything possible in the design on every cycle on the tester—and that’s the opposite goal of low-power design. That said, a complete rethinking of compression algorithms and other test technology is in order.

Imec and Holst Centre unveiled an analog-signal processor ASIC that reduces the overall power consumption of a heart activity signal monitor by five times. Key to the process is intelligent processing from an adaptive sampling scheme—slashing the amount of data that needs to be processed by the DSP and then transmitted by the radio.

This is one of the hidden benefits of Synopsys’ announced acquisitions of CoWare and VaST. The more you can control the software, the more you can control the overall efficiency of the entire system—particularly when it comes to a multicore system. The key is adding intelligence into the processing up front, which is where software prototyping comes into play. The amount of data in circuit design is exploding, but not all of it has to be processed at every step.

Imec wasn’t the only one looking at low-power medical devices. MIT is developing a series of self-powered sensors that harvest electricity from temperature differences in the body. Who needs batteries?

Broadcom introduced a new low-power chip that combines Bluetooth with FM and a GPS, as well as all the normal stuff you’d find in a smart phone. Most of the services in smart phones have been software-based. This should change the market—and potentially the amount of power necessary to make it work.

On the utilities side, Springsoft introduced a power-aware debug solution for verifying low-power chips that supports both UPF and CPF. Spanning rival formats is always an opportunity, particularly when companies use tools from more than one EDA vendor.