What makes one smart phone last longer on a charge than another? The answer may surprise you. Low-Power Engineering talks with Cary Chin, director of technical marketing for low-power solutions at Synopsys, about what his months of research have shown.

By Ed Sperling
Scaling down the voltage to boost battery life and cut energy costs has always been considered the best option, but it’s getting more difficult at advanced nodes and in stacked die packages.

The key problems are noise and leakage. Lowering the voltage exacerbates both of them, forcing a rethinking of the whole design process starting at the architectural level and continuing to new tools that will be required for existing flows, new packaging approaches, new gate structures, potentially new materials, and some really thorny business tradeoffs. If this were a game of chess there would be multiple opponents, the board would be multidimensional, the chess pieces would conspire among themselves, the rules would change constantly, and those with the most powerful pieces at the end wouldn’t necessarily win.

These problems have been creeping in since about the 90nm process node from a process standpoint alone. Add to that more functionality on a single chip, with more power supplies, more voltage islands, thinner gate oxides and the possibility of lower signal-to-noise ratios and greater leakage and the game becomes more challenging. In short, this is a tough problem to solve—and it’s getting harder.

“You always want to have voltage as low as possible,” said Philippe Magarshack, group vice president at STMicroelectronics. “And we are getting better at understanding variability in the process. But there will be more than one voltage. It will be a different voltage for memory than for the rest of the transistors. What’s changing is that there is more playing around on the edge of the design to see what is the lowest voltage that can be used.”

He noted that by using fully depleted silicon on insulator at 20nm, and FinFETs at 14nm, there will be some gains as well as the need for fewer dopants in the channel. Stacking die also will add some benefits in reducing power drop, and there is more of an understanding of how to use power islands and dynamic voltage scaling for even mainstream designs. But knocking the voltage down is still challenging, and it will become even more challenging in the future.

Noise, IR drop and stacked die
Noise is one of the biggest problems that engineers encounter when lowering the voltage. There is simply less margin for managing signal-to-noise ratio.

“As you scale down, noise increases,” said Barry Pangrle, solutions architect for low power design and verification at Mentor Graphics. “But so does the tolerance for additional noise. One of the commonly used techniques has been clock gating, but that can change the characteristics of cu rrent on a grid and cause IR drop. What we’ve seen is that large variations in current are a source of noise.”

IR drop, in particular, is the bogeyman of low-power engineering. IR drop is equivalent to voltage drop and both result in power dissipation. And with the projected voltage at 14nm expected to be somewhere around 0.4 volts, The challenges of IR drop will force more designs closer to the noise margins.

Some of these dissipation effects will be minimized by the advent of FinFETs, which provide better control of gate leakage, and by new substrate materials such as silicon on insulator. But the other trend underway is also to stack die rather than just shrink all the features—particularly for analog portions of the chip. Both noise and IR drop can affect adjacent die, in part because they’re thinner, and in part because they’re connected by through-silicon vias.

“The noise on a signal can be propagated through different die,” said Qi Wang, technical marketing group director of solutions marketing Cadence. “We’re already starting to see a wide spectrum of voltages on chips. They don’t have to be on a single die to cause problems.”

Making tradeoffs
So what’s the solution? The answer has always included a combination of new materials—copper, low-k dielectrics, SOI, for example—and design advances such as finFETs and ultimately tunnel FETs that can be implemented for a reasonable cost. It also has included a conscious tradeoff between area, power and performance. In the past several years, however, with an emphasis on more mobility and better efficiency in data centers, energy efficiency has emerged as the No. 1 goal. Lowering the voltage has always been considered the fastest way to achieve that—despite the problems associated with it.

“At 700mV, power consumption can be reduced by half,” said Aveek Sarkar, vice president of support and product engineering at Apache Design. “But as we move from 28 to 22nm and beyond, the big worry is gate oxide thickness or the maximum supply voltage before the dielectric degrades. The other issue is that if you continue to drop the voltage, performance decreases. So you’ve got a tradeoff between performance, power and reliability.”

He noted that at 14nm, the technology itself will require a lower supply voltage. “The devices and the interconnects need lower voltage. You can’t have a 1.2 volt power supply with those dielectrics.”

Insulator thickness at advanced nodes is a huge consideration. With gate oxides as thin as 5 to 7 atomic layers, process variation that’s off by just one atomic layer can have a huge effect on transistor performance.

Several other approaches are in use or being considered to deal with these problems. One approach is to dynamically scale voltage, rather than keep it constant. This technique has been widely used already. A second, particularly in stacked die, is to use different power sources for different die, which can help alleviate some of the IR problem. Still another is to re-architect the entire power delivery network, which creates its own set of problems.

“In CPF 2.0 there is a special section for modeling of LDOs (low dropouts),” said Cadence’s Wang. “Initially we had one or two LDOs and you could design them by hand. Now there are 20 or 30 and they depend on each other. The output of one is the input for another. That’s a better way to control the power delivery.”

The result is that power can be cut off using multiple levels of control rather than just one. That, in turn, can be balanced with voltage reduction where it makes sense. But making these tradeoffs isn’t so easy.

What’s needed
At least part of the problem is in the tools needed to do this kind of work. There needs to be significant advancements the analysis capabilities at the very front end of the design process.

“To the extent that we can push voltage lower we will,” said Cary Chin, director of technical marketing for low-power solutions at Synopsys. “But the best way to deal with all of this is more statistical timing analysis versus our worst-case scenario planning. For voltage and margin you really need to look at statistical methods rather than the worst case. That can have a significant impact on efficiency, and a lot more has to be done there.”

At least part of the problem is also a better understanding of use cases. Efficiency varies greatly depending on the application, the temperature and the length of the duty cycle.

“There are a large number of variables that can change the most efficient operating voltage,” said Mentor’s Pangrle. “The server folks are looking at cloud implementations, but even there the workload can have a big impact. And in 3D, with a memory stack, the bandwidth between the process and the memory can chew up a lot of power.”

There is certainly a benefit on power in stacked die because of reduced parasitics, particularly in the interconnect. He noted that in some cases, running at a higher voltage may yield the same power savings as dropping the voltage and dealing with the resulting noise and IR drop. There’s also a hidden cost in dropping the voltage too far—manufacturing yield.

“The noise and reliability of a computation result in better yield of chips,” Pangrle noted. “If you decrease Vdd, there may be fewer chips that can run at that voltage level. If you have set 250mV as your threshold voltage, it will be leakier, so you will have to pay for additional performance.”

Conclusions
Dropping the voltage will always be seen as the most direct cause-and-effect way to improve efficiency in devices, and there have been big gains already in dropping the supply voltages for many components. I/O and memory, which used to run in the 3 to 5 volt range are now in the 1-plus volt range, and there is talk they will soon be in the sub-volt range. But there also will be limits to various components on an SoC or in a 3D stack, and they will require different voltages depending on such factors as data retention, performance and proximity effects.

EDA companies are well aware of these issues. They’re also aware that tools need to become much more sophisticated for dealing with analysis surrounding dropping the voltage, what impact that will have on performance at a system level, and developing rapid what-if types of scenarios. And they recognize that it will have to be done at a higher level of abstraction, or sequentially in discrete steps that are reflected in other steps, because the amount of data that must be analyzed is growing out of control.

There is no consensus, however, on how best to deal with this. Cadence, for example, is breaking the problem down into smaller chunks. “The problem size is double or triple,” said Cadence’s Wang. “You have to deal with it locally. It’s a divide and conquer solution.”

Apache, meanwhile, is looking at analyzing everything from chip to package to system. “You really need to do dynamic voltage analysis to get the actual picture.” Sarkar said, noting that may include more decoupling capacitance (decaps), more efficient decaps or the effects of the interposer.

So far there is no consensus other than the fact that all tools are welcome and the problem is monumental. But at least there is a recognition that something has to be done.

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By Ann Steffora Mutschler
In the quest to optimize an SoC for both power and energy efficiency many variables come into play. Target application, use cases, processor choice and amount of memory among other specifications all figure into the optimization equation.

As discussed in Part 1 of this series, energy and power are different entities and must be understood distinctly from each other. After that point engineering teams can then begin to apply design techniques to optimize one or the other in a system.

In terms of optimizing either power or energy efficiency for a specification application, if there is a function that takes a certain amount of time to execute it could be implemented in many different ways, according to Cary Chin, director of technical marketing for Synopsys’ low power solutions. “If you were to draw the power curve over time, you might see a constant level of power used and draw out a rectangle. Essentially the energy used is the area under that rectangle which is easy to compute. An alternative implementation of that might actually turn out to be a vertically standing rectangle, which takes much less time to execute but consumes much more power.”

However, a more detailed calculation is needed to compare the area under those curves, so it’s actually quite different, Chin noted. “When you break it down, it depends a lot on things like the energy overhead of certain functions and keeping things on. Leakage plays an important part because that’s what makes the difference between the real work that’s been done—what we associate with dynamic power (switching transistors). In that case, the horizontal rectangle might just be a slice off the top because there is a lot of overhead. And if there is a lot of overhead the vertical rectangle might actually be significantly more energy-efficient. So even though it consumes more power, it will consume it for less time.”

The overhead also figures into how much energy is actually being put to use in computing the function. “When you multiply that by the level of complexity in today’s chips it really brings out how complicated of a computation these days to even try and estimate,” he added.

That’s just from the hardware design perspective.

On the other side of the table, Mark Mitchell, director of embedded tools at Mentor Graphics argues that in many cases the software might actually be more significant than the hardware. “When you are designing a device, to have some idea of what you want it to be capable of, even some requirement on how much memory—it has to be able to process this many inputs and outputs per second—and from that you can pretty quickly say you’re going to new processor that runs 1 GHz with these capabilities on it. At that point, when you look at what your competing choices are, there’s not too much power variation at that level. A lot of the variation I believe is from really different classes of devices.”

Relating the type of processor to automobiles, Mitchell said once you decide that you are looking for a high-performance sports car or a four-door sedan or pickup truck, you get a pretty good sense of what the instantaneous power on the device is going to be. “But if you want to control the actual energy usage of the device, which is how long the battery is going to last, a tremendous amount of that is at the software level and very different from application to application or design to design.”

The operating system, for example, will shut down a peripheral when it’s not in use. But shutting that peripheral down has an associated cost for bringing that peripheral back up.

“How often do you want to wait for it to be unused before you shut it down,” he asked. “The longer you wait then the more you’ll be using it and just wasting energy there but if you can’t predict when it’s going to be needed again then it actually might be the right decision. Whereas if you know this device is used really infrequently and as soon as you stop using it you turn it off, that might be a big savings. Those policy decisions are really specific to the device that you are building.”

Still, the conventional wisdom is that high performance leads to high power, and that doesn’t necessarily lead to higher energy, said Pete Hardee, director of solutions marketing at Cadence. “If I’m worried about power then I’m likely to reduce the clock frequency to minimize the power and take as long as I can to do the processing—take as long as I have available. That will get the processing done at the minimum power but the energy is basically the same. It’s the same amount of processing, which is taking longer, but the energy is going to be similar when you just look at the dynamic power and clock reduction as a technique to deal with that.”

There’s a new variable in all of this, too: leakage. The best way to manage leakage is to turn circuitry off. Approaching the situation in this way opens up the opportunity to possibly minimizing power and energy by computing as fast as possible, then shutting off a part of the circuitry for a longer period of time.

“This is an example of why it has to be managed by both software and hardware,” Hardee noted. “Whether or not you can do that, whether or not the right choice is to spread out the computing, take all the time available and do that at a lower instantaneous power or get it done quickly and shut everything off, is very application-dependent. I’m going to make different decisions on that based on various system criteria around the application.”

He explained that it depends on how regular the application is versus bursty. “If I’m rendering Web pages, that tends to be a very bursty activity. I want to see that Web page in all its glory with its great graphics as quickly as possible and I might not see another one for a few seconds. Processing video is very different. It’s a more regular thing. There’s a frame rate I have to deal with. For one I might decide to render the graphics as quickly as possible and then shut down. With the other one I might need to keep the system alive, process the video, and take as much as of the frame rate as I need to process the video. I can’t shut down because I know I’ve got 25 frames per second and I don’t have time to shut down.”

Industry-wide challenge
Put in the context of system developers, just how big are these issues?

“One concrete measure is that a fair number of the silicon companies that we are dealing with now have more software engineers on staff than they do hardware engineers. It’s not that they have a lot of really expensive, good hardware engineers in a high-cost area and then they have this vast army of low-cost software engineers offshore someplace. No, they actually have high-cost, very highly capable software engineers on staff as well because the software problems are getting to be so significant,” Mentor’s Mitchell pointed out.

And it gets worse. “As we hit the Moore’s Law scaling limits and various physical limits, we go into more complex hardware architectures that are complex on one axis but simple on another. Instead of making a faster and faster processor, we are saying, ‘Here, have two cores or eight cores or 128 cores.’ In a way that’s very complex from the hardware point of view. You have a lot of transistors hanging around but in a way it’s also kind of simplistic,” he said. “You’re saying, ‘I don’t know what to do next as a hardware engineer, so here, have a lot of cores. Software guy, it’s your problem go figure it out.’ Unfortunately, taking advantage of that efficiently in software is really complex and it’s not just around cores.”

He offered another example: programmable I/O units. Instead of building an Ethernet unit onto an SoC an engineer may build a little I/O piece and it can be an Ethernet port or it can be some other kind of I/O port. It just needs software to control it. “We keep introducing places where what used to be done in hardware now has to be done in software, and that increases the complexity and gives us a lot more opportunities. It’s more flexible but also more chances to screw things up.”

By Ed Sperling
So far most of the energy savings in SoCs have been achieved using two main approaches—turning off most of the chip most of the time, and changing the materials used to insulate against current leakage.

Over the next few years, changes to designs will be more radical, encompass more pieces of a bigger system, and they will be orders of magnitude more effective. From a market standpoint, there is little choice. Computing increasingly is going mobile, and time between charges is a competitive edge. The caveat is that increased battery life has to come with a subsequent increase in functionality. Everything that could be done with a plug now will have to be done without one.

That means rethinking everything from the hardware design to the usage model to the software that runs on those platforms. And it means getting chips out the door at least as quickly, if not more quickly. Here are five trends and approaches that collectively, and sometimes individually, will have a big impact on energy efficiency, power consumption and leakage:

1. Rethinking the basics. Some of the biggest advances in efficiency will come from optimizing existing technology. There is more to turn off, more pieces to improve, and there are more ways of doing it better.

Consider something as basic as the clock, for example. The big focus has been maximizing frequency for nearly five decades. There are even concurrent clocks to make that happen. But having them always on and always running at the same frequency means they use a lot more energy than necessary.

“Design has always centered around the clock being the heartbeat of the system,” said Chi-Ping Su, senior vice president of R&D for Cadence’s Silicon Realization Group. “So people always assume the clock will be on. What we have found, working with ARM and the processor type of design, is that the clock consumes an extremely large percentage of the power. Timing and frequency are based on the clock. So you build a tree to be the ideal clock and you do everything based on that. When we started looking at it, we started asking why clocks need to be balanced at all.”

So how much energy can be saved? Su contends the amount is up to 30% of clock-tree power and up to 50% of dynamic power for the entire system.

He’s not alone in touting these kinds of numbers. Most SoC tools developers believe that dealing with energy/power/leakage at or before RTL can mean significant savings for the overall design.
“All the low-hanging fruit is still available to chip designers,” said Vic Kulkarni, senior vice president and general manager at Apache Design. “We find that even advanced designers are more concerned with meeting functionality and identifying power bugs. What they forget is the relationship between data, clock, reset and enable—the four signals in an SoC.”

2. Reducing distance and resistance. Over the next two years the SoC industry will undergo a radical shift that will continue for years to come. Rather than plotting Moore’s Law linearly, transistors will be placed in three dimensions.

Driven partly by re-use, partly by time-to-market pressures and partly by physical limitations, 2.5D and 3D stacking will have an enormous effect on energy consumption and power. By stacking memory and other components on top of logic, the distance a signal must travel can be shortened significantly, along with the energy necessary to drive that signal.

“Moore’s Law is not a law,” said Wally Rhines, chairman and CEO of Mentor Graphics. “But the easiest way to reduce the cost of a transistor for the last 40 years has been shrinking feature sizes and growing wafer sizes. We are coming into an era where it will be more cost effective to stack die than to shrink feature sizes. We will hit it with memory before logic, but as with all new technologies we will adopt it before it is cost effective because of unique capabilities.”

Whether it’s done with an interposer, package-on-package, or flip-chip bumped die, Rhines said there is a 70% decrease in power dissipation if the memory can be put on top of a processor.

And that’s just for starters. By adding more processors that are sized for a particular function and tying that to just the right amount of memory, rather than a whole memory chip or block, far less power is needed. Companies such as Tensilica and ARM have been making this case for some time. With stacked die, their arguments are likely to receive far more attention.

3. New materials and structures. Calling a material “new” is something of a misnomer in SoC design. Most of the techniques that we consider revolutionary have been around for decades, but they haven’t been developed enough to the point where they are cost effective, both from a yield and materials standpoint.

Through-silicon VIAs, for example, have been talked about since the late 1950s, and interposers in 2.5D packages are simply a collection of TSVs on a single die. But there are still issues to be worked out. Shang-Yi Chiang, senior vice president of R&D at TSMC, said there questions remain about how to integrate a substrate with an interposer, and how to debug it at different phases of development so it can be tested.

“There are a lot of parasitics to deal with in 2.5D,” Chiang said. “And with 3D we need time to make sure we can calibrate it.”

The other kind of 3D—structures such as FinFETs, tunnel FETs and nanowires—have been on the drawing board since the 1990s. All of these structures can lower leakage by controlling the gate at multiple points. FinFETs are planned in volume for 14nm by both GlobalFoundries and TSMC, while Intel may begin using them as early as 22nm.

These structures hold the promise of radically reducing leakage of both static and dynamic power using all modes of operation—at least initially.

“The problem is these are a one-off thing,” said Mike Muller, chief technology officer at ARM. “FinFETs do reduce leakage, but once you’ve done that you’ve still got three impossible things to do before breakfast. Those kinds of steps are part of the solution.”

Muller said combining those with stacking techniques will go even further. “It opens the door to completely different die-to-die memory interfaces which allow you to build more efficient systems than when you go off the chip, down the serial interface to a separately packaged die. It changes the memory bandwidth, and this is just a computer at the end of the day so memory is one of the fundamentals for performance. Stacking allows you to change that.

4. Lowering the voltage. One of the benefits of 3D structures such as FinFETs and stacking of die is that they make it easier to lower the voltage in certain parts of the chip. The reason is that the minimum voltage for DRAM may be higher just to maintain functionality than it is for logic or I/O. By separating those functions into different die, issues such as state retention and leakage can be confined and dealt with independently—the so-called divide-and-conquer approach.

So how low can the voltage go? Several years ago, researchers at IBM said the minimum voltage for an SoC would be at least 0.7 volts. It now appears it can be as low as 0.1 or 0.2 volts, and research is under way to lower it even further.

“You can get down to 0.3 or 0.2 volts without any problems,” Qi Wang, technical marketing group director at Cadence, said during a recent roundtable. “If you keep the aspect ratio of the depth and the height of a FinFET then you can guarantee the performance, but you do have other physical effects. Nothing is free. But the voltage can go much lower than what the textbooks say.”

5. Fixing software. Software is the last piece of the puzzle to fix, and it’s been one of the hardest for a number of reasons.

First of all, software takes longer to create and perfect than hardware. This is evident in all the bug fixes and updates. All three of the top EDA players are involved in this effort. Synopsys is working on software prototyping to get allow software to be written even before the hardware is ready. Mentor has been involved in simplifying the creation of RTOSes and embedded software. And Cadence has shifted its design approach so that software and hardware can be done far more concurrently.

But getting software out on time is only a first step. The next step is to make software function more efficiently, an approach that dates back to the RISC vs. CISC wars of the 1990s. Reduced instruction set computing was more efficient than complex instruction set computing, which boosted performance. By taking that approach one step further, it also can reduce the amount of energy consumed by a particular task, and be used to manage the overall power in an system much more efficiently.

Work on symmetric multiprocessing continues, as well. How far that will go is anyone’s guess, but for most applications we now seem to be facing a limit on the number of cores that can be effectively used by most applications. Talk about unlimited number of cores has given way to limited numbers of cores and unlimited numbers of processors spread throughout a system—most of which are off most of the time.

Taken together, all five of these trends will have a huge effect on efficiency, power and leakage. And now that battery life is a competitive issue, it also is likely to be used by vendors and seen as a value add instead of an unnecessary engineering cost—or worse, a nuisance.

By Ed Sperling
Low-Power Engineering sat down to discuss the increasing challenges of designing for mobile devices with Qi Wang, technical marketing group director at Cadence; Cary Chin, director of technical marketing for low-power solutions at Synopsys; Bernard Murphy, CTO of Atrenta; and Dave Reed, senior director of marketing at SpringSoft. What follows are excerpts of that conversation.

LPE: How real is wide I/O?
Wang: If you have unlimited resources and no restriction on packaging costs, even on the chip you can have wide I/O. You always want I/O as wide as possible. With 2.5D and 3D that will be the driving force. All the IDMs will keep developing the fancy stuff like FinFETs. Traditionally you go through the gate using source and drain, and the reason you have so much leakage is that your gate is so far from silicon that you control the other side. If you turn it around and put controls on the top and bottom of the silicon, the leakage is almost zero.
Reed: Other things that mobile drives is super-integration. Almost every chip we see has analog on the same chip as digital. That’s a noisy environment. You have to raise the voltages. But now you’re on a more advanced process than in the past, and some functions are moving into digital that used to be in analog. It’s done for power and availability. That’s a new architectural tradeoff that people have to make. Do they move it to digital or leave it in analog? Plus, people need automation there.
Murphy: Is the same thing happening with RF?
Reed: RF is coming onto the chip as well, but there are not the same tradeoffs as there are with other analog portions.
Murphy: I remember discussions about mono-chips where the whole smart phone including RF is on the same SoC.
Reed: I remember those discusssions, too. We had to give up gallium arsenide for a long time for RF.
Wang: One side of mobile is cost and low power. The other side is the signal. Anything that communicates with the outside world is analog. So every SoC is a mixed-signal chip by definition. We saw the same trend of moving things to digital. One reason is power. The other is when they define IP, they want to make it more configurable. They want to program those analog features. But analog is hard to migrate to the next node. If you move to digital it’s easier to migrate. So if you combine mixed signal and low power, that’s one of the big shifts in the market.

LPE: Do the tools exist for that?
Reed: I haven’t seen many. Are there any at the architectural level?
Wang: No. Right now we do it with a service team. It’s all manual.
Murphy: We’re seeing a lot more errors coming up around the mixed signal integration, too. And they’re subtle errors. When you put mixed signal together with power management you have things like level shifters and you find things aren’t quite characterized where you expected them to be or in the range you characterized them in. Something switches and the other side doesn’t switch. That’s a big challenge.
Chin: That whole verification area is tough. You can view the low power verification world today as a move in the direction of mixed-signal verification.
Wang: It originated from our old technology. We repositioned ourselves. Our previous methodology to speed up the design flow was analog and digital. The analog dealt with analog and the digital dealt with digital. Analog is a black box. You don’t even ask what is inside. The other side is the same. But that has to be changed. As ICs become more complicated, you can’t treat them as a black box anymore. It all has to be modeled and verified. The other side of this is that to move from analog to digital you have to do co-design. We are nowhere close to mature on that, but analog and digital engineers are working together because low power has to be considered as a whole.

LPE: But most of the engineers working in these fields live in silos. What’s going to change that?
Wang: On one side, the EDA vendors have to educate them in this methodology. There are a handful of very advanced companies in the world, but they don’t share their knowledge. To move the whole industry forward the EDA companies need to step forward. But we are starting to see more solutions architects to drive low power and mixed signal. I just came back from Taiwan and was promoting mixed signal models. The customer said they didn’t think that was a problem at the early stage. They would test a chip, find out what works, and go back and design another one. The customer acknowledged they will need to change in three to five years, but things will slowly happen.
Murphy: It’s not just Taiwanese companies. U.S. wireless companies accept they will have to do multiple spins because they cannot fix the mixed signal problems on the very first silicon. They’re going to put in enough redundancy to test it, and then they’ll fix it in the next one.
Chin: That’s really the testament to the need for tools in this space. When the customers are saying it’s going to fail, something is needed.

LPE: Let’s go back to the tradeoffs between Wide I/O and smaller I/Os. Do companies really understand this?
Chin: It’s the same problem we’ve been seeing on chip for a long time. It’s also related to this idea of dynamic power. What we’ve done for 20 years is optimize logic for performance, which means we care about the critical path. The way we optimize the critical path through synthesis is by trading off slack on other paths. You get a wave of transitions running through the chip. It’s an interesting tradeoff, because from the standpoint of power there’s nothing worse you can do. When you think about it from the standpoint of energy efficiency for computing a function, you have logic computing that function with a minimum of transitions and that’s it. Through this process of optimization we’ve folded everything onto itself. It’s re-use and resource sharing at a high level, but if we’re not reclaiming energy then design methodologies will have to change completely. Some smart EDA person will invent a new tool that allows you to push forward with this old idea of not folding your logic or sharing pieces so you can achieve the lowest possible power. That’s exactly where these tradeoffs happen. 3D IC is one example for the packaging level. Within the chip, within the synthesis domain, the system-level domain, the whole idea of architectural assembly of IP and blocks, this plays itself out many ways. It’s an important concept with regard to dynamic power. It’s fundamental. It’s the multiplexor problem.
Reed: If you look at the way the CPU guys have gone, they’re already down that path. They’ve stopped frequency scaling. You have separate cores. You can shut these things down or run them slower. They’re using the silicon to buy better power.
Chin: But you have more stuff sitting there that’s inactive.
Wang: If you look back 30 years, the most expensive thing was silicon area. At that time you had to do resource sharing. You went from parallel to serial. Now we are taking mixed signal to parallel.
Chin: And massively parallel is just one function computed optimally for everything that comes out of a chip. Maybe you expand that to 3D IC where each one of those has it’s own I/O. It’s interesting to think about how the methodologies and flows will have to change as we move in that direction.
Murphy: Architecturally, people are doing that on SoCs. Instead of one big DSP or CPU, they’re moving more and more of this stuff apart. There are multiple CPUs. The bus structure is split into many levels of hierarchy so you can shut big chunks of it down.

LPE: How low can we drop the voltage? Is it just 0.7 volts or 0.8 volts?
Wang: It can go much lower than that.
Murphy: I’ve heard 0.1 volts.
Wang: It also depends on the size we go to. You can get down to 0.3 or 0.2 volts without any problems. If you keep the aspect ratio of the depth and the height of a FinFET then you can guarantee the performance, but you do have other physical effects. Nothing is free. But the voltage can go much lower than what the textbooks say.
Reed: The rate of voltage scaling has been slowing. Leakage was the consideration that has been slowing the rate of scaling, though.
Wang: Absolutely, because if you look at a traditional 2D device it’s harder to control the channel so the leakage is a problem. But we can continue dropping it for a long time to come.

By Ed Sperling
Low-Power Engineering sat down to discuss the increasing challenges of designing for mobile devices with Qi Wang, technical marketing group director at Cadence; Cary Chin, director of technical marketing for low-power solutions at Synopsys; Bernard Murphy, CTO of Atrenta; and Dave Reed, senior director of marketing at SpringSoft. What follows are excerpts of that conversation.

LPE: What effect does the wireless spectrum have on design?
Murphy: Spectrum availability is getting squeezed. That’s why things like MIMO (multiple input multiple output communications) are becoming interesting. But to support MIMO you need multiple radios or complex radios, and radios suck power. You have to deal with that problem to take advantage of whatever spectrum is left.
Chin: I’ve been doing a lot of experiments with power lately, and it turns out that the screen is not always the biggest power hog in the system. In general it is, but if you’re in an area with poor communications signals the radio draws a lot more power than the screen. This is why some people with the first iPhones were surprised that they were getting 1.5 hours of battery life. With multiple radios in a device today, it’s a big deal. My phone gets much hotter when I’m streaming something while driving around in my car with the screen off than if I’m at home in a WiFi environment. We’ve been working on cutting a number of cords in mobile. The power cord is the most recent. But the one we cut previous to that was Ethernet. It turns out that was a big deal. There are new standards. Bluetooth was notorious for being a power hog. The new Bluetooth standard improves that. But power is really a global issue. When I worked in synthesis, we thought a lot about divide and conquer. But the ramification of power is global. A picowatt in one quarter of the chip affects the whole chip. That’s one thing we need to think differently about. It’s not just physically adjacent blocks or logically connected blocks.

LPE: But some of these effects are also outside the chip, like multiple towers handling a signal instead of just one. How you deal with that in the design? There are lots of disconnected pieces that aren’t even part of the SoC ecosystem.
Murphy: There is a lot of architectural power modeling. They’ll look at the SIM card and the battery and what’s around. Then you have to start thinking about where your transmission sources are, and as you move around between these things how much power are you using as you move around.
Chin: More and more we need to talk about this holistic approach for low-power design. You really need to think about everything in a global sense. It’s a difficult problem, and the solutions are moving toward more standardization and more IP. If we can take communications standards and have reasonably re-usable chunks, that will simplify things. But then having all of those things work together and making sure the low-power methodologies are consistent is not simple. We’re not going to run out of things to do.
Murphy: A lot of design teams thought they could handle power in the same way they handle test. The problem now is there is a much stronger coupling between power management and the design, so you can’t finish the design and then do the power management. They’re too interrelated. But you still need a high level of expertise to do the power management.
Chin: Power goes even above the chip-design process. It might even be something you need to think about before you think about the rest of your chip. And chip designers are pretty uncomfortable with that.
Wang: Most of our leading customers in the mobile market have come to the conclusion that they cannot address this from the same point of view. They have to combine software engineers, hardware engineers and system engineers all the way to the signoff. They need to work holistically doing modeling, estimation, create a spec, and at every stage check for the spec. We’re seeing more and more real customers adopting that approach. What’s ironic here is that EDA companies often get blamed for being behind, but in this case the EDA companies are ahead. They want to know why their power came up at 11 (volts) when then put down 5 (volts).
Reed: EDA is always a little bit behind the leading edge and ahead of everyone else. The people who have had to deal with power seriously for awhile have been doing just that. We’ve learned from them. But before test could be thought of separately it was part of everything else. It was great when you didn’t have to include test. It was liberating because you went from a small handful of people designing 7,000-transistor chips to tens of thousands of people designing millions of transistors. I have no doubt power will come to that stage.
Chin: I’m not so sure of that. I used to work in test and we created a methodology to make that separate. But in the case of power, it’s so closely intertwined that I can see the opposite happening. It may be power that’s most important, and whatever performance comes out is what we get. Design for power may become the biggest design parameter and everything else may fall beneath that.
Reed: Power debug has become a new thing you have to worry about, whether you’re using UPF or CPF.
Wang: Power has become an inseparable part from concept to silicon. Power is a requirement. It is not a technology or technique. If people want more functionality, it all boils down to energy needed to do the computation. In some ways, people have invented the problem. One CEO came to Cadence to talk about moving from desktops to mobile. He is trying to find a new market for his processors, so he is looking at medical and gaming. But what’s interesting is they’re not building games. They’re building simulators for physical effects. We need to worry about demand for bandwidth and power. And performance does not just mean speed. Bandwidth is part of the performance. Response time of downloading and communicating can be a bottleneck.
Murphy: And it still has to be within the cost envelope. Power has probably gone slightly beyond performance in importance, but it hasn’t gone beyond cost. Consumers are forever going to be cheap. If I could buy something last year for $200, it should be $50 next year.
Chin: But the iPhone is a $600 device that costs $200, so we’ve figured out different ways of paying for that to amortize the cost over time.
Wang: Cost is a constant, but that doesn’t solve the problem. The success of Apple is not just the device. They create a value chain so they don’t just try to extract the value from the hardware device. There’s too much competition for that. Another angle we need to consider is that it’s not just about consumer mobile devices. A much larger market for mobile applies to medical. In a hospital you will have thousands of sensors in one room. If you multiply that by the number of sensors you will have in your body, it’s a very large number. People want entertainment and they want to live longer. You don’t need a different methodology to low power and low cost. The application-driven business model will be the underlying baseline.

SLD: What changes if power becomes the starting point?
Murphy: FinFETs will have an effect. Intel thinks they’ve solved the leakage problem.
Wang: That creates a new problem, though, gate sizing. Previously you could increase the channel width to make the cell bigger. Now you have to make it higher.
Chin: As power becomes the most important factor for design, the design methodology and tools will change. You can envision that over the tools we use will be very different. Over the past 30 years we’ve defined a methodology that gives us the highest-performance devices for the lowest cost and the smallest area. But we’re optimizing for performance. If that changes, there’s a lot of room for new methodologies, new tools and new ways of designing. If you look at simulation tools, we’ve been doing logic simulation for at least 30 years. It won’t be long before someone introduces a simulator that simulates power as well as logic. Today we have lots of approximations that help to solve the problems we have today, but we go back to device-level simulation to figure out what’s really going on with power. With UPF and CPF, that’s a temporary thing. In five years design intent and power intent will be the same thing. I believe these things are going to change radically.
Murphy: But everything we worry about in mobile power is predicated on the fact that you are removed for a long period of time from charging sources. If energy scavenging becomes really effective the problem goes away.
Reed: In terms of things affecting designers, there are a number of them. One thing people have had to care a lot about lately is leakage. It’s been an ongoing challenge—whether it’s subthreshold leakage, so we turn these off harder, or the dynamic power. For 3D (stacking) we can reduce the power several ways if we shorten the connection. You also can widen the I/O and add more memory and memory channels.

By Ed Sperling
As complexity grows in SoCs, so does the ability to accurately test them. That helps explain why there are so many different types of tests and so much confusion about what to use to perform those tests, when to test, and where in the flows to include those tests. But what’s less well known is that tests done improperly also can give false results, labeling good chips as bad—or in some cases actually killing a good chip.

Some of the problems occur when testing involves SoCs with multiple power islands and voltage rails. The primary reason in many cases is a bad test design. Use cases for smart phone chips, for example—the so-called worst-case scenarios—have multiple power islands turned on at the same time. In a testing scenario, including built-in self test (BiST), all of those islands may go on at the same time if they’re not carefully scheduled.

“You can burn a chip with a bad schedule,” said Yervant Zorian, chief architect at Synopsys. “There are two different modes of operation. In one, the CPU is doing it’s own work. Then, you have a memory scan or BiST when it’s idle. Throughout the life of the chip, 90% of the time it will do a normal function and there will be no problems. But during test mode the activity is creating excitement in the chip.”

That excitement is sometimes maximum power, and there are limits for the amount of power that a chip can handle. The best way to avoid this problem is to test in sequence so that all power islands are not on at the same time, but this requires up-front planning. Test frequently is an afterthought in many designs. In addition, while testing is good, over testing can be very bad.

“There are two levels of failure from test,” said Giri Podichetty, technical marketing engineer at Mentor Graphics. “One is at the soft level. The second is in the power supply. You can get a false failure even if the chip is okay. But you also can get a catastrophic failure if there is too much heat or current.”

The flip side of this is that testing itself is ineffective, allowing bad chips to reach the market. One of the unique challenges at advanced process nodes is the amount of power needed is not scaling at the same rate as the transistors in the design. That can greatly impact test, said Podichetty, because small voltage swings with high leakage can cause significant problems.

“Power integrity can be localized, but it may not be what you expected,” he said. “You also may have the chip running slower and it may be hotter.”

Mix and match
Another challenge is the so-called mix and match approach of chipmakers. Tools and IP are bought from multiple vendors, with some of that IP developed on different process nodes. In addition, not all methodologies are up-to-date because chipmakers will frequently push older tools and methodologies.

With soft IP, much of this can be factored into synthesis. But with hard IP, testing requires a real understanding of the IP and how it will be used.

“Some designs can be tested in their entirety, but others need to use a partitioned test approach,” said Robert Ruiz, senior product marketing manager for test automation products at Synopsys. “You need to attack the problem with different methods. ATPG (automatic test pattern generation) can model faults. You may need to do dynamic bridges that exist for a moment vs. a static bridge. But the challenge for test engineers is to establish the operating parameters of frequency and voltage range. Basically what you’re doing is creating shmoo plots, where frequency is one axis and voltage is on the other. Then you try to push the devices to the corners and determine what’s in the spec and what’s not in the spec.”

Engineers also need to make sure the test program is more sensitive to the power budget than in the past, he said. If the budget is set too low, there’s a danger of under testing.

“Low power is not the best way to handle testing,” he said. “Power-aware is the right approach. Low power actually minimizes the power, so you end up under-testing.”

Conclusions
While test can go a long way toward making chips more reliable, done wrong test also can damage chips or provide false results. In a single die, that can be expensive. In a stacked die, it can be multiple times more expensive.

It’s important to note that each chip is different, each organization doing the testing is different, and the number of combinations of what to test, where to test and what to use is increasing. That’s why there is so much activity in test these days, with all three of the big EDA vendors and many of the smaller ones working to secure a stronger position in this area. Where there is pain there frequently is opportunity, and there appear to be plenty of both in this area.

By Ann Steffora Mutschler
The terms power and energy are used almost interchangeably these days, but understanding and clearly articulating how to optimize embedded designs for maximum energy and power efficiency can make a big difference in a design.

At a physics level, energy = power x time, whereas power is the rate of energy in a given time window. When the focus is specifically power, it is the rate at which energy is released—so much per second. Typically that is associated with things like supplying current into a chip and pulling heat out of a chip.

“You may not be able to instantaneously or over a short period of time be able to sustain more than a certain amount of power dissipation,” said Chris Rowen, CTO of Tensilica. “It’s related most often to the thermal envelope within which you are operating.”

Energy, on the other hand, is the total consumed over the course of some job. Most importantly here, he reminded, batteries don’t store power, batteries store energy. There is a finite supply of energy in a battery and often in mobile devices, and the first consideration is with energy. For example, you want someone to be able to get their job done, which might be to go all day with their phone with the amount of charge that they have in their battery. You may not care quite so much about exactly what rate that energy is used up, but you do care about completing the task at hand.

The difference between energy and power is obvious when there may be two approaches to doing some kind of computation. Power may be dissipated at a high rate, the work performed very quickly and then shut down. Alternatively, that computation may be stretched out over a longer period of time, dissipating less power at any instant, but consuming energy over a longer period.

“You have to actually look at the product of the two or the area under the curve and say how much power times how much time, that’s what gave me energy. This shows up particularly when people are looking at the interaction of hardware and software because software has a lot of control over algorithms. The algorithms often will determine how much energy is required to get something done,” Rowen explained.

If the engineering team has a good understanding of what the power dissipation is, with one set of instructions that might be executed versus another, they might able to determine that for a particular processor in a specific circumstance they are better off dissipating more power by running an algorithm that takes less time and consumes less energy. Or they may determine for a different algorithm that they are best off choosing the lowest energy instructions even though it may take a lot more instructions to get the job done but may result in less total energy.

“There are a wide range of non-obvious tradeoffs that people might make to look at the interaction between what algorithms, what software they might run and what the characteristics of hardware are. In some cases the hardware, which has higher power dissipation has lower energy,” Rowen added.

When it comes to battery life in mobile devices, energy efficiency is on the top of everyone’s list.

“Ultimately we want to do the most operations per electron that shoots through the power grid and that’s what is really going to give us longer run times for standby, active, whatever it is,” observed Cary Chin, director of technical marketing for Synopsys’ low power solutions. “Power efficiency is important, as well, because in an environment where if you assume that energy usage or power is relatively constant, then power and energy are kind of equivalent. It’s a technicality, but when you look at complex devices the level of power is certainly not constant. It starts to change a lot. This is the time about which we should really start to make the distinction because the assumption of constant power is no longer true in these devices. And as we go forward the assumption that when my phone is on, it’s just on, is no longer going to be true. In fact, it will never be all on, there will always be pieces that are off.”

That concept of on and off being relative is an important element in design. Another consideration is how much energy a design uses to get a particular task done.

“Customers think a lot about how much power the design is using and they are thinking about instantaneous power consumption,” said Jon McDonald, technical marketing engineer in Mentor Graphics’ design creation synthesis group. “But to really look at what they are trying to do, they are not trying to optimize the power generally. They really are trying to optimize the energy the system is consuming to get the job done.”

In talking with an engineering team recently, McDonald learned they have good estimates for how much power the system uses in any given state but they don’t have a good idea of how much energy is used by that system as it is processing the work that it needs to do because they don’t know how long it stays in any given state. For example, he said that when a system is processing data, if there is a lot of contention on the bus and the system ends up staying in a given state for 20% or 30% longer because it’s waiting for resources, all of a sudden it is using 20% or 30% more energy. The power it used didn’t change. The power in that state is still the same. But the power in that state doesn’t mean anything until you know how long it’s been in that state.

“You need a good understanding of not just the power that the system is consuming but the timing, the performance of the system, how long it takes in any given state to do the job that it’s trying to do,” McDonald said.

Coming next month: Optimizing for power and energy efficiency and the differences between them.