By Ann Steffora Mutschler
The increasing amount of mixed-signal content being included in SoCs for automotive, networking and all manner of mobile devices is reinvigorating the mixed-signal industry. While this is great news for companies playing in anything related to mixed-signal technology, it also means increasing complexity for the engineering teams pulling all the pieces together.

“People have been designing mixed-signal for a long time and the composition of mixed-signal is changing drastically,” explained Mladen Nizic, engineering director at Cadence Design Systems. “Traditionally, mixed-signal was viewed as big digital with some analog in there, but now we see that mixed-signal has really expanded in complexity. So we have designs today that are about equal mixed with respect to analog and digital content. With designs that in the past were predominantly digital, engineers didn’t need to worry about analog impacts and effects. Now they have to, at least to some extent. Digital designers doing verification need to have some representation for these analog parts or mixed-signal parts or they might not completely verify their designs.”

Given that consumers are the driving force behind semiconductor demand today, there are very high performance and cost demands. In fact, cost is now viewed as a primary design variable, according to Navraj Nandra, senior director of marketing for DesignWare analog and mixed signal IP at Synopsys.

Packaging—a significant portion of system cost—plays a deterministic role in the architecture of SoCs because the choice of package dictates a number of technological aspects of the system.

“Our customers are selling package-tested parts, so packaging becomes an important part of the cost equation. Customers would like to use the cheapest possible package that they can get away with, and the design challenge is that the cheapest package has the worst performance in terms of parasitics. You’ve got really bad parasitic inductance, parasitic capacitance, lead frames are very badly put together, and there’s a lot of leakage through the substrates. These things are typically in some kind of cheap BGA or wirebond implementation,” he explained.

To illustrate, Nandra shared a recent situation with a customer that wanted very high performance capabilities on the die but were going to put it into a really cheap package because it was going into a low-end smartphone they wanted to sell under $200. “The discussion was around how to get a very-high-speed memory to connect to the chip being developed without compromising signal integrity. In that particular package configuration that they had, there would be a limitation on speed. At a certain speed they’re going to get skew and reflections on the line, which is going to impact performance of the chip. Then the customer asked if they could save cost by compromising on the board—maybe use a two-layer board instead of a four-layer board. That’s certainly possible but, again, you have to downgrade or degrade the performance because the two-layer board doesn’t have that many degrees of freedom in terms of performance. So cost is absolutely a critical part of the equation when you’re coming into designing not only IP but also when you’re looking at it from an SoC perspective.”

He believes a lot of engineers don’t quite understand these tradeoffs. While it is certainly possible to get the performance with a very expensive technology at 28nm with all the process options, all the different masks that allow all the different voltages, a nice package and an expensive board or connector, the reality is that many SoCs must be designed and manufactured in the cheapest possible environment.

“This could be the biggest mixed-signal challenge, because every six months or so engineering teams look at ways of getting the cost down on their product. But they want the performance, too, so the ingenuity from the engineering side really needs to apply to that: ‘How can I get the most out of very little in terms of the package, the board material and such,’” Nandra continued.

Complicating mixed-signal designs is the persistent drive for lower power, said Pat Hunter, product marketing engineer responsible for developing strategies for point-of-load power solutions at Texas Instruments. “Integration and power consumption [are trends,] but the biggest trend I really see is battery life because we all know—we’re consumers—the biggest complaint we all have about our cell phones is the battery life. In TI we do a lot in the area of charging the battery, but the more important part of it is accurately gauging the capacity of the battery.”

Low-power challenges in mixed-signal come from a couple of aspects, noted Cadence’s Nizic. “One is that we brought more digital into analog. Before we didn’t worry much how much of that digital was consuming because it was really small parts. If I have instead of a few hundred or a couple thousand standard cells now I have a hundred thousand or a few hundred thousands with my analog, that’s becoming a significant part of my overall power budget. Second, I want to use this digital to better optimize power of my analog — shut it down when it’s needed — it’s all interacting — now I have to apply low-power techniques on my digital part but at the same time, that complicates my interfaces with analog. That’s another dimension when I try to verify power modes and functionally entire design.”

Like Nandra, TI’s Hunter has seen customer demand for cost reduction, as well as the accompanying struggle to make the right architectural tradeoffs.

Speaking to designing devices for longer battery life, Hunter said, “If you look at them like they are fuel gauges, the biggest architectural tradeoff is you are adding cost to your system because the microcontroller will have an analog/digital converter on board and they can do their own gauging. But it’s very inaccurate because the batteries have internal impedance, and if you don’t keep up with internal impedance you’ll think that there’s less energy in the battery than there really is. I’ve got customers that were doing laser wrinkle removers and so they had their own A-to-D gauging the battery. They were doing a cost reduction. But the biggest complaint from their end customers (the consumer) was that they could never trust the battery reading. Here’s the case where they were going to do a cost reduction but they are adding my part because they needed that extra accuracy. The challenge is trying to justify the extra cost. The way you do that is with consumers. If you’ve got two smartphones side by side—they pretty much all do the same thing nowadays—but if you’ve heard this one’s got twice the battery life you as a consumer will buy that. Nobody cares that my solution is in there. They just care what my solution does for the product.”

When it comes down to it, cost defines everything. “It’s choice of process technology, choice of the IP that you’re going to use, speeds that you’re targeting, packaging, risks you’re willing to take. In the end, if you were to devote significant resources your quality would be great, but you have to make that tradeoff now between ‘my cell phone probably is going to be on the market for six to nine months before someone is going to expect an update or a new cell phone, so do I need to now run through all the qualification standards that require five years of operation?’” Nandra said.

By Pallab Chatterjee
Integration of CODECS and graphics cores with new processor engines is proving to be a trouble spot for power optimization.

Because these blocks are driven by performance and are high-duty-cycle components, the main focus has been to push the limit for process performance.
These blocks still use most of the tricks identified by both UPF and CPF, including multi-phase clocking, dynamic voltage and frequency scaling, control of body bias, asynchronous paths, power gating, parallelism versus pipelines, and multiple supply domains/voltages. Those are in addition to process scaling from 40nm through 22nm. But when it comes to trading off area, power and performance, performance is the clear winner.

The reason: Graphics blocks, such as TI’s OMAP chip and several incarnations of the H.264 CODEC for high-resolution video, are now being combined with high-performance, low-power CPUs for full combination chips. These are different from standard processors because of the optimization of the data size and the idiosyncrasies of both replay and streaming video—and that’s where the power optimization problems come in. Video data is different from Web data in that it has to be processed and rendered locally to display on the screen. The task is increased in computational resource requirements when the block is called on to deliver ray tracing, 3D shading and output from multiple streams.

Typical computation requirements for video include pixel processing of 12-bit video data at resolutions of 1920 x 1080 (2,073,600 pixels) at 60 frames per second (1080p video) or 1,492,992,000 bits per second. Typical video is extended length of 10 minutes to 120 minutes in duration. As a result, the GPU and graphics processing cores do not go idle during the “operational data” stage as a CPU would upon idling down during extended memory operations and instruction preparation. This means the GPUs and CODECs tend to either be powered off completely when there is no video data being processed, but on at 100% to sometimes 120% of standard performance in the context of the video information. The 120% is achieved with overvoltage to drive the variable power supplies while using FSBB for driving the floating body of the device to provide maximum power supply levels and device switching speed.

In this mode, these GPU and CODEC blocks do not really benefit from the power management design techniques promoted by the tool flows and vendors. Instead, the single-digit percentage advantage they provide is both negated by the device use model (mid-power states, not “on” or “off”) or not generally encountered when used, which also contributes to design complexity. These devices benefit greatly from process scaling, as the reduced device size, power supply and interconnect capacitance reduction minimize the active power use. Papers submitted at the recent ISSCC conference indicate that process scaling resulted in double-digit power reductions from larger processes.

There are a number of things these devices share in common. One is that power isolation for the GPU and CODECs from the rest of the logic and CPUs is key. Second is the dynamic voltage and frequency scaling, which allows for overvoltage applications and clocks to keep data on time. Another feature is the shift from a single clock block to internal Async-Sync paths. This is the separation of multiple simultaneous synchronous paths that are normally clocked together, made up of a number of separate synchronous paths that start from a common register bank and end in a common register bank. These are then separated or decoupled from the per-path common clock to being individual function paths, each with its own synchronous clock. This type of path is a more power-efficient method than the old “ripple” style logic, which did not have managed switching peak power control.

While the low power techniques bring some value to the overall chip design, the benefits of advanced process scaling are in the single digits rather than double-digit power reduction. As a result, it may require some hard business decisions about whether the design overhead for squeezing out every last percentage of power is really worth it—or whether it makes more sense to get to market more quickly.

By Ed Sperling
Analog engineers have always scoffed at the amount of energy consumed by their digital colleagues. But ever since digital electronics have become tied to a battery, the shoe has been on the other foot. This hasn’t sat too well with the analog side of the house, and it’s beginning to show. The race is on to achieve energy efficiency on all sides.

Case in point: A Canadian company, Airtest Technologies, has created an infrared gas sensor for CO2 that it claims consumes 50 times less energy than conventional CO2 sensors, even while sampling up to 20 times per second. What’s different is that it uses an infrared LED developed by the U.K. military.

Another case in point: Texas Instruments introduced a new front end for femtocell base stations and portable software-defined radio. What’s particularly interesting with this application is the ability to maximize energy efficiency at the expense of performance, or vice versa. Having that kind of flexibility is a big win where usage models vary greatly, depending on what a device is used for or the cost of energy at a particular time of day.

What should put this sector toward even greater energy efficiency is the fact that in stacked die, re-engineering analog blocks for the latest process node won’t be an issue. They will be able to run at whatever process node makes sense, allowing analog engineers to put more effort into performance and efficiency rather than just meeting production deadlines.

By Ed Sperling
Software is the next big target in the quest to make electronics more energy efficient, but it’s proving a far bigger challenge than most systems architects originally believed it would be.

There are several very large big problems to deal with in software. Writing efficient code for small processors isn’t one of them. In fact, the proliferation of small processors across an SoC makes it easier to deal with at least a portion of the software software. Code can run directly on the bare metal, some of it can be nothing more than an executable file, and still other code can run on a real-time operating system written for a specific purpose or even on slimmed down versions of operating system code.

But bringing all of this code under the control of an SoC is another matter, despite the fact that this is the best way to manage power and minimize physical effects in a chip. Solving this problem requires integration and coherency across a chip, which in turn requires software architects and system architects to work together up front. This may be a goal among companies, but it certainly isn’t a reality.

“You need coherence to develop a high-end software design,” said Dan Driscoll, Nucleus software architect for Mentor Graphic’s Embedded Software Division. “At this point integration is a large portion of the effort, and the problem has yet to be solved. One thing that helps is a single development environment. If you use multiple profiling tools it’s more difficult to pull that together into a system.”

Devils in the details
Just understanding the interactions between various hardware portions of an SoC has far exceeded human limits in complex SoCs, even at mainstream process nodes. Most companies use a block or subsystem approach to deal with this complexity, working on smaller pieces and then assembling them into the whole and hoping it works as a single system.

Software increases the complexity by orders of magnitude, because an increasing amount of software now controls functionality across the chip. It determines what remains on, what gets turned off, in what sequence, at what speed, and what gets priority. It also determines how much power and memory can be allocated to a given function or logic subsystem—at least in 2D designs. (In stacked die, it may be possible to dedicate portions of memory to logic blocks to minimize this issue).

“This is the job of the controller software for the overall system,” said Frank Schirrmeister, group director for product marketing of the system development suite at Cadence. “You tell it to execute this API or put data over here. This is a high-level sequence, and it can do connectivity between different cores of a processor. You also can add up the energy transactions and memory transactions that will trigger.”

Multi-core, many-core, and multiple processors
A second big problem stems from the types of processors being used. The ability to write software applications that can take advantage of multiple cores is an old and well-understood issue—about four decades old, in fact. And while it’s easy for processor makers to add more cores onto a piece of silicon and hand it off to applications developers to deal with, the reality is that most applications cannot be parsed to take advantage of more than eight cores, and in many cases the number is likely to be fewer than four.

Databases, scientific calculations and graphics rendering, where there is extreme redundancy, are the exceptions. Even some games can have functionality parsed across cores. For most other applications, though, the limit it probably two to four cores. And if these cores are running popular general-purpose operating systems such as Windows, Mac OSX or Linux, chances are pretty good that it’s not the most efficient implementation of a function even though it may be the most convenient.

RTOSes have been used by the military for decades as a much more energy-efficient alternative, although most of that work was far less concerned about the energy than about security and performance. Their shift into commercial applications such as mobile phones makes them especially suitable for managing specific functions on separate processor cores in an SoC. It doesn’t make sense, for example, to utilize a multicore general-purpose processor for audio enhancements, and if it isn’t running on a general-purpose processor then it probably doesn’t need a general-purpose OS, either. But those functions still have to work with other parts of the chip without affecting signal integrity or creating hardware proximity effects such as heat, ESD and electromigration.

“The idea of SMP (symmetric multiprocessing) beyond 8 to 16 cores is not realistic for most applications,” said Mentor’s Driscoll. “We’re almost stuck with AMP (asynchronous multiprocessing) as part of large multicore implementations. But we’re seeing cases where you may have a TI OMAP 5, running a dual-core ARM Cortex A-9, an A4 and a DSP. You may have six or seven cores, and a general-purpose operating system going through this part of the system. That operating system may control other DSP interfaces, including RTOSes.”

Verification and testing brain freezes
This approach leads to another problem, though. How do engineering teams verify and test this complex SoC, which now may include multiple types of processors and processor cores, various types of software, and a central software management scheme that probably involves a standard operating system? There may even be middleware making some of the connections, and in homogeneous environments possibly even a virtualization layer that may include hypervisors that can run on bare metal.

“The first thing you have to deal with is a traffic debug issue,” said Cadence’s Schirrmeister. “In many cases, the partitioning may happen by hand. But how you pull this all together may affect your debug strategy. Tensilica presented an extreme example involving a printer design, where they had a block diagram of the functionality and the cores. The printer company used Tensilica cores, which allowed them to replace the functions done in RTL with programmable functions. The connections worked, the memories worked, and the functionality was done in software as bare-metal, low-level software.”

There’s a tradeoff in doing that, however. Driscoll said that pushing functionality down to lower-end processors makes integration more complex. In addition, measuring power consumption becomes more difficult because it means adding up energy transactions that the memory transactions will trigger.

“That means you need data to verify what works at the block level, the subsystem and in the overall system,” Schirrmeister said. “And some chips have processors you can’t access from outside for security reasons. You need flexibility in the software because of security, but you are not allowed to see it from the outside.”

Conclusion
While there has been much attention devoted to finding a common language between hardware and software engineers, the real path forward may be more focused on matching goals at the architectural stage, and then being able to swap information as a design progresses.

Virtual platforms that allow software to be developed earlier in the process help. So do some of the features that are being built into RTOSes these days. In addition, stacked die will help eliminate some issues, while creating new ones. But the real challenges will continue to be integration of hardware and software, and of various types of software with other software—with an eye toward remaining within a power budget and understanding how code affects energy consumed over time.

By Ed Sperling
Near-field communications has attracted an enormous amount of attention of late. Banks are allowing customers to scan checks from their cell phones and, increasingly, smart phones are being used for everything from airport access to paying bills at the grocery store. They’re even being used for parking lot fees.

But there’s a hidden pricetag behind all of this—the amount of energy needed to drive these transactions. That has led to a slew of development efforts behind the scenes, with the latest entry showing up this week from Texas Instruments. TI’s is bragging that its new NFC transceiver uses half as much power as the competitors’ products, running only as high as 120 milliampere in full-power mode and less than 1 microampere when it’s powered down.

TI clearly is not alone in this game of leapfrog. Companies such as Broadcom, Qualcomm and ST are racing in the same direction. But what’s interesting is that energy consumption has become the marketing focus rather than performance. The transceiver comes with eight possible power modes, which is particularly important in matching user preferences with the end devices.

EVM Board. Source: Texas Instruments

By Ed Sperling

The Other 3D
Intel will roll out processors using tri-gate finFET transistors at 22nm, which it says will sharply lower the operating voltage, boost performance and reduce leakage.

Multigate transistors have been the subject of research for decades, most prominently at UC Berkeley, because they can be used to reduce current leakage and increase density. Going vertical allows more transistors to be loaded onto a piece of silicon, which in the case of a processor is particularly important because more transistors can translate into better performance.

Intel claims the new structures will improve performance by 37% at low voltages. The company said that makes it ideal for small handheld devices, a market where Intel has not done very well in the past primarily because its chips are considered power hogs next to those using ARM and MIPS cores. That statement alone caused ARM’s stock to plunge 7% as speculation mounted that Intel could replace ARM cores inside of some Apple devices. This is pure speculation, of course. Apple never talks about that stuff and Intel hasn’t even intimated that. ARM’s stock recovered rather quickly, too.

Still, most companies have shied away from finFETs because they are extremely difficult to manufacture and potentially can add to the design and manufacturing cost. Intel’s big advantage in this regard is that it still owns its own fabs and develops its own manufacturing process, something that is far too costly for all but a handful of chipmakers.

An alternative to 3D structures is ultra-thin body silicon on insulator, which is now being tested by IBM, STMicroelectronics, Soitec and Globalfoundries. And there is a possibility of mixing things up to include both. But the writing is on the wall—big changes are ahead, and Intel’s move is a first big step in that direction.

TI Pushes FRAM
Microcontrollers have been used for years to reduce power in devices through such developments as multispeed motor control and intelligent sensors, but the real battle of late has been inside the microcontrollers themselves. Companies in this sector have been playing leapfrog with power numbers taking priority over performance increases.

TI’s latest rollout includes an ultra-low-power FRAM, or ferroelectric RAM (previously written as FeRAM). This type of RAM uses 250 times less power than EEPROM-based microcontrollers, according to TI, and can be written at speeds of 100 times faster. FRAM is not a new technology. It was developed in the 1990s by Ramtron, and has been manufactured by Fujitsu for more than a decade.

Apparently major strides have been made in the pricing of this technology since then. TI’s microcontroller is priced at $1.20.

By Pallab Chatterjee
What will be the next major improvement that will cut power levels by an order of magnitude?

That question was the basis of a roundtable discussion at the recent ISSC conference. Current technology provides incremental improvements each year, but the next generation of electronic systems will require dramatic changes and innovation. This premise is based on Gene’s Law—that’s Gene Frantz of Texas Instruments—which states that the power efficiency for DSPs doubles every 18 months.

The roundtable consisted of six panelists from TSMC, Hitachi, STMicroelectronics, UCLA, Infineon, and an industry veteran consultant. The interactive challenges were posed by domain experts from Imec, the University of Tokyo and Stanford University. In addition, it was moderated by Jan Rabaey of the University of California at Berkeley.

Rabaey outlined some of the major challenges as the opening for the discussion. Among them:

1. The impact of technology scaling being reduced for new processes;
2. The impact of voltage scaling is reduced as a proportion of new power supply levels;
3. Getting control of the wasted energy in the systems, and
4. Identifying energy efficient design architectures.

At the core of the discussion were two main themes. First, new devices will be at the center. And second, there will need to be new new tools and methods to implement these next-generation designs. The device migration is toward 3D devices and low leakage devices and substrates such as Fully Depleted SOI (FDSOI) and FinFETs. These structures have the ability to provide consistency in performance despite lithographic challenges. Lithography is just one of the many aspects of variability that area plaguing sub-20nm process technology.

The manufacturing challenges for these new devices have yet to be determined, but the solutions to these challenges will help shape the product designs and architectures. Moreover, yield, predictability and power performance will drive the operating power supplies and determine how much power is wasted in the design through heat and inefficiency in current transfer.

As these devices operate in a different voltage and current modes with different sensitivities from standard planar (2D) devices, new models and device-level simulation tools are needed to capture their characteristics. Due to the small geometries and the resulting large density vs. device units scaling, new matrix-solving routines need to be created to solve the equations without causing the tools to slow down or fail to converge to a solution. This is already driving changes in EDA and CAD to support the devices. The capacity, capabilities and throughput of the current EDA tools is not sufficient to be able to address the new 3D device requirements and their associated block and system designs.

One of the major challenges is to address the guard-banding and safety factors in the designs that are wasting power. Current worst-case design optimization wastes operating power by helping to identify corners of the design space that may not be reachable in practicality, but require power to stay away from. The capacity and extent of verification software that can address multiple levels of the design will have to be created. One of the major issues is creating architectural tools that can help do power optimization as a driving design function rather than just as an analysis tool.

Key issues involving these tools is who will solve the fundamental problems—industry or academia—and whether it will become a viable business. For academia to put resources on solving the guard-banding and multi-level design issues it will need funding from the government (NSF) or industry to pay for the student and facilities needed to complete the work. If it is done by industry, companies need to know that when answers are found that customers will buy the products and that they will have some time advantage over competitors. With the scope and breadth of the new tools that are required, and the skyrocketing costs of building chips at these advanced node, the issue of, ‘Will there be enough people who need the results of the effort for the tool development to be a business,’was left open as one of the keys for addressing the next power plateau.

By Ed Sperling
Redefining Portable Computing
The University of Michigan has shrunk a full-scale computer down to the size of a millimeter. Uses for the computer are varied, but initial targets—cited in the paper that was presented by researchers at the International Solid-State Circuits Conference in San Francisco this week—are in the sensor arena.

One proposal is to implant the computers to monitor eye pressure. A second is to monitor frequencies in wireless networks. What’s particularly interesting is the amount of power needed to drive these complete systems. The eye sensor requires 5.3 nanowatts of power, achieving these savings with a combination of power-gating and deep sleep modes.

The possibilities for this kind of technology are mind-boggling, both as standalone devices and as analog sensors that can be connected through wide I/O types of communications to other chips.

Better phone technology
Also at ISSC, MIT and Texas Instruments introduced a paper that details a DSP for mobile applications using as little as 0.6 volts at 28nm. The DSP scales from high performance at 1.0 volts down to the ultra low power mode.

What’s interesting about this development is the system-level focus that researchers used to develop this chip, customizing circuit styles, memories and timing. This should significantly increase the time between battery charges.

By Ed Sperling
Microsoft will develop its next version of Windows for AMD, Microsoft and ARM SoCs. The emphasis is on SoCs, and the focus of SoCs has been on two things: power and the reusability of existing and commercially developed IP.

This is an interesting challenge for Microsoft, as well as for Intel, AMD, and ARM’s slew of partners. A general-purpose OS takes a lot more code to create—and it takes a lot more power to use—than a real-time operating system or an embedded version. The result is greatly reduced battery life and more time with a plug in the wall. Even open-source Linux has the same problem, which is why companies such as Mentor Graphics offer a slimmed down embedded version.

The big question for architects of these SoCs will be one of priorities. What takes precedence? Is it processing power? Is it performance? Or is it segregation of more efficient code for individual cores.

Microsoft’s announcement doesn’t address these kinds of issues. Intel has said next to nothing other than a canned statement from Douglas Davis, VP and GM of the tablet group: “…what is so exciting is how our two companies will be able to match a tailored, low-powered operating system with future generations of our popular Intel Atom processors…”

And comments from ARM, and ARM customers Nvidia, Qualcomm and TI have been no more enlightening. This isn’t a simple problem to solve while maintaining backward compatibility with bloated applications developed when power efficiency were far less critical than ease of use and connectivity. And it’s not one that anyone is likely to be talking about for at least a year or more. But when they finally do start talking, it will be very interesting to hear how these companies will position Windows and its very large code base.

By Ed Sperling
The battle lines are shifting between ARM and Intel. While ARM has yet to make a significant dent in Intel’s computer stronghold and Intel has yet to make a dent in ARM’s mobile handset citadel, the crossover in netbooks and now tablets is fertile ground for both.

Raul “Ty” Garibay, director of OMAP IC engineering at Texas Instruments, summed it up quite well when he said that ARM’s Cortex-A15 is “the first time you get the performance of a desktop CPU with the footprint of a cell phone.” The result is you can choose your processor based on a number of factors without having to worry about performance.

Intel, meanwhile, is expected to launch its first tablet chips early next year. Code-named Oak Trail, the chips are expected to provide up to eight hours of battery life. Mileage may vary, of course, depending on your user settings, 4G reception and applications.

It’s something of a stretch to say that ARM will ever give up its core market to Intel or that Intel will give up its core market to ARM. But at least in Intel’s case, there is plenty of reason to at least try to branch out. Computer sales are healthy but not growing at the same kind of rate as smart phones. Moreover, buyers—even corporate buyers—tend to hold onto computers longer these days. The average turnover cycle has moved from every two years to as long as five to seven years.

That makes crossover markets such as tablets particularly enticing for Intel. And for ARM, fighting for a larger piece of the tablet market works like a buffer against its strongholds in areas such as portable electronics where extremely low power is critical.