By Ed Sperling
Analog engineers have always scoffed at the amount of energy consumed by their digital colleagues. But ever since digital electronics have become tied to a battery, the shoe has been on the other foot. This hasn’t sat too well with the analog side of the house, and it’s beginning to show. The race is on to achieve energy efficiency on all sides.

Case in point: A Canadian company, Airtest Technologies, has created an infrared gas sensor for CO2 that it claims consumes 50 times less energy than conventional CO2 sensors, even while sampling up to 20 times per second. What’s different is that it uses an infrared LED developed by the U.K. military.

Another case in point: Texas Instruments introduced a new front end for femtocell base stations and portable software-defined radio. What’s particularly interesting with this application is the ability to maximize energy efficiency at the expense of performance, or vice versa. Having that kind of flexibility is a big win where usage models vary greatly, depending on what a device is used for or the cost of energy at a particular time of day.

What should put this sector toward even greater energy efficiency is the fact that in stacked die, re-engineering analog blocks for the latest process node won’t be an issue. They will be able to run at whatever process node makes sense, allowing analog engineers to put more effort into performance and efficiency rather than just meeting production deadlines.

By Ed Sperling
Software is the next big target in the quest to make electronics more energy efficient, but it’s proving a far bigger challenge than most systems architects originally believed it would be.

There are several very large big problems to deal with in software. Writing efficient code for small processors isn’t one of them. In fact, the proliferation of small processors across an SoC makes it easier to deal with at least a portion of the software software. Code can run directly on the bare metal, some of it can be nothing more than an executable file, and still other code can run on a real-time operating system written for a specific purpose or even on slimmed down versions of operating system code.

But bringing all of this code under the control of an SoC is another matter, despite the fact that this is the best way to manage power and minimize physical effects in a chip. Solving this problem requires integration and coherency across a chip, which in turn requires software architects and system architects to work together up front. This may be a goal among companies, but it certainly isn’t a reality.

“You need coherence to develop a high-end software design,” said Dan Driscoll, Nucleus software architect for Mentor Graphic’s Embedded Software Division. “At this point integration is a large portion of the effort, and the problem has yet to be solved. One thing that helps is a single development environment. If you use multiple profiling tools it’s more difficult to pull that together into a system.”

Devils in the details
Just understanding the interactions between various hardware portions of an SoC has far exceeded human limits in complex SoCs, even at mainstream process nodes. Most companies use a block or subsystem approach to deal with this complexity, working on smaller pieces and then assembling them into the whole and hoping it works as a single system.

Software increases the complexity by orders of magnitude, because an increasing amount of software now controls functionality across the chip. It determines what remains on, what gets turned off, in what sequence, at what speed, and what gets priority. It also determines how much power and memory can be allocated to a given function or logic subsystem—at least in 2D designs. (In stacked die, it may be possible to dedicate portions of memory to logic blocks to minimize this issue).

“This is the job of the controller software for the overall system,” said Frank Schirrmeister, group director for product marketing of the system development suite at Cadence. “You tell it to execute this API or put data over here. This is a high-level sequence, and it can do connectivity between different cores of a processor. You also can add up the energy transactions and memory transactions that will trigger.”

Multi-core, many-core, and multiple processors
A second big problem stems from the types of processors being used. The ability to write software applications that can take advantage of multiple cores is an old and well-understood issue—about four decades old, in fact. And while it’s easy for processor makers to add more cores onto a piece of silicon and hand it off to applications developers to deal with, the reality is that most applications cannot be parsed to take advantage of more than eight cores, and in many cases the number is likely to be fewer than four.

Databases, scientific calculations and graphics rendering, where there is extreme redundancy, are the exceptions. Even some games can have functionality parsed across cores. For most other applications, though, the limit it probably two to four cores. And if these cores are running popular general-purpose operating systems such as Windows, Mac OSX or Linux, chances are pretty good that it’s not the most efficient implementation of a function even though it may be the most convenient.

RTOSes have been used by the military for decades as a much more energy-efficient alternative, although most of that work was far less concerned about the energy than about security and performance. Their shift into commercial applications such as mobile phones makes them especially suitable for managing specific functions on separate processor cores in an SoC. It doesn’t make sense, for example, to utilize a multicore general-purpose processor for audio enhancements, and if it isn’t running on a general-purpose processor then it probably doesn’t need a general-purpose OS, either. But those functions still have to work with other parts of the chip without affecting signal integrity or creating hardware proximity effects such as heat, ESD and electromigration.

“The idea of SMP (symmetric multiprocessing) beyond 8 to 16 cores is not realistic for most applications,” said Mentor’s Driscoll. “We’re almost stuck with AMP (asynchronous multiprocessing) as part of large multicore implementations. But we’re seeing cases where you may have a TI OMAP 5, running a dual-core ARM Cortex A-9, an A4 and a DSP. You may have six or seven cores, and a general-purpose operating system going through this part of the system. That operating system may control other DSP interfaces, including RTOSes.”

Verification and testing brain freezes
This approach leads to another problem, though. How do engineering teams verify and test this complex SoC, which now may include multiple types of processors and processor cores, various types of software, and a central software management scheme that probably involves a standard operating system? There may even be middleware making some of the connections, and in homogeneous environments possibly even a virtualization layer that may include hypervisors that can run on bare metal.

“The first thing you have to deal with is a traffic debug issue,” said Cadence’s Schirrmeister. “In many cases, the partitioning may happen by hand. But how you pull this all together may affect your debug strategy. Tensilica presented an extreme example involving a printer design, where they had a block diagram of the functionality and the cores. The printer company used Tensilica cores, which allowed them to replace the functions done in RTL with programmable functions. The connections worked, the memories worked, and the functionality was done in software as bare-metal, low-level software.”

There’s a tradeoff in doing that, however. Driscoll said that pushing functionality down to lower-end processors makes integration more complex. In addition, measuring power consumption becomes more difficult because it means adding up energy transactions that the memory transactions will trigger.

“That means you need data to verify what works at the block level, the subsystem and in the overall system,” Schirrmeister said. “And some chips have processors you can’t access from outside for security reasons. You need flexibility in the software because of security, but you are not allowed to see it from the outside.”

Conclusion
While there has been much attention devoted to finding a common language between hardware and software engineers, the real path forward may be more focused on matching goals at the architectural stage, and then being able to swap information as a design progresses.

Virtual platforms that allow software to be developed earlier in the process help. So do some of the features that are being built into RTOSes these days. In addition, stacked die will help eliminate some issues, while creating new ones. But the real challenges will continue to be integration of hardware and software, and of various types of software with other software—with an eye toward remaining within a power budget and understanding how code affects energy consumed over time.

By Ed Sperling
Near-field communications has attracted an enormous amount of attention of late. Banks are allowing customers to scan checks from their cell phones and, increasingly, smart phones are being used for everything from airport access to paying bills at the grocery store. They’re even being used for parking lot fees.

But there’s a hidden pricetag behind all of this—the amount of energy needed to drive these transactions. That has led to a slew of development efforts behind the scenes, with the latest entry showing up this week from Texas Instruments. TI’s is bragging that its new NFC transceiver uses half as much power as the competitors’ products, running only as high as 120 milliampere in full-power mode and less than 1 microampere when it’s powered down.

TI clearly is not alone in this game of leapfrog. Companies such as Broadcom, Qualcomm and ST are racing in the same direction. But what’s interesting is that energy consumption has become the marketing focus rather than performance. The transceiver comes with eight possible power modes, which is particularly important in matching user preferences with the end devices.

EVM Board. Source: Texas Instruments

By Ed Sperling

The Other 3D
Intel will roll out processors using tri-gate finFET transistors at 22nm, which it says will sharply lower the operating voltage, boost performance and reduce leakage.

Multigate transistors have been the subject of research for decades, most prominently at UC Berkeley, because they can be used to reduce current leakage and increase density. Going vertical allows more transistors to be loaded onto a piece of silicon, which in the case of a processor is particularly important because more transistors can translate into better performance.

Intel claims the new structures will improve performance by 37% at low voltages. The company said that makes it ideal for small handheld devices, a market where Intel has not done very well in the past primarily because its chips are considered power hogs next to those using ARM and MIPS cores. That statement alone caused ARM’s stock to plunge 7% as speculation mounted that Intel could replace ARM cores inside of some Apple devices. This is pure speculation, of course. Apple never talks about that stuff and Intel hasn’t even intimated that. ARM’s stock recovered rather quickly, too.

Still, most companies have shied away from finFETs because they are extremely difficult to manufacture and potentially can add to the design and manufacturing cost. Intel’s big advantage in this regard is that it still owns its own fabs and develops its own manufacturing process, something that is far too costly for all but a handful of chipmakers.

An alternative to 3D structures is ultra-thin body silicon on insulator, which is now being tested by IBM, STMicroelectronics, Soitec and Globalfoundries. And there is a possibility of mixing things up to include both. But the writing is on the wall—big changes are ahead, and Intel’s move is a first big step in that direction.

TI Pushes FRAM
Microcontrollers have been used for years to reduce power in devices through such developments as multispeed motor control and intelligent sensors, but the real battle of late has been inside the microcontrollers themselves. Companies in this sector have been playing leapfrog with power numbers taking priority over performance increases.

TI’s latest rollout includes an ultra-low-power FRAM, or ferroelectric RAM (previously written as FeRAM). This type of RAM uses 250 times less power than EEPROM-based microcontrollers, according to TI, and can be written at speeds of 100 times faster. FRAM is not a new technology. It was developed in the 1990s by Ramtron, and has been manufactured by Fujitsu for more than a decade.

Apparently major strides have been made in the pricing of this technology since then. TI’s microcontroller is priced at $1.20.

By Pallab Chatterjee
What will be the next major improvement that will cut power levels by an order of magnitude?

That question was the basis of a roundtable discussion at the recent ISSC conference. Current technology provides incremental improvements each year, but the next generation of electronic systems will require dramatic changes and innovation. This premise is based on Gene’s Law—that’s Gene Frantz of Texas Instruments—which states that the power efficiency for DSPs doubles every 18 months.

The roundtable consisted of six panelists from TSMC, Hitachi, STMicroelectronics, UCLA, Infineon, and an industry veteran consultant. The interactive challenges were posed by domain experts from Imec, the University of Tokyo and Stanford University. In addition, it was moderated by Jan Rabaey of the University of California at Berkeley.

Rabaey outlined some of the major challenges as the opening for the discussion. Among them:

1. The impact of technology scaling being reduced for new processes;
2. The impact of voltage scaling is reduced as a proportion of new power supply levels;
3. Getting control of the wasted energy in the systems, and
4. Identifying energy efficient design architectures.

At the core of the discussion were two main themes. First, new devices will be at the center. And second, there will need to be new new tools and methods to implement these next-generation designs. The device migration is toward 3D devices and low leakage devices and substrates such as Fully Depleted SOI (FDSOI) and FinFETs. These structures have the ability to provide consistency in performance despite lithographic challenges. Lithography is just one of the many aspects of variability that area plaguing sub-20nm process technology.

The manufacturing challenges for these new devices have yet to be determined, but the solutions to these challenges will help shape the product designs and architectures. Moreover, yield, predictability and power performance will drive the operating power supplies and determine how much power is wasted in the design through heat and inefficiency in current transfer.

As these devices operate in a different voltage and current modes with different sensitivities from standard planar (2D) devices, new models and device-level simulation tools are needed to capture their characteristics. Due to the small geometries and the resulting large density vs. device units scaling, new matrix-solving routines need to be created to solve the equations without causing the tools to slow down or fail to converge to a solution. This is already driving changes in EDA and CAD to support the devices. The capacity, capabilities and throughput of the current EDA tools is not sufficient to be able to address the new 3D device requirements and their associated block and system designs.

One of the major challenges is to address the guard-banding and safety factors in the designs that are wasting power. Current worst-case design optimization wastes operating power by helping to identify corners of the design space that may not be reachable in practicality, but require power to stay away from. The capacity and extent of verification software that can address multiple levels of the design will have to be created. One of the major issues is creating architectural tools that can help do power optimization as a driving design function rather than just as an analysis tool.

Key issues involving these tools is who will solve the fundamental problems—industry or academia—and whether it will become a viable business. For academia to put resources on solving the guard-banding and multi-level design issues it will need funding from the government (NSF) or industry to pay for the student and facilities needed to complete the work. If it is done by industry, companies need to know that when answers are found that customers will buy the products and that they will have some time advantage over competitors. With the scope and breadth of the new tools that are required, and the skyrocketing costs of building chips at these advanced node, the issue of, ‘Will there be enough people who need the results of the effort for the tool development to be a business,’was left open as one of the keys for addressing the next power plateau.

By Ed Sperling
Redefining Portable Computing
The University of Michigan has shrunk a full-scale computer down to the size of a millimeter. Uses for the computer are varied, but initial targets—cited in the paper that was presented by researchers at the International Solid-State Circuits Conference in San Francisco this week—are in the sensor arena.

One proposal is to implant the computers to monitor eye pressure. A second is to monitor frequencies in wireless networks. What’s particularly interesting is the amount of power needed to drive these complete systems. The eye sensor requires 5.3 nanowatts of power, achieving these savings with a combination of power-gating and deep sleep modes.

The possibilities for this kind of technology are mind-boggling, both as standalone devices and as analog sensors that can be connected through wide I/O types of communications to other chips.

Better phone technology
Also at ISSC, MIT and Texas Instruments introduced a paper that details a DSP for mobile applications using as little as 0.6 volts at 28nm. The DSP scales from high performance at 1.0 volts down to the ultra low power mode.

What’s interesting about this development is the system-level focus that researchers used to develop this chip, customizing circuit styles, memories and timing. This should significantly increase the time between battery charges.

By Ed Sperling
Microsoft will develop its next version of Windows for AMD, Microsoft and ARM SoCs. The emphasis is on SoCs, and the focus of SoCs has been on two things: power and the reusability of existing and commercially developed IP.

This is an interesting challenge for Microsoft, as well as for Intel, AMD, and ARM’s slew of partners. A general-purpose OS takes a lot more code to create—and it takes a lot more power to use—than a real-time operating system or an embedded version. The result is greatly reduced battery life and more time with a plug in the wall. Even open-source Linux has the same problem, which is why companies such as Mentor Graphics offer a slimmed down embedded version.

The big question for architects of these SoCs will be one of priorities. What takes precedence? Is it processing power? Is it performance? Or is it segregation of more efficient code for individual cores.

Microsoft’s announcement doesn’t address these kinds of issues. Intel has said next to nothing other than a canned statement from Douglas Davis, VP and GM of the tablet group: “…what is so exciting is how our two companies will be able to match a tailored, low-powered operating system with future generations of our popular Intel Atom processors…”

And comments from ARM, and ARM customers Nvidia, Qualcomm and TI have been no more enlightening. This isn’t a simple problem to solve while maintaining backward compatibility with bloated applications developed when power efficiency were far less critical than ease of use and connectivity. And it’s not one that anyone is likely to be talking about for at least a year or more. But when they finally do start talking, it will be very interesting to hear how these companies will position Windows and its very large code base.

By Ed Sperling
The battle lines are shifting between ARM and Intel. While ARM has yet to make a significant dent in Intel’s computer stronghold and Intel has yet to make a dent in ARM’s mobile handset citadel, the crossover in netbooks and now tablets is fertile ground for both.

Raul “Ty” Garibay, director of OMAP IC engineering at Texas Instruments, summed it up quite well when he said that ARM’s Cortex-A15 is “the first time you get the performance of a desktop CPU with the footprint of a cell phone.” The result is you can choose your processor based on a number of factors without having to worry about performance.

Intel, meanwhile, is expected to launch its first tablet chips early next year. Code-named Oak Trail, the chips are expected to provide up to eight hours of battery life. Mileage may vary, of course, depending on your user settings, 4G reception and applications.

It’s something of a stretch to say that ARM will ever give up its core market to Intel or that Intel will give up its core market to ARM. But at least in Intel’s case, there is plenty of reason to at least try to branch out. Computer sales are healthy but not growing at the same kind of rate as smart phones. Moreover, buyers—even corporate buyers—tend to hold onto computers longer these days. The average turnover cycle has moved from every two years to as long as five to seven years.

That makes crossover markets such as tablets particularly enticing for Intel. And for ARM, fighting for a larger piece of the tablet market works like a buffer against its strongholds in areas such as portable electronics where extremely low power is critical.

By Ed Sperling
If verification accounts for 70% of the non-recurring engineering expenses in a design, what percentage does verifying a low-power design actually consume?
Answer: No one knows for sure.

The reason has more to do with insufficient data than tools, processes or flows. That’s also the reason that power models have never been created for more than a single design.

“Power measurement is a challenging problem,” said Bhanu Kapoor, president of Mimasic, a low-power consultancy. “Everyone wants to have elements early in the design cycle, but all the power numbers depend on a very detailed implementation of the design. When you’re dealing with wires, you have all the information you need to calculate power. But at the front end you don’t have that kind of information.”

At least part of the problem also involves how different functions and their associated software are used within a design. In a cell phone, for example, a user may be taking a picture, sending e-mail or making a phone call. All of those are vectors in power and the number of possible combinations produce a lot of vectors.

“If you run it at the back end you have very few vectors and you can do a SPICE simulation,’ Kapoor said. “At the front end you don’t have the details to do it accurately.”

Derivative chips provide at least some relief from this process. Previous iterations of a chip can be used to provide at least some level of detail. But those calculations need to be redone at every new process node, particularly for the logic portion of the chip. Memory is much simpler.

The problem also becomes more complex as more power domains are added into the chip. Raul Garibay, director of OMAP IC engineering in Texas Instrument’s wireless business unit, said his company’s latest chips have 10 voltage domains and dozens of power domains.

“Being able to functionally verify those is one of the most critical things we do,” he told the audience at CDNlive!

Cross-talk needed
At least part of the issue facing design engineers can be solved by education and collaboration. Ask engineers at the system level, the RTL level and the signoff level to define low power and you’re likely to get different answers. But low power has become a global issue, which means everyone needs to start thinking about it the same way.

“The good news is that over the last two years, with all the fighting over CPF and UPF, people have become aware of the power issues,” said Xi Wang, technology group marketing director at Cadence. “There are different abstractions at the system level, the RTL level, the gate level and the physical level. The next step will be to link them all together. This will happen at the system level, which is where you have to estimate power. Ten years ago we estimated power at the RTL level.”

Some of that information needs to be provided by IP vendors, which isn’t always easy because they don’t fully understand how their IP will be used in designs. Standardized models currently do not exist in this area, although Si2 has created a modeling group to study this issue. So far, it remains in the exploratory stages.

“What isn’t well understood is that all low-power design involves mixed signal,” Wang said. “All the PLLs are design by analog engineers. Voltage scaling is all analog. And low-power is all about analog.”

Prototypical miscues
What isn’t always obvious is just how confusing prototypes can be in this process. Both software and FPGA prototypes can offer huge time savings in getting designs to market, but that sometimes comes at the expense of either performance or power.

“You usually can simulate and verify pretty well,” said Stephen Olsen, a technical marketing engineer at Mentor Graphics. “But there are some conditions, such as where a cache is between two cores, where if you access the same piece of memory in parallel you can slow down the performance. If the algorithm is written right it’s fine. But you don’t know that when you’re hit with the code.”

At least part of this is handled with traces. Frank Schirrmeister, director of product marketing for system-level solutions at Synopsys, said traces are run from software execution and those are executed at a lower level. And at the lower level, those traces are abstracted upward.

“If you make a fundamental wrong decision early on, it is not correctable by clock gating at the low level,” Schirrmeister said.

Those traces are also run inside an FPGA prototype to trace the data going through the chip. But FPGA prototypes, while capable of speeding designs, also add another wrinkle into the design process. In an FPGA, blocks cannot be turned off the way they can be in an ASIC. That makes gathering accurate power information harder because the interactions between blocks in different modes cannot be measured so it has to be estimated.

“If you use that profile to drive power estimation it’s going to be wrong,” said Cadence’s Wang. “Right now there is no infrastructure to shut off blocks, so it’s hard to fine-tune each chip design. We expect that will change in the next year or two.”

Conclusions
Verification has been one of the most time-consuming and expensive parts of designing semiconductors, particularly the functional piece, and that trend shows no signs of abating. While some very good tools do exist for making sure a chip is functionally correct and that it works, the kind of data necessary to build accurate power models early in the process are missing.

That will likely change over the next couple years, in part driven by EDA companies looking to cash in on this opportunity and in part because there will be enough clamor for standards that this type of information will need to be created. This will need to be accompanied by broad-based education about power, however, for it to be completely effective. And as many verification experts have made clear, no matter how good the tools there has to be training in how to use them.

By David Lammers
Over the past year, key technologists in the semiconductor industry have come around to believing that EUV lithography will be available for critical mask layers in the next three to five years. What is still up for debate is whether EUV will be cost-effective for low-power consumer SoCs. To penetrate that cost-sensitive market, EUV must overcoming hurdles presented by masks, damage to the collector optics, power consumption, and other costs of operation.

Memory makers, particularly the DRAM vendors with less-regular 2D structures than the more one-dimensional NAND devices, are fully on board the EUV bandwagon. However, several SoC makers such as Texas Instruments are on the fence. At the Sematech Litho Forum, TI’s Jim Blatchford, manager of lithography development and process simulation, argued that double and triple patterning with 193i scanners will better meet TI’s cost and performance objectives over the next five years.

TI seeks a 30% to 40% reduction in the node-to-node cost per die. For the 60nm routed pitch layers, corresponding to the 22/20 nm node, double patterning “is the only economically feasible solution,” Blatchford said in a detailed presentation on “lithonomics.” For the 14nm node, triple patterning will be required for the gate, contact, and metal 1 layers. “Double and triple patterning will be cost effective for die with a routed pitch of about 40nm,” he said.

“Triple patterning at the 44 nm pitch provides a 25% better cost reduction,” Blatchford said, adding that TI expects to use “aggressive” double patterning to meet its cost objectives at the 20nm node and “multi-patterning” at the 14nm node.

“The choice of lithography is an economic decision,” Blatchford said at the Sematech meeting. On the technical side, TI requires an overlay specification of 6nm to 10nm for triple patterning to work out. “We need another click in the overlay improvement from the scanner manufacturers,” Blatchford said.

Samsung expects EUV lithography to be less than half as expensive as double patterning. (Source: Samsung at the 2010 Sematech Litho Forum)

Most logic companies are cheering on the EUV technology to be ready for introduction at the 14nm node, giving designers more freedom from the restrictive design rules that would be required for extensive double patterning. Gary Patton, vice president at IBM’s semiconductor R&D center in Fishkill, N.Y., said “power is the new issue” facing device makers.

For IBM’s 15/14 nm technology, where the pitch will be about 80 nm, IBM may be forced to rely on double patterning, a variable light source, source-mask optimization, and continued imposition of design restrictions. If EUV were to be available for critical layers, Patton said IBM and its Fishkill partners could “relax the constraints on the light source and the mask, and avoid the need for design restrictions and double patterning.”

“At the 11 nm generation, we will certainly need EUV,” Patton said.

Jim Clifford, senior vice president of manufacturing at Qualcomm, also said the industry needs EUV to continue scaling, which he defined as increasing the transistor density within a set power budget. Costs are the main worry. “Is it going to be cheaper to scale if lithography is half the wafer cost?”

During a June 30th briefing at the ASML facility in Wilton, Conn., ASML vice president Noreen Harned outlined ASML’s efforts to get EUV ready. At its Netherlands facility, ASML has “completely built” one NXE 3100 pilot production scanner, with “another one right on its heels.” While Harned did not disclose which companies will get the six NXE 3100 systems, she did say that ASML had more than six companies queuing up to order the 3100 scanners. ASML decided to limit the 3100 to six units so it could move on the NXE 3300B volume production scanner by the first half of 2012. (ASML’s Harned describes the NXE 3100 as a pilot production machine that can be used for early production.)

Boosting the source power to >350 Watts is key to acceptable EUV wafer-per-hour throughput. (Source: ASML)

With IMEC as the expected first customer, other likely recipients of 3100 systems include Hynix, Intel, Samsung, Toshiba, and TSMC. One 3100 customer is expected to reach wafer-out status by the end of this year.

ASML installed the Cymer laser-produced plasma (LPP) source on the first 3100, but ASML is working with other source vendors. At the Wilton briefing, Harned announced that in early July ASML achieved the “first light” milestone on the first NXE 3100 platform, with a thermally controlled housing and mechanical dynamic stability. However, she said the source currently provides only 30-40% of the power ASML needs to achieve the 60 wph throughput target for the 3100 systems. The source power can be upgraded in-place, through various techniques, she said.

While Cymer appears to have the inside track at ASML thus far, Harned said the ASML EUV NXE platform was designed to be source neutral. Japan’s Gigaphoton Corp. is working on an LPP source that Harned said is similar to Cymer’s but which takes “a different approach to debris mitigation.” Among the discharge-produced plasma (DPP) vendors, Ushio Corp., working at its Aachen, Germany site, has made the most public progress so far. “All three have plans in place to meet the scanner needs. They all have credible roadmaps to intersect with high-volume production,” she said.

Asked about cost-of-ownership considerations, Harned said the lifetime of the collector optics is one concern. Unless mitigation efforts are improved, debris from the interaction of the laser and the tin droplets can damage the mirrors used to collect the source power. “The collector optics are the most-expensive consumable. Our target is a year, but it must be six months at the start. Fortunately, the collector optics are refurbishable,” she said.

Responding to a presentation by TSMC’s Burn Lin at the IEDM last December, in which Lin claimed that power consumption of the EUV scanners would make them impractical, Harned said ASML’s data shows that an EUV scanner and source will consume about 3X the power consumption of a 193 immersion scanner. “Power consumption is dominated by the source, and to a lesser extent by the need for vacuum operation. But it is about 3X, and that is a real measurement,” she said.