By Ed Sperling
If verification accounts for 70% of the non-recurring engineering expenses in a design, what percentage does verifying a low-power design actually consume?
Answer: No one knows for sure.

The reason has more to do with insufficient data than tools, processes or flows. That’s also the reason that power models have never been created for more than a single design.

“Power measurement is a challenging problem,” said Bhanu Kapoor, president of Mimasic, a low-power consultancy. “Everyone wants to have elements early in the design cycle, but all the power numbers depend on a very detailed implementation of the design. When you’re dealing with wires, you have all the information you need to calculate power. But at the front end you don’t have that kind of information.”

At least part of the problem also involves how different functions and their associated software are used within a design. In a cell phone, for example, a user may be taking a picture, sending e-mail or making a phone call. All of those are vectors in power and the number of possible combinations produce a lot of vectors.

“If you run it at the back end you have very few vectors and you can do a SPICE simulation,’ Kapoor said. “At the front end you don’t have the details to do it accurately.”

Derivative chips provide at least some relief from this process. Previous iterations of a chip can be used to provide at least some level of detail. But those calculations need to be redone at every new process node, particularly for the logic portion of the chip. Memory is much simpler.

The problem also becomes more complex as more power domains are added into the chip. Raul Garibay, director of OMAP IC engineering in Texas Instrument’s wireless business unit, said his company’s latest chips have 10 voltage domains and dozens of power domains.

“Being able to functionally verify those is one of the most critical things we do,” he told the audience at CDNlive!

Cross-talk needed
At least part of the issue facing design engineers can be solved by education and collaboration. Ask engineers at the system level, the RTL level and the signoff level to define low power and you’re likely to get different answers. But low power has become a global issue, which means everyone needs to start thinking about it the same way.

“The good news is that over the last two years, with all the fighting over CPF and UPF, people have become aware of the power issues,” said Xi Wang, technology group marketing director at Cadence. “There are different abstractions at the system level, the RTL level, the gate level and the physical level. The next step will be to link them all together. This will happen at the system level, which is where you have to estimate power. Ten years ago we estimated power at the RTL level.”

Some of that information needs to be provided by IP vendors, which isn’t always easy because they don’t fully understand how their IP will be used in designs. Standardized models currently do not exist in this area, although Si2 has created a modeling group to study this issue. So far, it remains in the exploratory stages.

“What isn’t well understood is that all low-power design involves mixed signal,” Wang said. “All the PLLs are design by analog engineers. Voltage scaling is all analog. And low-power is all about analog.”

Prototypical miscues
What isn’t always obvious is just how confusing prototypes can be in this process. Both software and FPGA prototypes can offer huge time savings in getting designs to market, but that sometimes comes at the expense of either performance or power.

“You usually can simulate and verify pretty well,” said Stephen Olsen, a technical marketing engineer at Mentor Graphics. “But there are some conditions, such as where a cache is between two cores, where if you access the same piece of memory in parallel you can slow down the performance. If the algorithm is written right it’s fine. But you don’t know that when you’re hit with the code.”

At least part of this is handled with traces. Frank Schirrmeister, director of product marketing for system-level solutions at Synopsys, said traces are run from software execution and those are executed at a lower level. And at the lower level, those traces are abstracted upward.

“If you make a fundamental wrong decision early on, it is not correctable by clock gating at the low level,” Schirrmeister said.

Those traces are also run inside an FPGA prototype to trace the data going through the chip. But FPGA prototypes, while capable of speeding designs, also add another wrinkle into the design process. In an FPGA, blocks cannot be turned off the way they can be in an ASIC. That makes gathering accurate power information harder because the interactions between blocks in different modes cannot be measured so it has to be estimated.

“If you use that profile to drive power estimation it’s going to be wrong,” said Cadence’s Wang. “Right now there is no infrastructure to shut off blocks, so it’s hard to fine-tune each chip design. We expect that will change in the next year or two.”

Conclusions
Verification has been one of the most time-consuming and expensive parts of designing semiconductors, particularly the functional piece, and that trend shows no signs of abating. While some very good tools do exist for making sure a chip is functionally correct and that it works, the kind of data necessary to build accurate power models early in the process are missing.

That will likely change over the next couple years, in part driven by EDA companies looking to cash in on this opportunity and in part because there will be enough clamor for standards that this type of information will need to be created. This will need to be accompanied by broad-based education about power, however, for it to be completely effective. And as many verification experts have made clear, no matter how good the tools there has to be training in how to use them.

By David Lammers
Over the past year, key technologists in the semiconductor industry have come around to believing that EUV lithography will be available for critical mask layers in the next three to five years. What is still up for debate is whether EUV will be cost-effective for low-power consumer SoCs. To penetrate that cost-sensitive market, EUV must overcoming hurdles presented by masks, damage to the collector optics, power consumption, and other costs of operation.

Memory makers, particularly the DRAM vendors with less-regular 2D structures than the more one-dimensional NAND devices, are fully on board the EUV bandwagon. However, several SoC makers such as Texas Instruments are on the fence. At the Sematech Litho Forum, TI’s Jim Blatchford, manager of lithography development and process simulation, argued that double and triple patterning with 193i scanners will better meet TI’s cost and performance objectives over the next five years.

TI seeks a 30% to 40% reduction in the node-to-node cost per die. For the 60nm routed pitch layers, corresponding to the 22/20 nm node, double patterning “is the only economically feasible solution,” Blatchford said in a detailed presentation on “lithonomics.” For the 14nm node, triple patterning will be required for the gate, contact, and metal 1 layers. “Double and triple patterning will be cost effective for die with a routed pitch of about 40nm,” he said.

“Triple patterning at the 44 nm pitch provides a 25% better cost reduction,” Blatchford said, adding that TI expects to use “aggressive” double patterning to meet its cost objectives at the 20nm node and “multi-patterning” at the 14nm node.

“The choice of lithography is an economic decision,” Blatchford said at the Sematech meeting. On the technical side, TI requires an overlay specification of 6nm to 10nm for triple patterning to work out. “We need another click in the overlay improvement from the scanner manufacturers,” Blatchford said.

Samsung expects EUV lithography to be less than half as expensive as double patterning. (Source: Samsung at the 2010 Sematech Litho Forum)

Most logic companies are cheering on the EUV technology to be ready for introduction at the 14nm node, giving designers more freedom from the restrictive design rules that would be required for extensive double patterning. Gary Patton, vice president at IBM’s semiconductor R&D center in Fishkill, N.Y., said “power is the new issue” facing device makers.

For IBM’s 15/14 nm technology, where the pitch will be about 80 nm, IBM may be forced to rely on double patterning, a variable light source, source-mask optimization, and continued imposition of design restrictions. If EUV were to be available for critical layers, Patton said IBM and its Fishkill partners could “relax the constraints on the light source and the mask, and avoid the need for design restrictions and double patterning.”

“At the 11 nm generation, we will certainly need EUV,” Patton said.

Jim Clifford, senior vice president of manufacturing at Qualcomm, also said the industry needs EUV to continue scaling, which he defined as increasing the transistor density within a set power budget. Costs are the main worry. “Is it going to be cheaper to scale if lithography is half the wafer cost?”

During a June 30th briefing at the ASML facility in Wilton, Conn., ASML vice president Noreen Harned outlined ASML’s efforts to get EUV ready. At its Netherlands facility, ASML has “completely built” one NXE 3100 pilot production scanner, with “another one right on its heels.” While Harned did not disclose which companies will get the six NXE 3100 systems, she did say that ASML had more than six companies queuing up to order the 3100 scanners. ASML decided to limit the 3100 to six units so it could move on the NXE 3300B volume production scanner by the first half of 2012. (ASML’s Harned describes the NXE 3100 as a pilot production machine that can be used for early production.)

Boosting the source power to >350 Watts is key to acceptable EUV wafer-per-hour throughput. (Source: ASML)

With IMEC as the expected first customer, other likely recipients of 3100 systems include Hynix, Intel, Samsung, Toshiba, and TSMC. One 3100 customer is expected to reach wafer-out status by the end of this year.

ASML installed the Cymer laser-produced plasma (LPP) source on the first 3100, but ASML is working with other source vendors. At the Wilton briefing, Harned announced that in early July ASML achieved the “first light” milestone on the first NXE 3100 platform, with a thermally controlled housing and mechanical dynamic stability. However, she said the source currently provides only 30-40% of the power ASML needs to achieve the 60 wph throughput target for the 3100 systems. The source power can be upgraded in-place, through various techniques, she said.

While Cymer appears to have the inside track at ASML thus far, Harned said the ASML EUV NXE platform was designed to be source neutral. Japan’s Gigaphoton Corp. is working on an LPP source that Harned said is similar to Cymer’s but which takes “a different approach to debris mitigation.” Among the discharge-produced plasma (DPP) vendors, Ushio Corp., working at its Aachen, Germany site, has made the most public progress so far. “All three have plans in place to meet the scanner needs. They all have credible roadmaps to intersect with high-volume production,” she said.

Asked about cost-of-ownership considerations, Harned said the lifetime of the collector optics is one concern. Unless mitigation efforts are improved, debris from the interaction of the laser and the tin droplets can damage the mirrors used to collect the source power. “The collector optics are the most-expensive consumable. Our target is a year, but it must be six months at the start. Fortunately, the collector optics are refurbishable,” she said.

Responding to a presentation by TSMC’s Burn Lin at the IEDM last December, in which Lin claimed that power consumption of the EUV scanners would make them impractical, Harned said ASML’s data shows that an EUV scanner and source will consume about 3X the power consumption of a 193 immersion scanner. “Power consumption is dominated by the source, and to a lesser extent by the need for vacuum operation. But it is about 3X, and that is a real measurement,” she said.

By Ed Sperling
ARM, Freescale, IBM, Samsung, ST-Ericsson and Texas Instruments teamed up to create “Linaro,” an open-source software engineering company. The stated goal is to speed the development of Linux tools and foundation software. While this is great for large processors, the real question is just how much Linux technology will be scaled down. In many applications, size matters, and being able to work with open source software in a smaller footprint is a big plus when it comes to power issues.

MIPS added symmetric multiprocessing support for the Android platform using multicore MIPS SoCs. This gets particularly interesting because in addition to multi-threaded applications, there is a trend to dedicate specific functions for cores. The possibilities are enormous, both in terms of functionality and more efficient power utilization.

Mentor Graphics updated its verification lineup just in time for DAC. The company rolled out version 3 of its O-In formal verification, adding better support for mixed language design and tighter integration with its Questa platform. The company also released a O-In CDC update for clock-domain crossing verification. While these are interesting releases in their own right, it looks particularly interesting for SiP and 3D stacking.

Synopsys, meanwhile, rolled out high-level synthesis support for Xilinx’s Virtex-6 FPGAs. Design of FPGAs used to be relatively straightforward, but at advanced process nodes they encounter the same headaches that SoCs do—area, power, performance and verification.

Sound quality may be the next big selling point in the PC and netbook space, along with battery life and I/O speed. ASUS is betting the bank on Virage Logic’s Sonic Focus as a differentiator, complete with new enhancements. So much for the tinny-sounding speakers that make it next to impossible to understand anything.

By Ellen Konieczny

Imagine that you go to your kitchen to get a drink and pass your home’s energy-usage monitor. Due to a recent heat wave, you see that your energy usage is already at what it usually is for the entire month. Yet you’ve still got one week left in your billing cycle. To keep the bill low, you turn your A/C thermostat up a degree and make a mental note to not keep lights on unnecessarily.

The next day, the weather is more comfortable. You log in from work and turn the A/C off completely. Such capabilities are not farfetched, thanks to plans to roll out smart-grid networks across the globe (see Figure 1). In fact, some utility companies have already tested these technologies. For such two-way communications to be realized on a grand scale, however, the infrastructure, smart meters, and millions of wireless devices involved will need to consume minimal power.

Fig. 1: The various aspects of the smart grid and how they will be connected. (Courtesy of Ember Corp.)

Emmanuel Sambuis, general manager for the metering business at Texas Instruments, says water and gas meters now require 20-year operation from the same battery. In some devices, the requirements are now as much as 25 to 30 years—particularly in areas where batteries are particularly difficult to access or where there are so many devices that changing out batteries can become expensive. In some extreme cases, companies have been developing energy-scavenging solutions that require no batteries at all.

What’s changing, however, is the addition of low-power communications technology inside of even home-area-network products, such as in-home displays and intelligent thermostats. Generally, such low-power communications are RF-based. In the case of power-line communications, regulations also apply and force the energy consumption to be minimal. To raise energy efficiency in e-metering applications, TI has developed an SoC microcontroller that integrates all metering functionality onto a single chip, with ultra-low-power operation so that only simple voltage regulation is required for a complete solution. The MCU provides direct device operation from a 3V supply with the CPU and ESP active at only 2.5 mA. During a power outage, the device can operate in standby mode at 1.1 µA with the real-time clock function active.

It is essential to keep in mind that smart-grid devices will most likely be asleep for the majority of the time. “The biggest challenge is in enabling the battery-operated devices to not be awake for long periods as well as for them to be able to join the network, acquire and process any data as quickly and efficiently as possible, and go back to sleep, said Skip Ashton, senior vice president of engineering at Ember Corp. “Designing technology–radio, processor, and networking software–which enables devices to do that reliably and securely is the crux. A user of a battery-operated device expects instant operation and control when they are using it but long battery life when they are not. This type of ‘instant-on’ capability requires coordination of the radio as well as the software controlling the devices.”

Thankfully, standards bodies like the ZigBee Alliance (www.zigbee.org) include low-power operation as a critical goal as they develop their protocols. For suppliers implementing the protocols and hardware, however, Ashton emphasizes it is important to view the technology offering as a “system” that includes hardware and software. “A tightly integrated platform, which has been developed from the ground up to work together to deliver excellent performance, efficiency in code size, and processing of security and application data, lends itself to better resolve the challenge of minimizing power consumption and extending battery life. Although the standards can prescribe a certain level of behavior, different suppliers can innovate within the standard to improve performance,” Ashton says.

In addition to running IEEE 802.15.4/ZigBee wireless, for example, the MeshConnect modules and integrated circuits (ICs) from California Eastern Laboratories promise to get good range out of a very low-powered device (Fig. 2). According to David Cohen, director of marketing, and Rich Howell, director of business development, the MeshConnect modules and ICs put out +7 dBm power out native (i.e., without using an external power amplifier). The MeshConnect technology delivers standby mode at less than 0.3 µA.

Figure 2: With sleep-mode power consumption below 1 µA, the MeshConnect Extended Range Module offers extended battery life

Although such products are impressive innovations on their own, they are only part of a bigger picture. A successful smart grid will require close collaboration between providers of communication devices (RF transceivers and processors, for example), providers of communication software, and designers of communication systems. In addition, success will largely depend on advances in signal processing.

“Smart-grid technology developers look to advanced digital and analog signal-processing technology to power next-generation energy infrastructure,” said Ronn Kliger, energy group director at Analog Devices. “By leveraging ICs optimized for a range of smart-grid applications—from energy-metering solutions to dynamic, grid-integrated management and communication systems—developers are able to design intelligent systems that promote energy efficiency and management flexibility.”

Along with energy-metering ICs, the firm offers RF, power-line carrier communication, power management, and digital signal processing in support of smart-grid applications.

Measurement capabilities also will need to be fine-tuned, as standby or “vampire” power poses a clear threat to the smart grid’s low-power-consumption efforts. Standby power results from electronic devices that are plugged into wall sockets, such as TVs, DVD players, cell phones, and answering machines. Whether they are on or off, they consume power 24 hours a day. It is difficult to accurately measure the power that they actually use, however, which is why they must be accounted for in the smart grid. A number of companies have developed ways to measure even the smallest amounts of energy usage. For example, Teridian claims to provide accuracy of +/-0.5% over a 2000:1 dynamic range.

Of course, the most frightening specter haunting power consumption in smart-grid devices may be standby current. This issue becomes especially critical for the finest silicon technology nodes, where transistor leakage current starts to dominate. Leakage power already poses a significant problem at advanced process nodes, and the problem increases with density at advanced nodes. The dynamic power dissipation arising from high-frequency switching of the tens of millions of transistors directly impacts aspects like battery life, packaging and cooling costs, form factor, and reliability.

All of the major EDA companies are now advising SoC developers to consider low power as part of the architecture rather than something implemented later in the flow, and entire flows are becoming power-aware and power optimized. That goes for the process as well as the components. Third-party IP vendors such as Virage Logic, ARM and Synopsys are now standardized on low power versions rather than splitting their product lines between IP geared for low power and performance, and even in the FPGA space, where concern for power was either an afterthought or non-issue, all of the major vendors are now offering lower-power solutions. Actel has even developed chips that rival the power consumption of some of the most advanced ASICs.

By Ed Sperling

Jan. 14, 2010—The current raft of companies emphasizing low power is growing. What’s changing is it’s no longer just limited to the portable market, where battery life is critical, or even the corporate data center, where reducing power on thousands of servers can save big bucks.

Via Technologies this week rolled out a compact server for the home office and small business market that utilizes its own 64-bit low-power processors and chipsets, which normally are used in laptops.

AMD’s ATI video card unit also unveiled a new GPU that draws significantly less power than previous versions. In idle mode, it draws only 15 watts, and at maximum power it runs only 64 watts. Given the fact that this is a high-definition graphics engine attached to a plug, this is a major step forward—particularly in the PC gaming world where power carries the same bragging rights as horsepower on a sports car.

Media Excel and Texas Instruments, meanwhile, are collaborating on low-power versions of network-based transcoding electronics for HD, scalable video. This deal is aimed at the MobileTV, WebTV and IPTV world, which has steadily been gaining adherents even if it hasn’t replaced regular television. Most of these units rely on a plug, although they have slipped under the radar screen of regulators looking to cut power consumption in large-screen TVs.

By Cheryl Ajluni
Power conversion is a general term that refers to a system or device producing an output that is different than its input. It can assume many forms—everything from an inverter to an isolated power supply, uninterruptable power supply (UPS), or AC/DC converter. Power conversion, like low-power design, is fairly commonplace these days. Nevertheless, recent advances in digital power solutions (e.g., the ability to address high-frequency switch-mode operation) are making it much more palatable for engineering low power, portable applications.

In an attempt to gain a better understanding of power conversion and its relation to low-power engineering, LPE recently posed a few questions to Don Alfano, applications director for power products at Silicon Labs.

LPE: How is power conversion beneficial to enabling low-power design?
Alfano: With all of the attention focused on ‘going green,’ low-power design is politically and economically very important. However, the real reason low-power design can be beneficial is based more in practice than populist opinion. One obvious example lies in battery-operated systems such as iPods, cell phones, GPS systems, and so on. The operating time of these systems is directly related to the system power consumption and battery capacity. Since higher capacity batteries are typically bulkier, it is more desirable to limit operating power than to increase battery capacity.

Another example involves consumer devices that are powered by the AC line. Devices such as flat-panel TVs, desktop PCs and consumer audio devices consume relatively large amounts of power due to their sheer volume (e.g., 1000 watts per TV x 5 million TVs = 5 billion watts of electricity). A mere 10% improvement in operating efficiency can save 500 million watts of power, and how many tons of coal does it take to make that much power? The answer is a lot.

It’s because of this that standby power requirements (e.g., power consumed when the TV is “off”) for these devices have come under scrutiny by certification agencies such as EnergyStar. Consider that the average TV consumes 10 watts of power when “off.” Applying the same 5 million TV sets, the power consumed would be 50 million watts. Reducing standby power to the new standard of 1 watt results in a savings of 45 million watts of power. The bottom line: low-power design extends the operating time of battery-operated devices, while reducing battery weight. Low-power design also results in greater operating economy when implemented in AC line-powered devices.

Are there any obstacles or challenges that engineers need to be aware of in applications requiring power-conversion technology, such as ac-dc or dc-dc?
Both linear and switch-mode power conversion systems have been around for decades, and their control technologies are well-developed. That being said, one common obstacle is the tradeoff between the emission of electromagnetic interference (EMI) and efficiency. In any power system design, the engineer strives for the highest efficiency. However, certain portions of the circuit can act as parasitic “radio transmitters,” causing EMI that can be induced into other devices. A classic example is the noise that appeared on a television screen when an old-time vacuum cleaner was turned on. Federal Communications Commission (FCC) regulations now prohibit such emissions, forcing the power system designer to add parts into his design that ‘snub’ (eliminate) these emissions. Such circuits dissipate power and degrade efficiency.

Another classic tradeoff is efficiency vs. physical size. Switch-mode power systems become smaller when they are designed to operate at high frequencies. However, these high frequencies cause lower operating efficiency. Reducing the operating frequency results in higher efficiency but requires larger, bulkier transformers, which adds size, cost and weight.

Have there been any recent advances in power-conversion technologies or techniques?
Yes, digital power control is catching on after a slow start. Digital power effectively uses digital computer technology to control power conversion instead of traditional analog control circuits. Digital power control can enable more sophisticated power-conversion algorithms that can increase efficiency and system responsiveness while (ultimately) lowering cost. Another trend is the use of analog resonant power-conversion control circuits, which can boost efficiency and decrease system cost. These are becoming popular in consumer electronics like flat panel TVs.

***

Alfano’s comments serve to underscore an important point—that digital power solutions and digital power control are highly relevant topics these days (See figure 1). One reason is that by minimizing high-speed circuit components and leveraging smaller process geometries, digital power solutions have simply become more practical for portable devices. Additionally, since digital power solutions integrate power control and power management, they are much more flexible than analog solutions and able to address higher levels of complexity, including the different operational modes of portable applications.

Figure 1. One example of a digital power solution comes from Microchip. It offers two device families for digital power applications: the dsPIC30F and dsPIC33F (pictured here) SMPS and digital-power conversion families. These devices include peripherals specifically designed for power conversion. Peripherals such as a high-speed PWM, ADC and analog comparators can be tied together using an internal configurable control fabric that enables them to interact directly with one another, resulting in significant performance gains in digital power applications.

Alfano adds that, “As its name implies, digital power control is based on digital processor technology. As such, the digital power controller can make informed control decisions based on multiple, real-time data it continuously gathers. For example, the digital power controller can measure various key operating parameters within the system such as input voltage and output current, then dynamically adjust or otherwise influence the operation of internal system components so as to maximize system operating efficiency (e.g., minimize power loss). In so doing, the digital power controller has the ability to maximize system efficiency across the power conversion system’s entire operating range.”

In addition to allowing the designer to adapt to different operating parameters, digital power control also has the ability to switch between compensators as a function of operational modes. Phase management, such as phase shedding and adding based on load requirements, is another capability that is possible with digital power control and one that is especially beneficial for applications that utilize multiphase regulators.

With portable applications continuing to weave their way through society, the current focus on low-power design shows no signs of letting up any time soon. Power conversion, digital power solutions and digital power control will therefore continue to be topics of great interest to designers. Such solutions offer flexibility as well as the ability to increase system efficiency—features which are highly prized in today’s portable market.

More information on power conversion, digital power solutions and digital power control is available from an array of companies working in this arena. Among those companies are Freescale, Intel, International Rectifier, Intersil, Microchip, Silicon Labs, STMicroelectronics and Texas Instruments.

By Ed Sperling

Business seems to be picking up everywhere in the design world, with an emphasis on speed—quicker deals, faster product rollouts and overall time to market—and all of it with an underlying emphasis on low power and tighter power budgets. Could it be that after the recession, everyone is trying to get back on track quickly?

Virage Logic completed the acquisition of NXP’s IP technology and its development team. That comes on the heels of its recent acquisition of ARC. The fact that Virage completed both of these acquisitions in a 12-day period is nothing short of an accounting miracle. And just in case the company didn’t have enough to do, it added a Silicon Browser for post-silicon bring-up and system debug.

Android seems to be getting its share of attention these days. Mentor Graphics introduced an Android Development System for Texas Instrument’s OMAP35x processors. TI’s processors also include ARM Cortex-A8 technology, which puts ARM squarely in the center of this effort, as well, with a heavy push toward better battery life. But will any of this take a bite out of the Apple iPhone?

On the get-things-done-quicker side, Digital Imaging Systems used Synopsys’ Galaxy Custom Designer to achieve first-pass silicon in 22 days. Not all of it was from scratch, of course, but that’s still a very tight timetable.

And Atrenta’s deal with Fujitsu’s Kyushu Network Technologies is aimed at reducing design risks in integration of third-party IP from multiple vendors with different clock domains. Translation: Faster time to market.

Also on the business side, Cadence expanded its design alliance with Toshiba for the consumer and mobile markets.

Intel invested millions of Euros in an Exascale Computing Research in France, as part of Intel Labs Europe. This is the second time in two weeks that Intel has paid out big bucks to appease antitrust regulators. This deal will add 900 new research jobs in Europe. That follows Intel’s settlement with AMD, clearing the way for Intel to go after ARM with its Atom chip.

ARM’s comeback was largely a reiteration of the strength of its ecosystem. It struck up a strategic architectural license agreement with Infineon for advanced security applications and created a solutions center for Android.

By Cheryl Ajluni

It wasn’t all that long ago that voice communication via a traditional landline was the norm. At the time, consumers would have been hard pressed to imagine a world in which anytime, anywhere communication (voice and data) with a device no bigger than the human hand was possible.

Many of those same consumers might today find it hard to conceive of a world in which their mobile phones are powered by the jacket they are wearing, but that too—like the mobile phone—may one day become a commercial reality. Given the ongoing research and developments in this area, that reality may be closer than many people think.

One technology hoping to give life to this vision is energy harvesting—a process by which energy is derived from an external ambient source (e.g., kinetic energy, RF, solar power, thermal energy, or vibration and wind energy), captured and then stored. Energy harvesting devices convert the ambient energy into electrical energy. In a wearable electronics application, for example, power captured from an ambient energy source is converted to electrical energy and stored in a device like a battery or a capacitor. The stored power can then travel through a microprocessor and be subsequently transmitted, usually wirelessly. Energy harvesters generally provide only small amounts of power (e.g., just a few milliwatts), dependent in part on their design and size, and are therefore considered suitable for powering low-energy electronics or small, autonomous devices like those used in wearable electronics and wireless sensor networks.

Energy harvesting technology has a number of critical benefits, namely cost and extended battery life. Ambient energy, the fuel that drives energy harvesters, is present in large quantities in nature and is, for all practical purposes, free. By harvesting or “scavenging” small amounts of power from these sources, the battery life of existing devices can be extended. But energy harvesting also has the potential to enable a new class of battery-free devices that can be powered indefinitely and deployed with minimal to no maintenance.

The problem with energy harvesting is that it requires ready availability of a potentially unreliable power source. In very simplistic terms: what happens if the energy harvester relies on wind and the wind dies down? Or what if it relies on sun and it’s a cloudy day? One possible solution to this dilemma is RF energy harvesting, which is now being eyed by the wireless communications industry as a viable power source for wireless electronic devices. RF energy is, after all, available everywhere—particularly in metropolitan areas. Moreover, RF energy harvesting can be coupled with a dedicated radio transmitter to provide remote power that is controllable through continuous, scheduled or on-demand power transmissions.

Energy harvesting on the cusp
RF energy harvesting devices have the potential to one day be used to power or recharge mobile phones, mobile computers, and even radio communications equipment using ambient radio waves emitted from WiFi, phone towers, television signals, and other sources. But is the technology really ready for prime time? In truth, the commercialization of this technology is likely a number of years away, but there is definitive progress being made. One company actively exploring that very possibility is the Finnish mobile phone maker Nokia. At the Nokia Research Center (NRC), researchers are investigating the concept of an energy harvesting handset—one that uses energy harvesting technology to recharge itself using only ambient radio waves. Energy harvesting would need to account for roughly 20 mW+ of power to keep a handset in standby mode indefinitely. Recharging the handset’s battery would require approximately 50 mW of power.

Intel also is actively researching the harvesting of free energy sources like the sun, kinetic energy and RF energy. In fact, earlier this year it conducted an experiment in which it harvested ambient RF energy using a television antenna pointed at a local television station tower. It harvested enough energy to actually power a wall-mounted, household weather station with an LCD screen, effectively proving that wireless power over a distance and battery-free operation is possible.

For the experiment, Intel employed an ambient RF harvesting technique similar to technology typically employed with off-the-shelf RFID tags. Here, unpowered ID tags are powered wirelessly from a tag reader that supplies just enough power to the ID tag so that it can read the information it contains. With RFID tags, the ID tag and tag reader must be in close proximity to one another. With Intel’s RF harvesting technique, the weather station was powered by a television station antenna located some 4 km away. The television antenna was connected to a 4-stage charge pump power harvesting circuit featuring the same design as that found in an RFID tag. Across an 8-KOhm load, researchers measured 0.7 V, corresponding to 60 microwatts of power harvested. That was enough to drive a thermometer/hygrometer and its LCD display, which is normally powered by a 1.5-volt AAA battery.

Key enablers
One factor playing a key role in moving RF energy harvesting forward is the advent of ultra-low power electronics for the power-conscious wireless communications industry. In the past, engineers and researchers working on energy harvesting technologies were hard-pressed to make their energy harvester designs work. They simply couldn’t harvest enough power to run a microcontroller. Today though, the power being harvested with energy harvesting devices is on the rise and the power electronic products require is decreasing. The convergence of these two trends is, for the first time, making energy harvesting technology a viable energy source in many markets, and could result in the emergence of a new class of renewable energy applications that essentially run forever—autonomously, remotely and without a battery.

Two companies that are working hard to develop low-power electronics (e.g., DSPs, microcontrollers, RF transceivers, and sensors operating on just μA’s of electrical current) for use in emerging technologies like energy harvesting are Analog Devices and Texas Instruments. ADI, for example, offers an ultra-low-power MEMS (microelectromechanical system) sensor, the ADXL345, which consumes 120 μA in full dynamic range and 25 μA in sleep mode (Figure 1). TI’s MSP430 microcontroller consumes a mere 160 μA/MHz in an active state and 1.5 μA/MHz in standby mode (Figure 2).

Figure 1. Shown here is a functional block diagram of ADXL345—a small, thin, low power, 3-axis accelerometer with high resolution (13-bit) measurement at up to ±16 g.

Figure 2. TI’s MSP430 MCUs are comprised of a 16-bit RISC CPU; modular, memory-mapped analog and digital peripherals; and a flexible clock system combined using a von-Neumann common memory address bus (MAB) and memory data bus (MDB). They are considered the industry’s lowest power solution for 8- to 16-bit battery-powered measurement applications.

Even University researchers have jumped on the bandwagon. Kansas State University, for example, has recently developed a single-chip microtransceiver for use in energy harvesting radio technology destined for future Mars missions as well as other earthly applications like powering radios for remote wireless sensors. The low-power RF chip uses a silicon-on-sapphire CMOS process from Peregrine Semiconductor Corporation (www.peregrine-semi.com) and operates in the 390-450 MHz band with 100mW output. It includes an integrated transmitter and superheterodyne receiver with an off-chip IF filter. To date, University researchers have already produced proof-of-concept hardware for using the single-chip radio in energy harvesting applications.

Conclusion
With the continued drive toward more energy efficient devices—especially when it comes to wireless communications applications—industry is being challenged to identify new means of powering devices. Energy harvesting, and in particular RF energy harvesting, offers one viable solution. While it may be awhile before wireless devices powered through this method make their way to market, progress is being made. Ultra-low power electronic components will play a key role in moving this technology forward. Coupling these components with energy harvesting technology is today allowing applications that were once unthinkable, like a knee brace that generates power from walking. In the years ahead, this technology will likely be leveraged with other alternate energy solutions and things like better power delivery and power management, to create electronic products that are both cheaper and more ecologically friendly.

By Ed Sperling

Digital power—using digital feedback control rather than converting from analog to digital—is hardly a new concept. But something has changed in this market because it’s starting to receive renewed attention by more established companies.

Digital power falls into two main categories, one in the control world and the second in communications, where it has a richer history.

In the control sector, companies such as Silicon Laboratories and Zilker Labs (now part of Intersil) have been offering digital power components for several years. But the push toward lower power consumption across a device and a smaller bill of materials, as much for size as cost, are attracting new entrants such as Microchip.

“What’s been the norm in control power conversion is analog circuits with a digital assist,” said Bill Hutchins, product marketing manager at Microchip. “There are savings right there, but there’s more when you take a whole system view. Overall system efficiency increases and there are fewer parts in the bill of materials.”

Microchip sees opportunities in areas such as uninterruptible power supplies and in lighting. Digital control can simplify everything from designing light ballasts to the amount of power supplied to a rack of computer servers. “What this also does is decrease time to market,” said Hutchins.

At least part of the attraction is time to market for the full device, particularly when it comes to software programming. It’s easier to program software to work with digital parts than analog parts, which is why Intel has been developing a digital radio model. Justin Rattner, Intel’s chief technology officer, said the number of problems that can be solved digitally rather than in analog is enormous, which makes it far easier to utilize software and write software.

The deeper history of digital power is in communications, where all-digital communications were developed in the 1970s for a variety of commercial operations. The Fieldbus Foundation, a not-for-profit consortium of companies in the process automation industry, has been focused on improving accuracy in communication by eliminating digital to analog conversion.

This kind of technology has widespread applications. Portland General Electric, for example, used it last year to create a digital bus for communication, allowing it to easily to connect up to software for managing its customer base.

Whether digital power ever fully replaces analog in a number of these markets remains to be seen. But the attention it is getting these days is certainly rising, and players like Texas Instruments and Microchip are at least picking up incremental business in this space while the market weighs its options.

By John Blyler

Designing embedded systems in energy-sensitive environments requires both attention to power details and a system-level view of overall energy architectures. Successful designers must embrace both perspectives.

This isn’t easy. Most embedded hardware engineers are used to the fairly generous power offered by a wall socket or inexpensive traditional off-the-shelf batteries, where portability is a requirement.

But energy-sensitive embedded designs contain a time-dependency that many designers do not fully appreciate – one not associated directly the function of the battery. Instead, this time-dependency is related to the operation scenario of the application. More on this in a moment. First, let’s consider the power “pain points” that drive engineers to consider energy harvesting systems in the first place.

Pain points
A major pain point is the high cost associated with the use of wired power in any application for which traditional wall socket power is not readily available, such as wireless sensors in data acquisition devices for industrial processes, patient monitoring, remote data logging, agri-business and intelligent building energy controls.

In the past this problem was solved by using single-charge batteries, notes Steven C. Grady, vice president of marketing at Cymbet Corp. “However, the next pain point is having to deal with changing out batteries. The unknown time frame of battery failure and costs to change batteries has also been shown to be very expensive.”

This is where energy-harvesting techniques become attractive, because they can provide a relatively permanent source of energy. However, to qualify as a satisfactory solution, energy harvesting implementations must be on parity or even less cost to wired and battery solution. As Grady explains, the adage of ‘People go green, when it saves green ($)’ certainly applies to energy harvesting.

Other conditions make energy harvesting devices attractive. Sandip Kundu, professor at the University of Massachusetts in Amherst, Mass., says that in addition to being removed from typical power sources, energy scavenging is most attractive for portable devices that do not need large amounts of power and have low usage duty cycles. Low duty cycle of usage applications include food-tracking techniques that use smart labels that contain history of origin information, as well as routing and temperature data.

At the other end of the spectrum are energy scavenging devices used in the co-generation of power, such as with internal combustion engines and heat furnaces. Kundu notes that such cogeneration of power allows the design to combine techniques to improve overall efficiency, such as with the combination of a Sterling cycle engine and thermocouple-based electricity generator.

Servicing the Battery

The reason a designer would choose energy scavenging over a standard battery really boils down to cost and/or the constraints of serving a battery in the application, says Mark Buccini, microcontroller marketing director at Texas Instruments. He says that a simple solar calculator is a good example of the cost benefit of energy harvesters, because a solar cell is actually cheaper than a battery and can last for decades.

One of the best examples of the constraint imposed by servicing some battery-enabled applications is found in solar-powered satellites. Here’s where solar power scavenging really shines, Buccini says. “Solar power is abundant and the cost of replacing a battery in space is prohibitive.” Another more down-to-earth example of difficult-to-service battery applications would be implanted medical devices.

Even with multi-year battery life, most embedded applications eventually will need maintenance in the form of battery replacement. For example, low-cost systems such as underground water meters or tire pressure monitoring systems may require several hundreds of dollars in associated maintenance because they are hard to access.

Before jumping on the energy scavenging bandwagon, designers should heed the words of Jan Rabaey, Donald. O. Pederson Distinguished Professor at the University of California’s Berkeley Wireless Research Center. He says the size of the device dictates just how effectively it can scavenge energy. For example, most scavenging is a third-order factor of the volume of the node, although solar is a square of the node because it is a flat structure. “If you double the size of the device, you can roughly double the amount of energy you can scavenge,” he said.

Energy Storage is a Must

Almost all energy-harvesting scenarios require some sort of energy storage element or buffer. Even if the voltage and current requirements of an embedded application were so low as to be run directly on power captured or scavenged from the environment, such power would not flow in a constant way. The sun doesn’t shine all the time, or at least not on the same terrestrial spot. This means that some type of energy storage element is needed, if for no other reason than to provide a steady and predictable amount of power.

Storage elements or buffers are implemented in the form of a capacitor, standard rechargeable lithium battery, or a new technology like thin-film batteries (see Figure 1). What kind of energy storage is needed depends greatly on the application.

Some applications require power for only a very short period of time, as short as the RC time constant discharge rate of a capacitor. Other applications require relatively large amounts of power for an extended duration, which dictates the use of a traditional AA or a rechargeable lithium battery. Still other applications need the small footprint benefit of the capacitor and the low energy leakage advantage of a tradition battery. This is where the thin-film batteries are gaining acceptance, notes Adrian Valenzuela, product marketing engineer for ultra low-power MCUs at Texas Instruments.

Figure 1: Characteristics of typical energy storage options (Courtesy of TI)

Understanding the Dependency

It should be apparent that the type of energy storage needed to complement an energy harvesting approach is dependent upon the embedded application. Designers must determine the energy capture profile and compare it to the energy storage profile, both of which are functions of the operational scenario of the embedded application. The operational scenario captures dynamic duty cycle or the (often) non-period timeline of the embedded devices usage model.

What tools are available to help the system architect or designer balance energy harvesting and storage cycle that are dependent on the operational scenario of the application? Not many.

There are very-low-power microcontroller kits that help the designer manage power and energy storage. But robust software tools that model the system-level duty cycle given a particular embedded energy input and load output are not yet available. They will be soon, judging by the growing interest in energy harvesting technology.

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Want to meet most of the experts quoted in this story? Then be sure to attend the Design Automation Conference (DAC) Pavilion Panel, Power Scavenging: Waste Not, Want Not

Everyone talks about low-power designs, long battery life and the environmental effects of so much power consumption. However, the consumption of power is an ever-increasing need that must be faced. Are there alternatives to generating “small” amounts of power for low-power gadgets from really unconventional methods? Let the experts tell you where some of the hidden power is available and how they are harnessing it for some of the most complex applications.

Panelists:

Sandip Kundu – Univ. of Massachusetts, Amherst, Mass.

Steve Grady – Cymbet Corp., Elk River, Minn.

Mark Buccini – Texas Instruments, Inc., Dallas, Texas

Moderator: John Blyler, Chip Design magazine

Organizer: Yatin Trivedi, Synopsys, Inc.