By Ed Sperling
The number of factors required for an effective power model has far surpassed the capabilities of even the most detailed spreadsheet at 45nm and beyond. It has now entered the realm of complex databases and architectural tradeoffs, and those tradeoffs will become even more complex as 3D stacking takes root over the next 24 months.

The idea of modeling power is hardly new, but you wouldn’t know that comparing the current iterations side-by-side with the old methods. While there is still a need to understand worst-case scenarios to protect signal integrity, not to mention the other components on a chip, there is far more that needs to be considered in power modeling at advanced nodes than in the past.

“There are two issues that need to be solved,” said Ran Avinun, marketing group director for system design and verification at Cadence. “One is how to do this. The second is who owns the format. The methodology hasn’t been solved yet. When you tell the customer that we’ll compare our numbers with your back-end flow and libraries, that’s not good enough. It’s going to give me the data about the SoC or the ASIC, but that’s not enough. When customers look at power it’s what they measure in the lab. When they test the device it’s in a real environment with real software and the package. Today they don’t have a good way to test. It’s done with software and vectors, but it’s not really reflecting what the user will get.”

The second issue is understanding what parts of the system actually consume power. “Customers don’t know how to partition the power consumption of the ASIC vs. the overall system, so what they measure is the overall power. They don’t know how to partition those components and there is no good way to model that. We’re looking at the ASIC and die level, but they need to model the whole system,” Avinun said.

Moreover, for the system-level numbers to be used in a meaningful way at the architectural level they have to be relatively accurate. The shrinkage of components has made everything more susceptible to the effects of power, mechanical and thermal stress, electromagnetic interference, electromigration and noise (see fig. 1). Modeling power is now required. But even the simplest ideas such as power supplies are no longer simple.

Fig. 1. Source: Apache Design Solutions

“In the past we had two power supplies, one for the digital and one for the analog,” said Cornelia Golovanov, an EMI expert at LSI. “Now we have three or four analog power supplies in a small area, which makes the supplies very inductive. These are not well analyzed in the context of the whole system.”

Like anything else at advanced nodes, without adequate planning power supplies can be corrupted. Even maximum power, which used to be calculated in a worst-case scenario fashion once RTL was already synthesized, has become incredibly complex with multiple power islands, multiple modes, multiple cores and multiple voltages.

“With a power model ideally you want to cover all scenarios and all vectors,” Golovanov said. “But some of these have really long simulation points. It can take weeks at the end of the design cycle, and then you have to factor in the chip in the package on the PCB. There is no time for that.”

What’s in the model?
That’s where models fit in. Much attention has been paid to the different library approaches for defining power intent with the Unified Power Format (UPF) and the Common Power Format (CPF). The power model is a level above that, defining the power delivery network, signal integrity analysis, electromagnetic interference and compatibility (EMI/EMC) and the thermal effects of power, primarily in the form of dynamic and static leakage.

“In the past power models were simplistic in nature and deemed sufficient for the needs at that time,” said Aveek Sarkar, vice president of product engineering and support at Apache Design Solutions. “You could provide a single current and single capacitance and the result was your best guesswork. That all began to change in 2006 when we moved to 65nm. The package design could no longer be off the shelf. It’s now a competitive difference for companies and it can determine the price and performance of a system. Hence, an accurate model that represents the actual activity and parasitic profile of the chip is important off which you can base package and PCB decisions.”

Packaging has other issues, though. While a chip consumes current, the package and the PCB can act as an antenna for chip-generated noise, which results in EMI. It’s becoming necessary to extract an S-parameter model (scattered parameter) model for the package. Once that model is constructed, then a full system-level AC, DC, and time-domain analysis, then a full analysis can proceed using the power models of the chip, said Sarkar.

“Right now 40nm is mainstream,” he said. “At 22nm and 28nm electromigration gets very complicated. Since electromigration and leakage current can change very drastically with a temperature increase, we have to model the thermal profile of the chip–especially for a stacked die configuration.”

But there’s also a point where models can become useless. Looking at everything from a very high abstraction level is excellent for layout and functionality, but it can insert some very large errors into power models—sometimes as high as 300%, according to Cadence’s Avinun.

And there needs to be more consistency among models to make them useful. Frank Schirrmeister, director of product marketing for system level solutions at Synopsys, said the standards don’t yet exist because this is all so new.

“In TSMC’s reference flow 11, they characterize their libraries for low power and then make this all accessible for TLM 2.0 modeling,” Schirrmeister said. “Then you should be able to add up meaningful power numbers, even at the system level. Today this is all in the early stages. The different vendors have different formats. At some point it needs standardization.”

Standards needed
All of the major foundries are working on these kinds of models. In addition, Apache is working with the GSA on models for power. Those will become particularly useful in stacked die configurations, where thermal issues are not always intuitive. (See fig. 2)

Fig. 2. Source: Apache Design Solutions

None of this will get solved quickly. For one thing, power models generated by memory makers may be different than those generated by foundries and IP vendors, which is where standards will become important. But the first step is creating a dialog and generating tools that can provide visibility inside and SoC, and so far at least that seems to be happening.

By Pallab Chatterjee
Process scaling has normally been performed on a lithographic basis, but as processes dip below 32nm there are optimization options beyond the lithographic and area reduction.

The Common Platform Group and GlobalFoundries have added the tradeoffs of power and performance optimization in addition to area in their 28nm flows. TSMC uses a five-way optimization that also has area, power and performance as three of the points.

The enabler of HKMG (high k/metal gate) is the process enhancement that allows power optimization to take place. The process nodes of 90nm, 65nm, and 4Xnm were plagued with device leakage issues. These leakage issues create a pause in the operating voltage scaling of the circuits at 1.2-1.3v. The use of HKMG, in either a GF (gate first) or GL (gate last) process flow, allows for a primary reduction of the device leakage. The corresponding benefit of the reduced leakage is the ability to vary the threshold voltage (Vt) of both the P and N transistors, in the case of GlobalFoundries over a range of 300mv at 28nm. Since the Vt can be adjusted without corrupting the basic device operation, the operating voltage can be reduced while delivering the same device switching characteristics.

Both the GF and GL versions of the HKMG process support a standard “G” style logic optimized flow, an “LP” low-power optimized flow and an “HP” high-performance optimized flow. As the reduced process size can be multi-point optimized, it is possible to create a 28nm process that provides 2x the performance (freq*density) at the same power factor as a 40nm node. Additionally, a low-power optimization supports a 28nm process at 1.1v, producing a 49% increase in operating frequency while having a simultaneous 44% reduction in switching power.

The ability to now scale the Vt of the small devices and reduce the power supply gives new design flexibility at the 2Xnm nodes. The 28nm and 22nm flows can support multiple Vts in a single design and, correspondingly, different power supply levels in isolated islands. This level of control over the devices is reminiscent of the capabilities last seen in the 250nm+ nodes. Designers now can perform IP and cell level optimization for power and area based on design rule adjustments and device selection. For IP, differentiation in the rules can optimize SRAM, logic and analog/RF all with different Vts and operating voltages. This makes the block and SoC-level design power and performance optimized only if the design flow supports technology based optimization.

Most design flows for low power rely on gate power switching and a single Vt selection per block The 28nm flows have context sensitivity for all the physical design components. With the use of computational lithography solutions, and the symmetry requirements of double patterning, multiple sets of design rules are used to drive the function optimization. The support environment allows for multiple SRAM types (operating voltages, Vt, density, speed, etc.) to be built and dropped into blocks that may share a common power-gating control. In the 40nm to 90nm designs, these variations could not be combined.

The very small cell size and device pitch in 28nm and 22nm processes has created a need for new interconnect solutions. These new interconnect methods are needed to ensure the low power operation of the designs, as the interconnect is a major consumer of the device power. Most of the designs in these nodes utilize bump and in-die pads. At the 250nm through 45nm nodes, the bond pad size for bump bonds are still the traditional 110um size on a 150um pitch. At the 28nm and 22nm nodes, the bump bonds can be reduced to a 60um size on a 100um pitch. This reduction in size creates a minimized interconnect path for both power and signals, and drive the area based optimization aspects of the process.

Low power design in the 2Xnm nodes is now a full design/technology/lithography co-optimization task. The design workflows have to address both device characteristics and lithography variability to ensure any power factor design goals.

By David Lammers
The trends towards vertical transistors, non-silicon channel materials, and resistive RAMs promise to hold center stage at the 2010 IEEE International Electron Devices Meeting (IEDM), set to begin Dec. 6 in San Francisco, Calif. (www.ieee-iedm.org)

Taiwan Semiconductor Manufacturing Co. (TSMC, Hsinchu, Taiwan) will present a 22/20nm technology platform based on a FinFET architecture. The TSMC paper describes a full CMOS technology, complete with silicon germanium stressors, high-k/metal gate, and dual-epitaxy technology. TSMC said it demonstrated a 0.1µm2 SRAM cell, which operated at a 0.45V operating voltage (Vmin) with a 90 mV noise margin.

While TSMC is expected to shift from today’s planar transistors to the vertical FinFET devices at the 14nm generation in the 2015 time frame, the IEDM 22/20nm paper demonstrates that the world’s leading foundry has the FinFET manufacturing challenges well in hand. TSMC used 193nm immersion lithography to achieve NMOS and PMOS drive currents of 1200/1100 µA/µm respectively, at off-currents of 100 nA/µm.

Fig. 1: TSMC will unveil a complete FinFET-based 22/20nm CMOS logic technology at IEDM 2010. Electron microscope images show a cross-section of the vertical fin’s sidewall.

While creating 20nm gate-length vertical transistors is “demanding,” due to parasitic capacitances and other challenges, an abstract of the TSMC paper said the FinFET architecture allows continued scaling with good electrostatic control of the channel. To accomplish its scaling goals, TSMC turned a series of process technology knobs, including embedded SiGe to strain the PMOS channel, stress memorization techniques in the NMOS devices, an optimized contact edge stop layer (CESL), dual work functions, and both epitaxial silicon and boron-doped e-SiGe in the source and drain regions. Compared with planar transistors, the TSMC paper will describe much (100x) improved leakage from the source and drain regions, critical for low-power mobile systems.

Intel and IQE Inc. researchers will describe their latest advances with a FinFET architecture based on an InGaAs quantum well technology. At the 2009 IEDM, Intel described a surface-channel InGaAs FinFET. The quantum well InGaAs FinFET features fins, which are 35nm-wide and smaller, 5nm gate-to-drain and gate-to-source separations, and a high-k gate dielectric.

Intel and its research partner have been developing quantum-well compound devices as successors to silicon CMOS. The paper to be presented at the 2010 IEDM takes the InGaAs technology from a planar to a FinFET architecture, which delivers much-improved control of the channel compared with the planar devices described at the previous meetings. Also, the paper describes a high-k dielectric with a Tox of 20.5 Angstroms and good interface properties.

An InGaAs MOSFET will be presented by a team led by the University of Tokyo. The device features a 3.5nm channel, the smallest such device to be described thus far. The dual-gate device was created on a silicon substrate using wafer bonding.

Memories taking resistive turn
On the memory front, researchers from Intel and Micron Technology have developed a 25nm multi-level cell (MLC) NAND memory technology, with a cell size of 0.0028 µm2 – the smallest transistor now in production. An air gap was introduced between word lines to control the word line-to-word line capacitance and cell-to-cell interference.

The MLC device uses only 30 to 40 electrons per level, which requires advancements in the insulating tunnel oxide and the inter-poly dielectric in order to confine the charges. The cell has an asymmetric design, with a word line half pitch of 24.5nm and a 28.5nm half pitch in the bit line direction, allowing for insertion of the control gate between the floating gates. The technology is used for 64-Gbit NAND memories.

The authors will describe how the Intel-Micron team dealt with dopant fluctuations, structural bending, and other challenges presented at such small dimensions.

Fig. 2: Researchers from Intel and Micron Technology will describe the 25nm 64Gbit multi-level cell (MLC) NAND technology. The image shows the select gate and contacts in the bit line direction.

Resistive RAMs (RRAMs), which use a voltage to alter the resistive state of metal-based compounds, have emerged as a path to higher-density non-volatile memories once NAND flash scaling reaches its limit. A functional transition-metal-oxide resistive memory (TMO-RRAM) developed at the National Nano Device Laboratories in Taiwan has a record 9nm half-pitch, with a programming current of less than 1 µA, which compares with about 20 mA for phase-change memories. The researchers controlled the device’s resistivity by changing the chemical composition of the tungsten-oxide layer. They postulate that the memory’s change in resistance is due to the controlled movement of oxygen ions, with a monotonically varying ratio of oxygen and tungsten atoms.

The Taiwan laboratory’s research team includes Chinming Hu, a professor at the University of California, Berkeley. In an abstract of the paper, they said the “unexpectedly low” 1 µA current required to set and reset the RRAM cell makes it a promising candidate for low-power non-volatile memories.

The reported progress with exploratory RRAMs comes amid concerns about power consumption with the phase-change RAMs (PC-RAMs), which use heat to change the resistive state of a chalcogenide material. At IEDM, a team from the IBM/Macronix PCRAM Joint Project will describe a previously unknown failure mechanism for phase-change memories, apparently related to electromigration stemming from the polarity of the operating current.

At the high current densities required to change the state of the chalcogenide material, the researchers found that hole-induced electromigration occurs when current polarity is reversed. The paper claims that the phenomenon causes voids at the interface between the phase-change material and the bottom electrodes, limiting their cycling endurance by four orders of magnitude. The team also will discuss countermeasures to deal with the effect.

IBM researchers also will describe their latest-generation SOI-based embedded DRAM (eDRAM), enhanced with a high-k/metal gate technology. Big Blue claims eDRAM delivers several advantages over SRAM for large on-chip caches, including higher density, better soft error rates, and lower power consumption. The performance rivals SRAM speeds, with the SOI eDRAM delivering a sub-1.5ns latency and 2ns cycle time.

The 32nm eDRAM uses a deep trench capacitor with 25 percent higher capacitance and much less resistance than conventional memory stacks based on SiON/poly gate stacks. IBM said it use of a high-k/metal gate technology to reduce leakage and control the threshold voltage of 40 mV. IBM created a 32 Mbit array from cells measuring 0.39 µm2. The eDRAM is 3-4x smaller than a comparable SRAM, enabling a much-higher density on-chip cache, the abstract of the paper said.

By David Lammers
Over the past year, key technologists in the semiconductor industry have come around to believing that EUV lithography will be available for critical mask layers in the next three to five years. What is still up for debate is whether EUV will be cost-effective for low-power consumer SoCs. To penetrate that cost-sensitive market, EUV must overcoming hurdles presented by masks, damage to the collector optics, power consumption, and other costs of operation.

Memory makers, particularly the DRAM vendors with less-regular 2D structures than the more one-dimensional NAND devices, are fully on board the EUV bandwagon. However, several SoC makers such as Texas Instruments are on the fence. At the Sematech Litho Forum, TI’s Jim Blatchford, manager of lithography development and process simulation, argued that double and triple patterning with 193i scanners will better meet TI’s cost and performance objectives over the next five years.

TI seeks a 30% to 40% reduction in the node-to-node cost per die. For the 60nm routed pitch layers, corresponding to the 22/20 nm node, double patterning “is the only economically feasible solution,” Blatchford said in a detailed presentation on “lithonomics.” For the 14nm node, triple patterning will be required for the gate, contact, and metal 1 layers. “Double and triple patterning will be cost effective for die with a routed pitch of about 40nm,” he said.

“Triple patterning at the 44 nm pitch provides a 25% better cost reduction,” Blatchford said, adding that TI expects to use “aggressive” double patterning to meet its cost objectives at the 20nm node and “multi-patterning” at the 14nm node.

“The choice of lithography is an economic decision,” Blatchford said at the Sematech meeting. On the technical side, TI requires an overlay specification of 6nm to 10nm for triple patterning to work out. “We need another click in the overlay improvement from the scanner manufacturers,” Blatchford said.

Samsung expects EUV lithography to be less than half as expensive as double patterning. (Source: Samsung at the 2010 Sematech Litho Forum)

Most logic companies are cheering on the EUV technology to be ready for introduction at the 14nm node, giving designers more freedom from the restrictive design rules that would be required for extensive double patterning. Gary Patton, vice president at IBM’s semiconductor R&D center in Fishkill, N.Y., said “power is the new issue” facing device makers.

For IBM’s 15/14 nm technology, where the pitch will be about 80 nm, IBM may be forced to rely on double patterning, a variable light source, source-mask optimization, and continued imposition of design restrictions. If EUV were to be available for critical layers, Patton said IBM and its Fishkill partners could “relax the constraints on the light source and the mask, and avoid the need for design restrictions and double patterning.”

“At the 11 nm generation, we will certainly need EUV,” Patton said.

Jim Clifford, senior vice president of manufacturing at Qualcomm, also said the industry needs EUV to continue scaling, which he defined as increasing the transistor density within a set power budget. Costs are the main worry. “Is it going to be cheaper to scale if lithography is half the wafer cost?”

During a June 30th briefing at the ASML facility in Wilton, Conn., ASML vice president Noreen Harned outlined ASML’s efforts to get EUV ready. At its Netherlands facility, ASML has “completely built” one NXE 3100 pilot production scanner, with “another one right on its heels.” While Harned did not disclose which companies will get the six NXE 3100 systems, she did say that ASML had more than six companies queuing up to order the 3100 scanners. ASML decided to limit the 3100 to six units so it could move on the NXE 3300B volume production scanner by the first half of 2012. (ASML’s Harned describes the NXE 3100 as a pilot production machine that can be used for early production.)

Boosting the source power to >350 Watts is key to acceptable EUV wafer-per-hour throughput. (Source: ASML)

With IMEC as the expected first customer, other likely recipients of 3100 systems include Hynix, Intel, Samsung, Toshiba, and TSMC. One 3100 customer is expected to reach wafer-out status by the end of this year.

ASML installed the Cymer laser-produced plasma (LPP) source on the first 3100, but ASML is working with other source vendors. At the Wilton briefing, Harned announced that in early July ASML achieved the “first light” milestone on the first NXE 3100 platform, with a thermally controlled housing and mechanical dynamic stability. However, she said the source currently provides only 30-40% of the power ASML needs to achieve the 60 wph throughput target for the 3100 systems. The source power can be upgraded in-place, through various techniques, she said.

While Cymer appears to have the inside track at ASML thus far, Harned said the ASML EUV NXE platform was designed to be source neutral. Japan’s Gigaphoton Corp. is working on an LPP source that Harned said is similar to Cymer’s but which takes “a different approach to debris mitigation.” Among the discharge-produced plasma (DPP) vendors, Ushio Corp., working at its Aachen, Germany site, has made the most public progress so far. “All three have plans in place to meet the scanner needs. They all have credible roadmaps to intersect with high-volume production,” she said.

Asked about cost-of-ownership considerations, Harned said the lifetime of the collector optics is one concern. Unless mitigation efforts are improved, debris from the interaction of the laser and the tin droplets can damage the mirrors used to collect the source power. “The collector optics are the most-expensive consumable. Our target is a year, but it must be six months at the start. Fortunately, the collector optics are refurbishable,” she said.

Responding to a presentation by TSMC’s Burn Lin at the IEDM last December, in which Lin claimed that power consumption of the EUV scanners would make them impractical, Harned said ASML’s data shows that an EUV scanner and source will consume about 3X the power consumption of a 193 immersion scanner. “Power consumption is dominated by the source, and to a lesser extent by the need for vacuum operation. But it is about 3X, and that is a real measurement,” she said.

By Ed Sperling
ARM took a new tack in its war with Intel. The company is working on a Green Cloud Services project using the ARM architecture in conjunction with Nokia, IMEC, EPFL and the University of Cypress to create a 3D package with low-power processing. This is particularly interesting in light of gamers using Intel Atom-based servers.

Along the same power-saving lines, Actel introduced its power management solution for its SmartFusion mixed signal FPGA, complete with a reference design and a configurator for power sequencing and trimming. Given Actel’s focus on low power in its other chips, this isn’t all that surprising.

Also on the low-power front, Virage Logic introduced a big update of the open source GNU and Linux toolchains for its ARC processors, which will soon belong to Synopsys. That puts Synopsys firmly into the open source world, as well, with interesting implications.

Arteris joined forces with other EDA and IP vendors supporting TSMC Reference Flow 11, this time with network on chip interconnect IP. This is more like networking the industry on chip.

eSilicon will provide logistics services and production operations to Ember and Pixim. This is an interesting extension of supply chain expertise.

Mentor Graphics rolled out its commercial embedded Linux platform for Freescale, building on a strategic alliance the two had signed in April.

Mentor also won a couple deals with Mindtree for its Questa functional verification and with Autoliv for machine programming.

Both Synopsys and Cadence trumpeted successes with their products. Cadence global services enabled a 65nm TD-LTE baseband chip from Innofidei, a company with operations in Taiwan and Beijing. Synopsys, meanwhile, demonstrated interoperability between DesignWare IP for PCI Express 3.0. The company also awarded the Tenzing Norgay interoperability achievement award to IEEE-ISTO. We’re not sure what the famed Sherpa had to do with interoperability, but congrats.

By Ed Sperling
Complexity, less room for error and concern over adding any extra wires or circuits into chips because it may boost power consumption or affect the thermal profile are making it more difficult to tackle all the corners on an SoC.

The problem gets worse with mixed signal chips, where the corners are far less definable. And it gets even more complex when it comes to turning on and off multiple power islands inside an SoC because there are often surges when the power comes back on.

“At 90nm and 65nm, all you had to deal with were the process corners like fast-fast and fast-slow,” said Amit Gupta, CEO of Solido. “Then you had to deal with temperature variations and high-low voltages, but that was still only about 20 different combinations. Now it’s increasing to hundreds or even a thousand. You’ve got process corners and environmental variations.”

So what do you do about all of these? Let’s take a look.

Corner reduction
A corner describes a boundary, and most times blocks within chips, or the chips themselves, don’t ever cross that boundary. The emphasis is on most times, because much of the current thinking about how to deal with corners is with statistical averages. A massive voltage spike can still kill a chip, but most times it never gets that high.

To some extent this is based upon application. In a high-reliability chip like a missile guidance system or an industrial temperature sensor, all corners must be addressed and redundancy is required. In a consumer application addressing all the possible corners is unnecessary and redundancy consumes battery power.

Tom Quan, deputy director of design methodology at TSMC, said one solution is to describe these corners statistically, which he said is more consistent and practical. “Looking at it as a corner is a more pessimistic approach,” he said. “Most times you really are not pushing into the corners.”

Restrictive design rules help in this regard because they determine layouts and minimize variation.

“When you’re printing a line, as the process gets smaller printing the gate gets harder,” said Quan. “You have variation associated with it, so at 40nm you may actually print 42nm. If you draw with a bent poly the variation gets even larger. With restrictive design rules, you have fewer corners, less turns and more lines are straight. Printing is easier and variation is less.”

Once that is understood, the next best step is to measure, quantify and understand the margins that exist in current designs.

“Some of this is through timing analysis tools that consider multiple corners, environment variation, noise/IR drop, etc., but another important chunk is through silicon margin validation using at-speed test techniques, record keeping on failure bins, and analysis on failing parts to identify weak points in the existing margining process,” said an ARM spokesman. “Beyond this, there can be a benefit to using methods that take into account variation in transistors and wiring (e.g. various advanced OCV approaches, or even statistical analysis of critical circuitry). This can again give insight into the types of margin in a design, and can also be employed in adaptive methods that take advantage of the fact that most silicon is not worst case and has much more margin than exists in sign-off corners, and that this margin can be exploited for power or performance gains by adjusting voltage and frequency.”

The spokesman noted that some types of circuits can be modified using Razor-type approaches—speculative execution designed to push margin boundaries by adapting to slow-moving variation such as temperature or load changes while surviving fast-moving variation such as jitter or power glitches.

“Each of these obviously has a cost/risk/reward profile that needs to be evaluated for a given design and places certain requirements on the methodology and IP used, both at the physical and RTL level. Thinking outside the chip can also help—changes in external power supply requirements, for example, can affect the margins needed on-chip, and careful understanding of temperature can lead to cost or reliability improvements,” the spokesman said.

Accuracy, accuracy, accuracy
At least part of the challenge in dealing with corners is also understanding how the pieces that might affect that corner are behaving—with far greater accuracy than in the past.

“Accuracy is at the center of all of this,” said Juan Rey, senior engineering director for Calibre Engineering at Mentor Graphics. “There is far less guard-banding allowed at advanced designs.”

He noted that the allowable variability at 28nm and 22/20nm is about 1% to 2%. “It keeps getting more stringent.”

So does an understanding of exactly what corner cases need to be addressed. Solido’s Gupta said brute force approaches don’t work anymore. “You need to intelligently pick out the ones that matter and fix them,” he said. “There are two ways the foundries model variations, five corners and random variations. But if you do a true statistical distribution for local and random variations using a Monte Carlo analysis it’s very time-consuming.”

A better approach is understanding exactly what needs to be measured, how it will be measured, how those corners will be addressed and how to check for ramifications in other parts of a design once those fixes are made. And after that, it’s all statistics.

By Ed Sperling
Xilinx is developing a 3D architecture for its FPGAs and Actel has been approached by SoC makers to use its flash-based FPGA as a layer in a 3D IC stack. Both approaches could radically alter the fundamental equation about the tradeoffs between FPGAs and ASICs—particularly the power and performance overhead normally associated with programmable logic.

Xilinx declined to comment, but a half-dozen independent industry sources familiar with its efforts have confirmed the 3D development is well under way. Rich Kapusta, Actel’s vice president of marketing, applications and business development confirmed his company has been approached by SoC makers to use the company’s non-volatile flash-based FPGA as a layer in their 3D SoCs. He declined to comment further.

Getting 3D chips this kind of work done is anything but guaranteed. It’s complicated and there are lots of pitfalls, such as accessing RAM or logic across multiple die. Nevertheless, the implications of these developments are enormous. Because of the very regular and controlled structure of an FPGA, it is extremely well suited to defining where components can be placed on a chip. That makes it much easier to predict hot spots caused by putting two or more chips together—a problem that becomes particularly thorny when chip layers are developed by multiple vendors without knowledge of the thermal characteristics and layout of the other components.

3D stacking makes it far easier to bump up performance at advanced nodes using shorter wires while reducing power because it takes less power to achieve that performance over shorter distances. But getting this accomplished with SoCs has been particularly difficult. As a result, sources say the need for FPGA prototypes may change FPGAs into the end game rather than an in-between step.

Moreover, both moves also are expected to open huge markets, finally, for advanced EDA tools to work on complex FPGA designs, as well as third-party IP, processor cores from companies like ARM, MIPS and Virage Logic, and interconnect fabrics such as network on chip. They also can open up 3D to mainstream development. While companies such as IBM, Freescale, Qualcomm and Texas Instruments have been working on 3D chips for years—IBM started its R&D in this area almost a decade ago—most of that work has been a closely held secret because it is considered a competitive advantage for performance and power. FPGAs can quickly turn that into a less expensive option that may have more overhead than bottom-to-top 3D ASIC designs, but far less than 2D ASICs.

Issues in 3D
FPGAs can solve one of the biggest problems in 3D stacking, namely standards for placement of components. Without those standardized approaches there will likely be some ugly finger-pointing when two chips are put together.

“One of the problems that we see coming is who’s going to pay for a bad part,” said Andrew Yang, chairman and CEO of Apache Design Systems. “Testing may show that memory and logic are all good and that the die works, but when you put it together with another chip it may turn into a bad part. So you can say it’s good, and all your testing and verification may show that it is, but when it doesn’t work who pays?”

Yang said there is a need for far more analysis of the stacked die, measuring everything from heat and power to electrostatic discharge and signal integrity.

“We also need to understand what are the killer applications and what applications are not good for 3D,” he said. “The compelling value of 3D is shorter distance, which is the TSV promise. The challenge is in coupling chips together. In 2D you could shield high-speed signal transmissions. You get a cross-coupling effect with a TSV, so there is promise but there are also challenges.”

One of the big draws for 3D in general is the ability to re-use IP, which may come in the form of entire chips. That doesn’t work too well, however, when those chips were created for the best utilization of real estate on a 2D structure, where heat dissipation is relatively simple. In 3D, putting chips together can sandwich heat between die with no way to get it out of the chip.

“When you stack die you concentrate the heat,” said Carey Robertson, product marketing director for Calibre Design Solutions at Mentor Graphics. “That affects chip reliability, either short-term or long-term because they’re operating at temperatures they’re not expected to operate at. Circuits perform differently at 100C or 125C or 130C. At 130C it may affect the core, the timing, the signal integrity.”

While the overall heat of a chip hasn’t changed much, the more tightly everything is packed together the more difficult it is to cool. “When you stack them, you concentrate that heat even more,” Robertson said. “Potentially, when you move the wires closer together you can reduce resistance and IR drop. There would be a decrease in power and heat, but we have not seen enough of that yet to draw that conclusion.”

Under the covers, there are two technical ways to make this all possible, according to an ARM insider. “The first is for TSVs at similar pitch to solder bumps (about 50nm). This expands the capability of FPGAs and creates what amounts to multi-FPGA chips, as well as allowing for better-integrated flash, DRAM, and high-performance logic. The limited inter-chip bandwidth and power delivery, along with thermal issues, keep this as more of a cost dynamic – an extension to existing SiP approaches,” said the source. “The second answer is for high-density future TSVs, at a pitch of less than 5nm. These increase inter-chip bandwidth by a factor of 100 over the first solution and allow for some game-changing capability, including wide word high-speed off-chip memory access, combined FPGA/logic solutions, multi-die FPGA (greatly increased gate count) and so on. The reconfigurable aspect of FPGAs may also help solve the test and fault tolerance issues that are a very significant impediment to making tight pitch TSVs viable. Neither of these eliminates the crossover argument on power and performance, but they both have the potential to move it.”

Programming the future

Whether this effort ultimately succeeds is anyone’s guess. What is known is that a lot of resources are being marshaled into 3D stacking and a lot of hopes are being pinned on the back of efforts such as those from Xilinx and Actel’s partners.

Tom Quan, deputy director of design methodology at TSMC, said the great advantage of FPGAs is that they are very regular. “You can predict the thermal profile much better than with a mixed-signal SoC. Analog can be all over the map. But while the base array may be regular, in another corner of the chip you might have a USB so the outside of the chip might be hotter than the inside.”

Still, there was a lot of hype behind multi-chip modules in the 1990s and so far they have failed to materialize as a popular solution, largely because of cost. That could change as double patterning becomes the norm at 22/20nm and standard production costs rise, but visibility remains limited at that node.

At the very least, the moves by FPGA players are worth tracking, and a lot of companies are predicting major changes if these scenarios work. There are reasons FPGAs may hold more promise than multi-vendor or multi-generational SoCs. But there are still a lot of challenges to resolve before the total cost of development is known

Arteris, which makes network on chip technology, announced it is working with ARM to provide interoperability with ARM’s AMBA 4 bus specification. This is an interesting deal. On one hand, it expands ARM’s options with a faster and easier interconnect strategy. On the other, it moves Arteris deep inside ARM’s ecosystem, which includes 750 companies at last count. Many of those companies are on the short list for handheld devices such as smart phones—so far the leaders in low-power design—which now have to support more I/O options and communications protocols in a very narrow power budget. And not to be forgotten, until now most outsiders viewed these two companies as competitors.

Virage Logic rolled out new D-PHY and controllers for the 40nm low-power process across a number of standard interfaces such as the mobile industry processor interface (MIPI) and the camera serial interface receiver (CSI Rx). The company says power is down 80% and area is down 70%.

Mentor Graphics’ Calibre DFM is now qualified for TSMC’s 28nm processes. For anyone who thought the Roaring ’20s was something out of history, wait until you see the sounds coming out of the semiconductor design world over the next couple of nodes.

IAR Systems, which makes middleware for microcontrollers, threw its support behind Actel’s new SmartFusion chip. While this is a good deal for IAR—SmartFusion is the first chip to combine a programmable analog subsystem with an FPGA on a single low-power chip—it also gives Actel access to the industrial, medical and communications markets.

Synopsys completed its acquisition of CoWare. It now owns a company in which rival Cadence once invested, not to mention the vast majority of the commercial software prototyping market.

Cadence, meanwhile, acquired Taray, which makes tools to put FPGAs onto printed circuit boards. This is an interesting move for a couple reasons. First, it’s something of an acceptance that there are plenty of tools around for designing FPGAs and the most successful ones are those made by the FPGA vendors themselves. The reason? They’re cheap. Second, it moves Cadence out of the fray of whether FPGAs actually need more advanced tools made by Mentor and Synopsys and addresses a very real problem, namely putting the chips on a board. The main competition in this space will likely be Mentor Graphics.

Is this considered an adjacent market or a sharp left turn? TSMC broke ground on an LED lighting R&D center. The focus is LEDs and solar power, according to TSMC Chairman Morris Chang.

Actel set the FGPA market ablaze with its new SmartFusion device, which combines programmable analog with a complete microcontroller subsystem and an integrated programming environment, including tools. This is an interesting move, and it will be equally interesting to see how long it takes Actel’s top rivals to respond. Actel insiders, most of whom came from Xilinx and Altera, say the catch up period may be quite lengthy. They may have a bone to pick, but the low-power angle is definitely interesting. This also should grab some attention from the companies that have been developing multichip solutions because they don’t want to deal with integrating analog and digital.

Mentor Graphics announced its fiscal Q4 financials for the full year ending Jan. 31. Revenue was $802.7 million, up 2% from fiscal 2009. Non-GAAP earnings per share more than doubled to $0.47 per share, while the GAAP loss was $0.23 per share. That’s a lot better than a loss of $0.99 per share. For the fiscal Q4 Mentor revenues of $237.1 million, non-GAAP earnings per share of $.30, and GAAP earnings per share of $.39. As Mentor chairman and CEO Wally Rhines pointed out, “the electronics industry recovery seems to be well underway.” Break out the champagne—but don’t spend more than $8 a bottle or the corporate accounting department won’t approve it.

Synopsys bolstered the capabilities of its System Studio C/C++ analysis and simulation environment. The product now includes support for matrix and vector data types, which the company says significantly reduces coding and debugging efforts.

The Taiwanese earthquake earlier this week registered 6.4 and cost about 1.5 days in wafer movement from TSMC’s fabs in Tainan. This was a big earthquake, but the impact was slightly less near the Tainan fabs.

You have to wonder about Wall Street. Marvell beats estimates by $500,000 and the stock tumbles. According to analysts, the company didn’t beat estimates by enough. Isn’t the whole point to meet estimates?

Intel added the Atom processor to the networked small office/home office storage market. What’s interesting about this announcement isn’t Intel’s push into this market. It’s that there is now a dual-core version of Atom available. This should make for a nifty ultra-low power solution.

It was a very good week for low power engineering, although you have to do more than just scratch the surface to figure out why.

Mentor Graphics connected the dots on test and yield analysis, building on its own internal development in the yield space and coupling that with its LogicVision acquisition. The result is a new solution called Tessent, whose purpose is to sort through the rising mass of data in complex chips and simplify it. This could be a great step forward if it works as well as Mentor’s pitch, particularly in complex designs involving low-power techniques such as power islands and multiple power states at different voltages.

Virage Logic completed its acquisition of ARC International. This should prove to be an interesting marriage, in large part because the sum of the two is greater than the parts. Virage has the capability to target much broader markets than ARC did. It now has IP for the processor, memory and logic areas—and some very close ties to the major foundries. And all of this is a low-power play, which makes it particularly interesting should it ever decide to play alongside ARM and Intel’s Atom.

This proved to be a good week for indirect distribution channels, too. Mentor signed up Authorize Pty as a distributor for its FPGA and PCB products. Those kinds of products have to go through distribution because they’re low margin, high volume. That means direct sales are too expensive. This is how you come out on top down under.

And Synopsys announced that Arrow Electronics, another big distributor, cut its test development schedule by using automatic test pattern generation with multicore processing with TetraMAX. A lot of the stuff to design at the nano-design level can be applied to the macro world, as well. Consider this a case in point, and a nice potential growth market for EDA vendors.

Infineon and TSMC will jointly develop a 65nm embedded flash process for microcontrollers used in automobiles and chip cards. Embedded flash is also less susceptible to radiation from packaging than DRAM and draws lower power. That’s been Actel’s whole pitch for its Fusion and Igloo lines.

Also on the foundry side, Chartered Semiconductor’s shareholders approved ATIC’s bid to acquire the company. Our prediction: Globalfoundries becomes the leading edge foundry with the most advanced process technology and SOI substrates, Chartered comes in one or two nodes behind running on either SOI or bulk CMOS, and potentially another foundry is added for older process technology. That way equipment is bought once, processes are developed once, and everything is passed down the line.