Billions And Billions Sold
After years of talk, swarm computing appears to be gaining real momentum. The only question now is exactly what people mean by the word “swarm.”

The University of California at Berkeley will take an important stab at this with its new SWARM Lab, which will be officially uncorked next week. According to the announcement, “The Swarm Lab seeks to foster the creation and distribution of exciting applications for large swarms of sensors and actuators through the adoption of an open and universal platform.”

This concept has been through several iterations over the past couple of decades in technology. Both Sun and Novell introduced concepts in the 1990s that processors—and therefore computing tasks—could be shared by a variety of devices on a network. And several companies such as Dust Networks have introduced concepts, and in some cases products, involving thousands of sensors that can communicate with each other for purposes such as how much water or fertilizer is needed in a specific area of a field, or whether an earthquake has made a bridge or a building unsafe. There are even spy chips that can track movements across a vast area by waking up and communicating as a swarm.

The possibilities for this kind of effort are limitless, and so is the potential for seriously lowering the amount of power needed to gather complex information. Cell phones can be part of the swarm, to dictate traffic and road conditions. So can airplanes, cars—and even people.

Copper Vs. Silver
Imec and Kaneka have developed a manufacturing process for solar cells that uses copper instead of silver—something that has a long history in IC design and manufacturing.

At issue, in particular, are the heterojunction silicon solar cells. The two groups reported that using existing copper electroplating technology their cells were able to achieve a conversion efficiency of 21% using six-inch silicon substrates. Eliminating silver from the screen printing and replacing it with electroplated copper is a big deal and represents a major step forward in solar cell production using the same kinds of techniques that have made other ICs so inexpensive.

–Ed Sperling

By Ed Sperling
Memory is everywhere. In fact on most SoCs it accounts for the majority of the chip. But what exactly does it cost in terms of energy?

It all depends on where that memory actually is, but the general rule is that accessing memory requires about the same amount of energy as doing a complex computation, according to Paul Franzon, a professor of electrical and computer engineering at North Carolina State University.

In a presentation at the Berkeley Symposium on Energy Efficient Electronic Systems, Franzon detailed the energy costs of various functions on an SoC compared with a complex computation, which for decades has been the benchmark in computing devices. He said that I/O requires about the same energy as a complex computation, but energy storage requires more because it has to be turned on and off.

In the stacked die world, a TSV with ESD protection requires about three times as much energy as a TSV without ESD protection. And if communications is vertical rather than planar, there can be up to a 60% memory power savings.

So how much energy can be saved using a variety of techniques? Here are the breakdowns:

1. Shorter wires: 2% to 13%.
2. DRAM on logic: up to 38%.
3. Trading area for power: up to 20%
4. Heterogeneity: 15%+
5. Re-architecting the system: 5% to 60%.

Intel working with solar power and 3D stacking
Intel Labs rolled out a novel concept this week—a new CPU architecture that it claims will offer five times the energy efficiency of other Pentium-class processors while offering the ability to run off a postage-stamp sized solar cell.

What’s unique about this approach is that the CPU drops below 10 milliwatts when its workload is load, but can utilize Intel’s burst approach to add in more cores when necessary. Bursting is akin to on-chip virtualization, in that it allows a single application to utilize any available processing resources.

Even more intriguing, though, is Intel’s collaboration with Micron on the latter’s Hybrid Memory Cube, which it claims will add a seven-fold improvement in energy efficiency over DDR3. In case you wondered whether Intel was experimenting with 2.5D and 3D stacked die architectures, this should provide the answer. The HMC is a 3D stacked die package, which greatly improves density and speed by adding multiple layers of chips connected with through-silicon vias. That both shortens the distance and widens the data pipes, while simultaneously requiring less energy to drive signals.

Most researchers look at stacked die as the best way to cut power while also improving performance. The fact that Intel already is collaborating with Micron on this approach opens up some interesting possibilities for the processor giant’s move into the low-power SoC world.

Lower power capacitors and transistors
Researchers at UC Berkeley are using a ferroelectric layer—in this case lead-zirconate-titanate—on an insulator to cut the minimum voltage needed to store a charge in a capacitor. By using this combination the charge can actually be amplified, creating negative capacitance and solving one of the big issues with capacitors.

The initial work was done at 200 degrees Celsius, but new materials are expected to allow this principle to operate at room temperature. They’re also working on putting these materials into transistors, which is where things get even more interesting. One of the big challenges in dropping the voltage inside of SoCs is the minimum needed to safeguard function and prevent data loss through gates. It remains to be seen whether amplifying a charge can actually alter the minimum voltage, but it’s certainly worth a try.

Perhaps even more interesting is who else is funding this effort—Semiconductor Research Corp. and the Office of Naval Research.

–Ed Sperling

By Mike Demler
Minimizing on-chip power consumption continues to be one of the greatest challenges facing SoC designers. Everyone who owns a cell phone has undoubtedly seen the effect on limited battery life firsthand, but the impact on the unseen compute servers in “the cloud” is even more severe, making total electrical operating costs greater than the hardware expense, according to AMD Fellow Stephen Kosonocky.

In his presentation at the recent Hot Chips Conference, Kosonocky shared the experiences of the AMD Llano APU (accelerated processing unit) design team and how they addressed these challenges. By integrating a quad-core CPU architecture with a GPU in Llano, AMD was able to eliminate the power that would have been consumed by chip-to-chip I/O, and increase the bandwidth between the CPU and memory by 3X. To achieve this integration, the team implemented a complex power management scheme that required power gating (PG) and dynamic voltage/frequency scaling (DVFS) throughout the chip, and the combination of hardware policies with operating system (OS) software interaction.

While advances in circuit design and process scaling have enabled higher levels of integration in multi-core SoCs, Kosonocky showed that another limiting factor must now be considered—device packaging. The Llano APU requires six separate power supplies, including two high-current supplies. Designers can’t just add more supplies, he said, because multi-layer packaging is typically limited to only four power planes of thick high-current metal.

Aside from the cost impediment of adding more layers, package and chip designers simply run out of space. Each power layer requires its own decoupling capacitors to suppress supply noise. These chip capacitors are mounted on the package during manufacturing, and they consume available space with surrounding keep-out areas. Also, whenever another VDD is added the impact is multiplied by the increased share of package resources that must be dedicated to the VSS return path.

With packaging constraints now limiting power delivery to the number of cores that can be supported in an SoC, designers are looking to circumvent the problem by bringing external voltage regulators on-chip. Voltage regulators fall into two classes—switching circuits that use capacitors or inductors to boost and scale voltages, and linear regulators. Switching converters are generally preferred for their higher efficiency, but they require large amounts of capacitive or inductive energy storage. New solutions for power management will require more sophisticated analog circuit designs, possibly combined with additional process steps to build higher capacity passive components that are compatible with nanometer scale CMOS.

Intel, meanwhile, is investigating the use of inductive “buck converters” for on-chip voltage regulation, according to Donald Gardner, principal engineer at Intel Labs. Inductors are commonly integrated into RF ICs for wireless applications, but the current carrying capacity and inductive density of such structures is inadequate for power circuits. By adding magnetic materials to a standard CMOS process, engineers can increase the inductance of copper interconnect that is typically used in power busses. On-chip integration of a switching voltage regulator enables the use of circuit techniques to increase frequencies by more than 100 times over off-chip devices, which reduces the total inductance required by a factor of 1,000. This makes a single-chip solution feasible, and also offers the benefit of providing much finer resolution for dynamic frequency-voltage scaling, because the output of a buck converter is a function of its duty cycle.

The magnetic materials that Intel is evaluating include CoZrTa (cobalt, zirconium, tantalum) and NiFe (nickel-iron). Gardner said that regardless of the material, physics limits the gain in inductance that can be achieved by coupling a single layer of magnetic material to a wire to only two times, which is insufficient. Building structures that completely wrap wires in two magnetic layers, as his team is doing, is more complex but yields inductance gain that is much higher—theoretically up to the increase in the added material’s permeability.

Figure 1 - Researchers at Intel Labs have added magnetic materials to a 90nm CMOS process to build integrated switched-inductor voltage regulators. (source: “Integrated Inductors with Magnetic Materials for On-Chip Power Conversion”, 2011 Hot Chips Conference)

Striped inductors (rather than spirals) are the “Holy Grail” of voltage converters, said Gardner, because the application of a magnetic field during the deposition process inevitably creates orthogonal “hard” and “easy” axes. The hard axis has the property of saturating too quickly, but laying an elongated stripe in the easy direction takes full advantage of the increase in inductance. By wrapping a thick copper wire with two layers of CoZrTa, and sealing the sides with magnetic vias to prevent flux leakage, Intel has seen inductance increases of more than 30 times compared to air-core inductors. Intel’s research has progressed to the prototype stage, with a 48-core test chip containing 8 on-chip voltage regulators that the company has distributed to researchers for further investigation of new power management techniques.

It is unclear how much additional cost would be incurred by adding magnetic materials to a fabrication process, but capacitors are an intrinsic component of CMOS transistors and are commonly used for analog/mixed-signal circuits and on-chip power supply decoupling. Elad Alon, of the University of California’s Berkeley Wireless Research Center, has explored this alternative.

In SC (switched-capacitor) DC-DC converters, Alon noted that efficiency is limited by conductance density, or the amount of current (or power) delivered to a load for a given voltage. A DC-DC converter could be built as a replacement in the same area as a typical decoupling capacitor, which he estimated to occupy about 10% of a chip, so that no additional cost would be incurred if the regulators delivered at least 10 times the power density that their loads consumed. A typical processor was estimated to consume about 1 watt per square millimeter, but the payoff would be even higher in a lower power mobile device, which typically has 10 times lower power density. The Berkeley Wireless Research team implemented a 32nm CMOS SOI (silicon-on-insulator) test chip to test their concepts, achieving about 80% efficiency at 86 watts per square millimeter—close to the goal of 1 watt per square millimeter for a processor SoC.

Figure 2 - Researchers at UC Berkeley's Wireless Research Center have proposed incorporating switched-capacitor DC-DC converters in a 3D IC configuration, to supply power over tha area of a processor SoC. (source: “Fully Integrated Switched-Capacitor DC-DC Conversion”, 2011 Hot Chips Conference)

Higher capacitance per area yields higher efficiency in SC converters, and losses in the bottom plate parasitic set the maximum efficiency that can be achieved. The use of dense trench capacitors, such as in DRAMs, has been shown to offer the potential of about 90% SC regulator efficiency. Alon proposed that SC voltage regulators could be integrated into about 10% of the area of a DRAM die, and used to supply the power in a processor-memory 3D IC package. Alternatively, because the power regulator circuits can be built in older, less-expensive process technologies, a dedicated converter chip could be stacked and connected through TSVs (through-silicon vias) to distribute power over the entire area of a processor die.

By Ed Sperling

The Other 3D
Intel will roll out processors using tri-gate finFET transistors at 22nm, which it says will sharply lower the operating voltage, boost performance and reduce leakage.

Multigate transistors have been the subject of research for decades, most prominently at UC Berkeley, because they can be used to reduce current leakage and increase density. Going vertical allows more transistors to be loaded onto a piece of silicon, which in the case of a processor is particularly important because more transistors can translate into better performance.

Intel claims the new structures will improve performance by 37% at low voltages. The company said that makes it ideal for small handheld devices, a market where Intel has not done very well in the past primarily because its chips are considered power hogs next to those using ARM and MIPS cores. That statement alone caused ARM’s stock to plunge 7% as speculation mounted that Intel could replace ARM cores inside of some Apple devices. This is pure speculation, of course. Apple never talks about that stuff and Intel hasn’t even intimated that. ARM’s stock recovered rather quickly, too.

Still, most companies have shied away from finFETs because they are extremely difficult to manufacture and potentially can add to the design and manufacturing cost. Intel’s big advantage in this regard is that it still owns its own fabs and develops its own manufacturing process, something that is far too costly for all but a handful of chipmakers.

An alternative to 3D structures is ultra-thin body silicon on insulator, which is now being tested by IBM, STMicroelectronics, Soitec and Globalfoundries. And there is a possibility of mixing things up to include both. But the writing is on the wall—big changes are ahead, and Intel’s move is a first big step in that direction.

TI Pushes FRAM
Microcontrollers have been used for years to reduce power in devices through such developments as multispeed motor control and intelligent sensors, but the real battle of late has been inside the microcontrollers themselves. Companies in this sector have been playing leapfrog with power numbers taking priority over performance increases.

TI’s latest rollout includes an ultra-low-power FRAM, or ferroelectric RAM (previously written as FeRAM). This type of RAM uses 250 times less power than EEPROM-based microcontrollers, according to TI, and can be written at speeds of 100 times faster. FRAM is not a new technology. It was developed in the 1990s by Ramtron, and has been manufactured by Fujitsu for more than a decade.

Apparently major strides have been made in the pricing of this technology since then. TI’s microcontroller is priced at $1.20.

By Pallab Chatterjee
What will be the next major improvement that will cut power levels by an order of magnitude?

That question was the basis of a roundtable discussion at the recent ISSC conference. Current technology provides incremental improvements each year, but the next generation of electronic systems will require dramatic changes and innovation. This premise is based on Gene’s Law—that’s Gene Frantz of Texas Instruments—which states that the power efficiency for DSPs doubles every 18 months.

The roundtable consisted of six panelists from TSMC, Hitachi, STMicroelectronics, UCLA, Infineon, and an industry veteran consultant. The interactive challenges were posed by domain experts from Imec, the University of Tokyo and Stanford University. In addition, it was moderated by Jan Rabaey of the University of California at Berkeley.

Rabaey outlined some of the major challenges as the opening for the discussion. Among them:

1. The impact of technology scaling being reduced for new processes;
2. The impact of voltage scaling is reduced as a proportion of new power supply levels;
3. Getting control of the wasted energy in the systems, and
4. Identifying energy efficient design architectures.

At the core of the discussion were two main themes. First, new devices will be at the center. And second, there will need to be new new tools and methods to implement these next-generation designs. The device migration is toward 3D devices and low leakage devices and substrates such as Fully Depleted SOI (FDSOI) and FinFETs. These structures have the ability to provide consistency in performance despite lithographic challenges. Lithography is just one of the many aspects of variability that area plaguing sub-20nm process technology.

The manufacturing challenges for these new devices have yet to be determined, but the solutions to these challenges will help shape the product designs and architectures. Moreover, yield, predictability and power performance will drive the operating power supplies and determine how much power is wasted in the design through heat and inefficiency in current transfer.

As these devices operate in a different voltage and current modes with different sensitivities from standard planar (2D) devices, new models and device-level simulation tools are needed to capture their characteristics. Due to the small geometries and the resulting large density vs. device units scaling, new matrix-solving routines need to be created to solve the equations without causing the tools to slow down or fail to converge to a solution. This is already driving changes in EDA and CAD to support the devices. The capacity, capabilities and throughput of the current EDA tools is not sufficient to be able to address the new 3D device requirements and their associated block and system designs.

One of the major challenges is to address the guard-banding and safety factors in the designs that are wasting power. Current worst-case design optimization wastes operating power by helping to identify corners of the design space that may not be reachable in practicality, but require power to stay away from. The capacity and extent of verification software that can address multiple levels of the design will have to be created. One of the major issues is creating architectural tools that can help do power optimization as a driving design function rather than just as an analysis tool.

Key issues involving these tools is who will solve the fundamental problems—industry or academia—and whether it will become a viable business. For academia to put resources on solving the guard-banding and multi-level design issues it will need funding from the government (NSF) or industry to pay for the student and facilities needed to complete the work. If it is done by industry, companies need to know that when answers are found that customers will buy the products and that they will have some time advantage over competitors. With the scope and breadth of the new tools that are required, and the skyrocketing costs of building chips at these advanced node, the issue of, ‘Will there be enough people who need the results of the effort for the tool development to be a business,’was left open as one of the keys for addressing the next power plateau.

By Pallab Chatterjee
The theme for this years ISSCC (International Solid State Circuits Conference) is “Electronics for Healthy Living.” In addition to the new microprocessors, memory and data converter technologies, the focus and keynotes are directed toward health-care products.

The common theme between all the talks is that health-care is being driven by mobility, information flow, and power. The key to high quality data transfer is having enough power to complete it—either wired or wireless. The key to mobility is to have autonomous power for the devices for the duration of time that it does not impact the activity the user is involved with.

The keynotes cover the range of silicon’s impact on the health care. Medtronics is discussing the scope of implantable devices, the reliability, data transfer and the system architecture of the implanted and external portions of the system. IMEC then follows with a discussion of the invasion of specialized purpose sensors that are now possible, their inroads into health care and the creation and powering of body area networks. Samsung then speaks on a different twist for health care. Their angle is that the major cause of pollution is energy consumption and hence generation. The way to address this problem is through reducing energy use in the manufacturing process and in the design of devices that utilize less power and can take advantage of innovative packaging.

Following the keynotes is the inaugural Plenary RoundTable discussion on how to address the next 10X reduction in power. The discussion is is hosted by Jan Rabaey of UC Berkeley and features TSMC, Hitachi, STMicro, Infineon, IMEC and other senior experts from the semiconductor and university commnity. This challenge, encompassing process innovation, CAD, design flows for digital, RF, analog, and memory is one of the key drivers for the next generation of energy efficient electronics.

Energy efficiency has now earned its own session with Energy Efficient Digital, which will be detailing such projects as ultra-low-voltage standard cells that operate down to 62mv of supply. Other new technologies include a 28nm DSP from TI that can operate at 0.6V, and wireless sensor processor that utilizes only 10pJ per clock cycle.

The technology development sessions once again mix between high performance and low power. On the high-performance side, architectural design for Terahertz (300GHz to 3THz) imagers and associated device blocks—amplifiers/antennas are being shown. On the low-power side, a transceiver that can operate at 0.24nJ/b, and energy scavenging converters that are now up to 72% efficient and generating 95mv, will be presented.

Filling out the program are tutorials on ultra-low power digital design and a forum on ultra-low voltage VLSI for energy efficient ICs. These sessions are expecting large attendance as they are the dominant directions for the next decade.

The shift for the conference and the industry is dramatic. Historically over the past 40 years the conference has been the vehicle where the biggest and fastest semiconductors were debuted. These devices now have to share the spotlight with the smallest, highest-density and lowest-power devices. The show is focusing a lot more on architecture, device technology and the systems aspects rather than just circuit blocks. This focus accompanies the idea that SoCs are true systems, and the they need to be addressed as such with focus on function, performance, power and application. The body area network discussions and technology, which balance data transfer and power as the main tradeoffs, are representative of the future of the systems and IC discussions in the future.

By David Lammers
Since 1956, some of the top minds in information processing, including Claude Shannon and John von Neumann, have been pondering the problem of how to build reliable systems out of unreliable components. The communications industry embraced the challenge, and deployed error correction techniques to ensure that today’s most sensitive information is transmitted reliably over noisy transmission lines.

But in computing, the notion of probabilistic, error-resilient computing “never caught on,” said University of Illinois Professor Naresh Shanbhag. Probabilistic (stochastic) computing research is underway at Intel, IBM, and at a variety of academic research centers, including the University of Illinois, Stanford, and the University of California at Berkeley. And a new startup, Lyric Semiconductor (Cambridge, Mass.) has developed a chip architecture aimed at probability processing.

Jan Rabaey, a Berkeley professor and researcher at the Gigascale Systems Research Center, said the semiconductor industry faces a power-consumption wall that will require error-resilient computing. In a keynote speech at the recent International Symposium on Low Power Electronics and Design (ISLPED), Rabaey said, “Going forward, computing equals the cost of energy. The minimum energy point is set by the leakage in the transistors. From the 22nm generation and beyond, chip companies have not been able to scale the operating voltage. Going forward, capacitance may not go down that much. In fact, it may go up a bit.”

One path toward reducing power consumption is to reduce the supply voltage to a point where errors occur, but in small enough numbers that it is energy efficient to go back and correct the errors that matter. Rabaey said computer architects need to determine a “distribution of probabilistic outcomes” that would lead to what he calls a Probabilistic Turing Machine.

The power situation is exacerbated by the scaling-related issue of transistor variability, which also makes it more difficult and expensive to deliver deterministic outcomes.

“It might not be used for banks, but there are plenty of applications where customers don’t need absolute determinism,” Rabaey said. Among those applications are sensor networks, user interfaces, multimedia compression and graphics processing. A broad swath of RMS (recognition, mining, and synthesis) applications may only be doable, he argues, if designers consider the tradeoffs between power consumption and digital resolution, or accuracy.

“We can build machines to deal with lots of errors and still function,” Rabaey said, acknowledging that the approach would involve “a drastic redefinition in the way data is encoded and decoded.”

UC Berkeley's Jan Rabaey

“Some errors are catastrophic . We need an error model to brace against fatal errors. We need errors that have a smooth rolloff,” Rabaey said.

In stochastic computing, the system collects information from the application and from the circuit fabric. It determines which errors are bad and which are good, and provides a classification of errors. The result, proponents argue, is a system that is much more energy efficient.

Already, some MPUs include logic level techniques, such as error-detection blocks and shadow latches which sample the signal, detect an error, which, once detected, causes the processor to roll-back and recompute. “It is quite expensive in terms of power consumption if the chip has to roll back and recompute,” Shanbhag said. “That approach does not admit the possibility of having a benign error — all errors are equally bad. Today’s MPUs treat all errors as the same.”

Industry adoption slow
While MPU vendors are edging closer, using terms such as error-tolerant or self-healing processors, the concept of accepting that some errors may be tolerated may be a decade away from industry adoption.

Within the Gigascale center, ideas for error-resilient system architectures are various, including applications that could be served by an SoC with a super reliable core, supported by several reasonably reliable cores.

Before joining the faculty at Illinois, Shanbhag designed very high-speed digital subscriber line (VDSL) communications ICs at Bell Labs, incorporating the error-correction techniques that make it possible for consumers to bank on-line and trade stocks over noisy telecom networks. When he moved to academia in 1995, he began writing about computing applications that could would be well-served by similar error correcting architectures. However, after more than a decade of research, even relatively obvious applications such as PC graphics processing — where a few errant pixels usually would not be noticeable – remain based on deterministic techniques, he said.

Stochastic computing is the best way to keep power consumption under control, Shanbhag said, particularly for data-intensive applications such as extractions of features, models, and parameters, apps which draw upon huge databases in the process of serving decision makers.

Stochastic computation is based on a model that “allows one to achieve robustness and energy efficiency on SoCs.” Shanbhag is working on a P-encode acquisition filter for CDMA phones, a stochastic computing-based implementation that is two to three orders of magnitude more power efficient than conventional P encode acquisition filters.

Naresh Shanbhag

Lyric takes on Sudoku
So how does this all of this fit into the real world? Lyric Semiconductor emerged from stealth mode at the ISLPED 2010 conference last month, but the startup has kept much of its technology under wraps, partly because it attracted financial backing from DARPA.

Lyric applies statistical inference algorithms to a class of applications, mapping them onto its factor graph-based architecture. The approach creates an algorithmic description of statistical inferences, structures that can be used to derive conclusions from databases. The company has released its first chip, dedicated to error correction on flash memories, and is building a general purpose processor, said Theo Weber, a statistician at Lyric who spoke at the ISLPED conference in Austin last month.

“Lyric’s probability processing technology is designed from the ground up to efficiently consider many possible answers and find the most likely fit,” said Weber. Lyric’s factor graph approach estimates “how variables are connected, such as Sudoku-like problems. It infers meaning from imprecise data,” he said.

Lyric is working on a “GP5” general-purpose computer that Weber said is “1000 times more powerful than today’s processors.”

By Ed Sperling
Reducing the voltage in a system on chip is like turning down the water pressure on a home plumbing system. Pretty soon you find out that not all the faucets work properly because there isn’t enough pressure behind them.

While it’s vital to drop the voltage to boost battery life in mobile devices, not to mention reduce the overall power consumption in plug-in devices, the effects aren’t always well understood ahead of time. Power delivery changes with the voltage, and not always in anticipated ways. The problem is that chips are getting so complicated with power islands and multiple cores that it’s difficult to anticipate all the possible permutations up front.

“There are indeed challenges,” said Jan Rabaey, who heads the Wireless Research Center at the University of California at Berkeley. “Fluctuations in currents are an obvious result of turning domains on and off.”

In fact, the more abrupt the on/off states, the greater the likelihood of power delivery problems. “It’s like hitching a car to a trailer and taking off,” said Srikanth Jadcherla, group director for R&D in Synopsys’ verification group. “It doesn’t move the same way.”

And the more power islands, the worse those problems get. “This is something that’s well known in the cell phone industry,” said Bhanu Kapoor, head of Mimasic, a low-power consultancy. “They’ve got ARM cores, DSPs and memory blocks on a cell phone processor and they have a power supply for all of these different modules. But when you need to switch on a new block, the power supply has to deliver power to both. The power supply inductor tries to guard against any change, though, so it actually gives parts a lower voltage. That causes a temporary malfunction.”

Thinking about delivery in the architecture
While the effect of power islands have gotten the lion’s share of attention in low-power designs, they’re certainly not the only things that can go wrong. Failing to account for all possibilities up front can cause problems that grow as the chip moves from architecture to design and verification.

“Blocked frequencies and domains shutting off are a result of badly designed power distribution networks, which can happen even if you don’t have power islands,” said Rabaey. “By changing the resonant frequencies of the power network, you may see potential interplay with the clock frequency of the modules. But again, this is a generic problem with power distribution networks and has nothing to do with having power islands or not.”

Problems also grow as the semiconductor process shrinks. One of the problems in delivery of power at smaller geometries is the width of the wires themselves. While most engineers went through school with the assumption that electrons move through wires at a fairly constant rate–depending upon the type of wire rather than the thickness of that wire—that’s clearly not the case. IBM first began noticing earlier in the decade that resistance of smaller wires was increasing due to electron crashes with the atoms in the wires. Increased density meant more crashes.

The typical route for chipmakers is to engineer a solution to these kinds of problems. But that also increases the complexity and the price, because it usually means more parts. A 10-cent decoupling capacitor for a chip that is sold in quantities of 50 million adds $5 million to the overall price. And that doesn’t include the additional cost for assembly, which typically adds another nickel, or $2.5 million.

More parts also mean more complexity in the design. And more complexity means more things can go wrong.

“There was one chip we were developing where the clock gating domain produced a spike in current,” said one engineer, who asked not to be named. “We came up with logic to control the wake up, but when you shut down the clock it staggers it. As you’d expect, it got stuck. So we took off the clock-gating circuitry and there was a huge droop in voltage.”

In another real-world example, chip development was stopped the day before tapeout because there was insufficient decoupling capacitance. That affects timing. The chip arrived at tapeout two days later because a crew of engineers worked solidly for 36 hours to fix the problem. Needless to say, they wished the chip architects had figured this out ahead of time.

By John Blyler

Designing embedded systems in energy-sensitive environments requires both attention to power details and a system-level view of overall energy architectures. Successful designers must embrace both perspectives.

This isn’t easy. Most embedded hardware engineers are used to the fairly generous power offered by a wall socket or inexpensive traditional off-the-shelf batteries, where portability is a requirement.

But energy-sensitive embedded designs contain a time-dependency that many designers do not fully appreciate – one not associated directly the function of the battery. Instead, this time-dependency is related to the operation scenario of the application. More on this in a moment. First, let’s consider the power “pain points” that drive engineers to consider energy harvesting systems in the first place.

Pain points
A major pain point is the high cost associated with the use of wired power in any application for which traditional wall socket power is not readily available, such as wireless sensors in data acquisition devices for industrial processes, patient monitoring, remote data logging, agri-business and intelligent building energy controls.

In the past this problem was solved by using single-charge batteries, notes Steven C. Grady, vice president of marketing at Cymbet Corp. “However, the next pain point is having to deal with changing out batteries. The unknown time frame of battery failure and costs to change batteries has also been shown to be very expensive.”

This is where energy-harvesting techniques become attractive, because they can provide a relatively permanent source of energy. However, to qualify as a satisfactory solution, energy harvesting implementations must be on parity or even less cost to wired and battery solution. As Grady explains, the adage of ‘People go green, when it saves green ($)’ certainly applies to energy harvesting.

Other conditions make energy harvesting devices attractive. Sandip Kundu, professor at the University of Massachusetts in Amherst, Mass., says that in addition to being removed from typical power sources, energy scavenging is most attractive for portable devices that do not need large amounts of power and have low usage duty cycles. Low duty cycle of usage applications include food-tracking techniques that use smart labels that contain history of origin information, as well as routing and temperature data.

At the other end of the spectrum are energy scavenging devices used in the co-generation of power, such as with internal combustion engines and heat furnaces. Kundu notes that such cogeneration of power allows the design to combine techniques to improve overall efficiency, such as with the combination of a Sterling cycle engine and thermocouple-based electricity generator.

Servicing the Battery

The reason a designer would choose energy scavenging over a standard battery really boils down to cost and/or the constraints of serving a battery in the application, says Mark Buccini, microcontroller marketing director at Texas Instruments. He says that a simple solar calculator is a good example of the cost benefit of energy harvesters, because a solar cell is actually cheaper than a battery and can last for decades.

One of the best examples of the constraint imposed by servicing some battery-enabled applications is found in solar-powered satellites. Here’s where solar power scavenging really shines, Buccini says. “Solar power is abundant and the cost of replacing a battery in space is prohibitive.” Another more down-to-earth example of difficult-to-service battery applications would be implanted medical devices.

Even with multi-year battery life, most embedded applications eventually will need maintenance in the form of battery replacement. For example, low-cost systems such as underground water meters or tire pressure monitoring systems may require several hundreds of dollars in associated maintenance because they are hard to access.

Before jumping on the energy scavenging bandwagon, designers should heed the words of Jan Rabaey, Donald. O. Pederson Distinguished Professor at the University of California’s Berkeley Wireless Research Center. He says the size of the device dictates just how effectively it can scavenge energy. For example, most scavenging is a third-order factor of the volume of the node, although solar is a square of the node because it is a flat structure. “If you double the size of the device, you can roughly double the amount of energy you can scavenge,” he said.

Energy Storage is a Must

Almost all energy-harvesting scenarios require some sort of energy storage element or buffer. Even if the voltage and current requirements of an embedded application were so low as to be run directly on power captured or scavenged from the environment, such power would not flow in a constant way. The sun doesn’t shine all the time, or at least not on the same terrestrial spot. This means that some type of energy storage element is needed, if for no other reason than to provide a steady and predictable amount of power.

Storage elements or buffers are implemented in the form of a capacitor, standard rechargeable lithium battery, or a new technology like thin-film batteries (see Figure 1). What kind of energy storage is needed depends greatly on the application.

Some applications require power for only a very short period of time, as short as the RC time constant discharge rate of a capacitor. Other applications require relatively large amounts of power for an extended duration, which dictates the use of a traditional AA or a rechargeable lithium battery. Still other applications need the small footprint benefit of the capacitor and the low energy leakage advantage of a tradition battery. This is where the thin-film batteries are gaining acceptance, notes Adrian Valenzuela, product marketing engineer for ultra low-power MCUs at Texas Instruments.

Figure 1: Characteristics of typical energy storage options (Courtesy of TI)

Understanding the Dependency

It should be apparent that the type of energy storage needed to complement an energy harvesting approach is dependent upon the embedded application. Designers must determine the energy capture profile and compare it to the energy storage profile, both of which are functions of the operational scenario of the embedded application. The operational scenario captures dynamic duty cycle or the (often) non-period timeline of the embedded devices usage model.

What tools are available to help the system architect or designer balance energy harvesting and storage cycle that are dependent on the operational scenario of the application? Not many.

There are very-low-power microcontroller kits that help the designer manage power and energy storage. But robust software tools that model the system-level duty cycle given a particular embedded energy input and load output are not yet available. They will be soon, judging by the growing interest in energy harvesting technology.

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Want to meet most of the experts quoted in this story? Then be sure to attend the Design Automation Conference (DAC) Pavilion Panel, Power Scavenging: Waste Not, Want Not

Everyone talks about low-power designs, long battery life and the environmental effects of so much power consumption. However, the consumption of power is an ever-increasing need that must be faced. Are there alternatives to generating “small” amounts of power for low-power gadgets from really unconventional methods? Let the experts tell you where some of the hidden power is available and how they are harnessing it for some of the most complex applications.

Panelists:

Sandip Kundu – Univ. of Massachusetts, Amherst, Mass.

Steve Grady – Cymbet Corp., Elk River, Minn.

Mark Buccini – Texas Instruments, Inc., Dallas, Texas

Moderator: John Blyler, Chip Design magazine

Organizer: Yatin Trivedi, Synopsys, Inc.