Solar Cells Like LEDs
Researchers from the University of California at Berkeley have suggested and demonstrated a solar cell concept more like that of LEDs to allow solar cells to be able to emit light as well as absorb it—a counterintuitive concept because currently to produce the maximum amount of energy, solar cells are designed to absorb as much light from the Sun as possible.

Principal researcher and UC Berkeley professor of electrical engineering Eli Yablonovitch said, “What we demonstrated is that the better a solar cell is at emitting photons, the higher its voltage and the greater the efficiency it can produce.”

Yablonovitch and his colleagues have been trying to understand why there has been such a large gap between the theoretical limit of 33.5% and the limit that researchers have been able to achieve of 26%. As they worked, a “coherent picture emerged,” explained Owen Miller, a graduate student at UC Berkeley and a member of Yablonovitch’s group. They came across a relatively simple, if perhaps counterintuitive, solution based on a mathematical connection between absorption and emission of light. “Fundamentally, it’s because there’s a thermodynamic link between absorption and emission.”

Eli Yablonovitch and Owen Miller, who worked out the theory for the new solar cell efficiency. The monitor in the picture illustrates the new physics concept where increased light emission yields higher efficiency. Source: The Optical Society (OSA)

Designing solar cells to emit light—so that photons do not become “lost” within a cell—has the natural effect of increasing the voltage produced by the solar cell. If there is a solar cell that is a good emitter of light, it also makes it produce a higher voltage, which in turn increases the amount of electrical energy that can be harvested from the cell for each unit of sunlight.

The Berkeley research team will present its findings at the Conference on Lasers and Electro Optics (CLEO: 2012), to be held May 6-11 in San Jose, Calif.

Harvesting Energy with Nanotechnology
With 58% of the energy generated in the United States wasted as heat, researchers at Purdue University are working on a technique that uses nanotechnology to harvest energy from hot pipes or engine components to potentially recover energy wasted in factories, power plants and cars.  “If we could get just 10% back, that would allow us to reduce energy consumption and power plant emissions considerably,” said Yue Wu, a Purdue University assistant professor of chemical engineering.

The technique utilizes glass fibers coated with a thermoelectric material containing nanocrystals of lead telluride they developed, then exposed to heat in an annealing process to fuse the crystals together.  When the materials are heated on one side, electrons flow to the cooler side, generating an electrical current. These coated fibers could be used to create a solid-state cooling technology that does not require compressors and chemical refrigerants or even be woven into a fabric to make cooling garments. The fibers could be wrapped around industrial pipes in factories and power plants, as well as on car engines and automotive exhaust systems, to recapture much of the wasted energy. The ‘energy harvesting’ technology might dramatically reduce how much heat is lost, Wu said.

This image shows glass fibers coated with a thermoelectric material that generates electrical current when exposed to heat. The technology might be used to harvest energy from hot pipes or engine components, possibly representing a way to recover energy wasted in factories, power plants and cars. Source: Purdue University

These findings were detailed in a research paper appearing last month in the journal Nano Letters. The paper was written by Daxin Liang, a former Purdue exchange student from Jilin University in China; Purdue graduate students Scott Finefrock and Haoran Yang; and Wu.

Today’s high-performance thermoelectric materials are brittle. The devices are formed from large discs or blocks, which requires using a lot of material. But the new flexible devices would conform to the irregular shapes of engines and exhaust pipes while using a small fraction of the material required for conventional thermoelectric devices, researchers said.

“This approach yields the same level of performance as conventional thermoelectric materials but it requires the use of much less material, which leads to lower cost and is practical for mass production,” Wu said. Further, this approach promises a method that can be scaled up to industrial processes, making mass production feasible.

—Ann Steffora Mutschler

Nanoeconomics
Nano and green technology frequently go hand in hand, but so far the focus has been on the “gee whiz” factor rather than how much this stuff really costs. An ongoing study by Georgia Tech is about to change all of that.

Researchers Philip Shapira and Jan Youtie have launched a study into the impact of nanotechnologies on energy, the environment and safe drinking water, balancing efficiency gains and performance against the net energy, environmental, carbon and other costs associated with production.

This multidisciplinary research is a first, and it could pave the way for stripping away some of the hype about new technology and replacing it with cold hard facts. Among the areas under study are nano-enabled solar cells, nanogenerators using piezoelectric materials, energy storage, nano insulation and nano additives for fuel. This one should be interesting.

Brown Fields
Next time someone talks about greenhouse gases and the need for a better energy policy, blame fertilizer. UC Berkeley researchers analyzed the nitrous oxide in the atmosphere and discovered that fertilizer is a major contributing factor.

Nitrous oxide, aka laughing gas, is the same stuff that was used by dentists to make people forget about having cavities filled in their teeth. But in the atmosphere, nitrous oxide is the third-most potent greenhouse gas—after carbon dioxide and methane. Cows, auto exhaust, and coal-fired industrial facilities are still a problem, but so are the chemicals used to make crops and lawns grow faster and bigger.

The Cape Grim Baseline Air Pollution Station in Tasmania. Source: UC Berkeley.

The scientists came to their conclusions after analyzing air samples taken from Antarctic ice, called “fim” air, dating back to 1940 and air taken from an atmospheric monitoring station at Cape Grim in Tasmania, which has archived air since 1978. Nitrous oxide is clearly on the rise in the stratosphere, which no doubt will lead to some interesting changes in the application and content of fertilizer.

–Ed Sperling

Cheaper Fuel Cells
The idea of fuel cells has been around for more than a century. So why haven’t they taken off?

The main reason is cost. But chemists at UC Berkeley have come up with a possible solution, and it all has to do with the shape of catalysts. Inside of fuel cells, those catalysts are used to induce chemical reactions, but almost all of the reactions occur at the edges of the catalysts, as well as around defects.

Rather than limit the reactions to those locations, the chemists have changed the basic structure of the catalyst so that it’s all edges—basically a spiky structure with lots of extra edges on it. That, in turn, makes the fuel cells much more efficient and it reduces the amount of expensive material such as platinum that goes unused.

Source: University of California at Berkeley

Not Quite Graphene
The University of Helsinki in Finland is looking at new carbon structures—one of which is a cross between nanotubes and graphite, which they’re calling quasi-graphene.

Graphene, as you recall, is a one-atom-thick sheet of carbon. So far, this quasi-graphene only exists in supercomputer forecasts. The goal is to use it to store hydrogen.

The shape of things to come? Source: University of Helsinki.

–Ed Sperling

Billions And Billions Sold
After years of talk, swarm computing appears to be gaining real momentum. The only question now is exactly what people mean by the word “swarm.”

The University of California at Berkeley will take an important stab at this with its new SWARM Lab, which will be officially uncorked next week. According to the announcement, “The Swarm Lab seeks to foster the creation and distribution of exciting applications for large swarms of sensors and actuators through the adoption of an open and universal platform.”

This concept has been through several iterations over the past couple of decades in technology. Both Sun and Novell introduced concepts in the 1990s that processors—and therefore computing tasks—could be shared by a variety of devices on a network. And several companies such as Dust Networks have introduced concepts, and in some cases products, involving thousands of sensors that can communicate with each other for purposes such as how much water or fertilizer is needed in a specific area of a field, or whether an earthquake has made a bridge or a building unsafe. There are even spy chips that can track movements across a vast area by waking up and communicating as a swarm.

The possibilities for this kind of effort are limitless, and so is the potential for seriously lowering the amount of power needed to gather complex information. Cell phones can be part of the swarm, to dictate traffic and road conditions. So can airplanes, cars—and even people.

Copper Vs. Silver
Imec and Kaneka have developed a manufacturing process for solar cells that uses copper instead of silver—something that has a long history in IC design and manufacturing.

At issue, in particular, are the heterojunction silicon solar cells. The two groups reported that using existing copper electroplating technology their cells were able to achieve a conversion efficiency of 21% using six-inch silicon substrates. Eliminating silver from the screen printing and replacing it with electroplated copper is a big deal and represents a major step forward in solar cell production using the same kinds of techniques that have made other ICs so inexpensive.

–Ed Sperling

By Ed Sperling
Memory is everywhere. In fact on most SoCs it accounts for the majority of the chip. But what exactly does it cost in terms of energy?

It all depends on where that memory actually is, but the general rule is that accessing memory requires about the same amount of energy as doing a complex computation, according to Paul Franzon, a professor of electrical and computer engineering at North Carolina State University.

In a presentation at the Berkeley Symposium on Energy Efficient Electronic Systems, Franzon detailed the energy costs of various functions on an SoC compared with a complex computation, which for decades has been the benchmark in computing devices. He said that I/O requires about the same energy as a complex computation, but energy storage requires more because it has to be turned on and off.

In the stacked die world, a TSV with ESD protection requires about three times as much energy as a TSV without ESD protection. And if communications is vertical rather than planar, there can be up to a 60% memory power savings.

So how much energy can be saved using a variety of techniques? Here are the breakdowns:

1. Shorter wires: 2% to 13%.
2. DRAM on logic: up to 38%.
3. Trading area for power: up to 20%
4. Heterogeneity: 15%+
5. Re-architecting the system: 5% to 60%.

Intel working with solar power and 3D stacking
Intel Labs rolled out a novel concept this week—a new CPU architecture that it claims will offer five times the energy efficiency of other Pentium-class processors while offering the ability to run off a postage-stamp sized solar cell.

What’s unique about this approach is that the CPU drops below 10 milliwatts when its workload is load, but can utilize Intel’s burst approach to add in more cores when necessary. Bursting is akin to on-chip virtualization, in that it allows a single application to utilize any available processing resources.

Even more intriguing, though, is Intel’s collaboration with Micron on the latter’s Hybrid Memory Cube, which it claims will add a seven-fold improvement in energy efficiency over DDR3. In case you wondered whether Intel was experimenting with 2.5D and 3D stacked die architectures, this should provide the answer. The HMC is a 3D stacked die package, which greatly improves density and speed by adding multiple layers of chips connected with through-silicon vias. That both shortens the distance and widens the data pipes, while simultaneously requiring less energy to drive signals.

Most researchers look at stacked die as the best way to cut power while also improving performance. The fact that Intel already is collaborating with Micron on this approach opens up some interesting possibilities for the processor giant’s move into the low-power SoC world.

Lower power capacitors and transistors
Researchers at UC Berkeley are using a ferroelectric layer—in this case lead-zirconate-titanate—on an insulator to cut the minimum voltage needed to store a charge in a capacitor. By using this combination the charge can actually be amplified, creating negative capacitance and solving one of the big issues with capacitors.

The initial work was done at 200 degrees Celsius, but new materials are expected to allow this principle to operate at room temperature. They’re also working on putting these materials into transistors, which is where things get even more interesting. One of the big challenges in dropping the voltage inside of SoCs is the minimum needed to safeguard function and prevent data loss through gates. It remains to be seen whether amplifying a charge can actually alter the minimum voltage, but it’s certainly worth a try.

Perhaps even more interesting is who else is funding this effort—Semiconductor Research Corp. and the Office of Naval Research.

–Ed Sperling

By Mike Demler
Minimizing on-chip power consumption continues to be one of the greatest challenges facing SoC designers. Everyone who owns a cell phone has undoubtedly seen the effect on limited battery life firsthand, but the impact on the unseen compute servers in “the cloud” is even more severe, making total electrical operating costs greater than the hardware expense, according to AMD Fellow Stephen Kosonocky.

In his presentation at the recent Hot Chips Conference, Kosonocky shared the experiences of the AMD Llano APU (accelerated processing unit) design team and how they addressed these challenges. By integrating a quad-core CPU architecture with a GPU in Llano, AMD was able to eliminate the power that would have been consumed by chip-to-chip I/O, and increase the bandwidth between the CPU and memory by 3X. To achieve this integration, the team implemented a complex power management scheme that required power gating (PG) and dynamic voltage/frequency scaling (DVFS) throughout the chip, and the combination of hardware policies with operating system (OS) software interaction.

While advances in circuit design and process scaling have enabled higher levels of integration in multi-core SoCs, Kosonocky showed that another limiting factor must now be considered—device packaging. The Llano APU requires six separate power supplies, including two high-current supplies. Designers can’t just add more supplies, he said, because multi-layer packaging is typically limited to only four power planes of thick high-current metal.

Aside from the cost impediment of adding more layers, package and chip designers simply run out of space. Each power layer requires its own decoupling capacitors to suppress supply noise. These chip capacitors are mounted on the package during manufacturing, and they consume available space with surrounding keep-out areas. Also, whenever another VDD is added the impact is multiplied by the increased share of package resources that must be dedicated to the VSS return path.

With packaging constraints now limiting power delivery to the number of cores that can be supported in an SoC, designers are looking to circumvent the problem by bringing external voltage regulators on-chip. Voltage regulators fall into two classes—switching circuits that use capacitors or inductors to boost and scale voltages, and linear regulators. Switching converters are generally preferred for their higher efficiency, but they require large amounts of capacitive or inductive energy storage. New solutions for power management will require more sophisticated analog circuit designs, possibly combined with additional process steps to build higher capacity passive components that are compatible with nanometer scale CMOS.

Intel, meanwhile, is investigating the use of inductive “buck converters” for on-chip voltage regulation, according to Donald Gardner, principal engineer at Intel Labs. Inductors are commonly integrated into RF ICs for wireless applications, but the current carrying capacity and inductive density of such structures is inadequate for power circuits. By adding magnetic materials to a standard CMOS process, engineers can increase the inductance of copper interconnect that is typically used in power busses. On-chip integration of a switching voltage regulator enables the use of circuit techniques to increase frequencies by more than 100 times over off-chip devices, which reduces the total inductance required by a factor of 1,000. This makes a single-chip solution feasible, and also offers the benefit of providing much finer resolution for dynamic frequency-voltage scaling, because the output of a buck converter is a function of its duty cycle.

The magnetic materials that Intel is evaluating include CoZrTa (cobalt, zirconium, tantalum) and NiFe (nickel-iron). Gardner said that regardless of the material, physics limits the gain in inductance that can be achieved by coupling a single layer of magnetic material to a wire to only two times, which is insufficient. Building structures that completely wrap wires in two magnetic layers, as his team is doing, is more complex but yields inductance gain that is much higher—theoretically up to the increase in the added material’s permeability.

Figure 1 - Researchers at Intel Labs have added magnetic materials to a 90nm CMOS process to build integrated switched-inductor voltage regulators. (source: “Integrated Inductors with Magnetic Materials for On-Chip Power Conversion”, 2011 Hot Chips Conference)

Striped inductors (rather than spirals) are the “Holy Grail” of voltage converters, said Gardner, because the application of a magnetic field during the deposition process inevitably creates orthogonal “hard” and “easy” axes. The hard axis has the property of saturating too quickly, but laying an elongated stripe in the easy direction takes full advantage of the increase in inductance. By wrapping a thick copper wire with two layers of CoZrTa, and sealing the sides with magnetic vias to prevent flux leakage, Intel has seen inductance increases of more than 30 times compared to air-core inductors. Intel’s research has progressed to the prototype stage, with a 48-core test chip containing 8 on-chip voltage regulators that the company has distributed to researchers for further investigation of new power management techniques.

It is unclear how much additional cost would be incurred by adding magnetic materials to a fabrication process, but capacitors are an intrinsic component of CMOS transistors and are commonly used for analog/mixed-signal circuits and on-chip power supply decoupling. Elad Alon, of the University of California’s Berkeley Wireless Research Center, has explored this alternative.

In SC (switched-capacitor) DC-DC converters, Alon noted that efficiency is limited by conductance density, or the amount of current (or power) delivered to a load for a given voltage. A DC-DC converter could be built as a replacement in the same area as a typical decoupling capacitor, which he estimated to occupy about 10% of a chip, so that no additional cost would be incurred if the regulators delivered at least 10 times the power density that their loads consumed. A typical processor was estimated to consume about 1 watt per square millimeter, but the payoff would be even higher in a lower power mobile device, which typically has 10 times lower power density. The Berkeley Wireless Research team implemented a 32nm CMOS SOI (silicon-on-insulator) test chip to test their concepts, achieving about 80% efficiency at 86 watts per square millimeter—close to the goal of 1 watt per square millimeter for a processor SoC.

Figure 2 - Researchers at UC Berkeley's Wireless Research Center have proposed incorporating switched-capacitor DC-DC converters in a 3D IC configuration, to supply power over tha area of a processor SoC. (source: “Fully Integrated Switched-Capacitor DC-DC Conversion”, 2011 Hot Chips Conference)

Higher capacitance per area yields higher efficiency in SC converters, and losses in the bottom plate parasitic set the maximum efficiency that can be achieved. The use of dense trench capacitors, such as in DRAMs, has been shown to offer the potential of about 90% SC regulator efficiency. Alon proposed that SC voltage regulators could be integrated into about 10% of the area of a DRAM die, and used to supply the power in a processor-memory 3D IC package. Alternatively, because the power regulator circuits can be built in older, less-expensive process technologies, a dedicated converter chip could be stacked and connected through TSVs (through-silicon vias) to distribute power over the entire area of a processor die.

By Ed Sperling

The Other 3D
Intel will roll out processors using tri-gate finFET transistors at 22nm, which it says will sharply lower the operating voltage, boost performance and reduce leakage.

Multigate transistors have been the subject of research for decades, most prominently at UC Berkeley, because they can be used to reduce current leakage and increase density. Going vertical allows more transistors to be loaded onto a piece of silicon, which in the case of a processor is particularly important because more transistors can translate into better performance.

Intel claims the new structures will improve performance by 37% at low voltages. The company said that makes it ideal for small handheld devices, a market where Intel has not done very well in the past primarily because its chips are considered power hogs next to those using ARM and MIPS cores. That statement alone caused ARM’s stock to plunge 7% as speculation mounted that Intel could replace ARM cores inside of some Apple devices. This is pure speculation, of course. Apple never talks about that stuff and Intel hasn’t even intimated that. ARM’s stock recovered rather quickly, too.

Still, most companies have shied away from finFETs because they are extremely difficult to manufacture and potentially can add to the design and manufacturing cost. Intel’s big advantage in this regard is that it still owns its own fabs and develops its own manufacturing process, something that is far too costly for all but a handful of chipmakers.

An alternative to 3D structures is ultra-thin body silicon on insulator, which is now being tested by IBM, STMicroelectronics, Soitec and Globalfoundries. And there is a possibility of mixing things up to include both. But the writing is on the wall—big changes are ahead, and Intel’s move is a first big step in that direction.

TI Pushes FRAM
Microcontrollers have been used for years to reduce power in devices through such developments as multispeed motor control and intelligent sensors, but the real battle of late has been inside the microcontrollers themselves. Companies in this sector have been playing leapfrog with power numbers taking priority over performance increases.

TI’s latest rollout includes an ultra-low-power FRAM, or ferroelectric RAM (previously written as FeRAM). This type of RAM uses 250 times less power than EEPROM-based microcontrollers, according to TI, and can be written at speeds of 100 times faster. FRAM is not a new technology. It was developed in the 1990s by Ramtron, and has been manufactured by Fujitsu for more than a decade.

Apparently major strides have been made in the pricing of this technology since then. TI’s microcontroller is priced at $1.20.

By Pallab Chatterjee
What will be the next major improvement that will cut power levels by an order of magnitude?

That question was the basis of a roundtable discussion at the recent ISSC conference. Current technology provides incremental improvements each year, but the next generation of electronic systems will require dramatic changes and innovation. This premise is based on Gene’s Law—that’s Gene Frantz of Texas Instruments—which states that the power efficiency for DSPs doubles every 18 months.

The roundtable consisted of six panelists from TSMC, Hitachi, STMicroelectronics, UCLA, Infineon, and an industry veteran consultant. The interactive challenges were posed by domain experts from Imec, the University of Tokyo and Stanford University. In addition, it was moderated by Jan Rabaey of the University of California at Berkeley.

Rabaey outlined some of the major challenges as the opening for the discussion. Among them:

1. The impact of technology scaling being reduced for new processes;
2. The impact of voltage scaling is reduced as a proportion of new power supply levels;
3. Getting control of the wasted energy in the systems, and
4. Identifying energy efficient design architectures.

At the core of the discussion were two main themes. First, new devices will be at the center. And second, there will need to be new new tools and methods to implement these next-generation designs. The device migration is toward 3D devices and low leakage devices and substrates such as Fully Depleted SOI (FDSOI) and FinFETs. These structures have the ability to provide consistency in performance despite lithographic challenges. Lithography is just one of the many aspects of variability that area plaguing sub-20nm process technology.

The manufacturing challenges for these new devices have yet to be determined, but the solutions to these challenges will help shape the product designs and architectures. Moreover, yield, predictability and power performance will drive the operating power supplies and determine how much power is wasted in the design through heat and inefficiency in current transfer.

As these devices operate in a different voltage and current modes with different sensitivities from standard planar (2D) devices, new models and device-level simulation tools are needed to capture their characteristics. Due to the small geometries and the resulting large density vs. device units scaling, new matrix-solving routines need to be created to solve the equations without causing the tools to slow down or fail to converge to a solution. This is already driving changes in EDA and CAD to support the devices. The capacity, capabilities and throughput of the current EDA tools is not sufficient to be able to address the new 3D device requirements and their associated block and system designs.

One of the major challenges is to address the guard-banding and safety factors in the designs that are wasting power. Current worst-case design optimization wastes operating power by helping to identify corners of the design space that may not be reachable in practicality, but require power to stay away from. The capacity and extent of verification software that can address multiple levels of the design will have to be created. One of the major issues is creating architectural tools that can help do power optimization as a driving design function rather than just as an analysis tool.

Key issues involving these tools is who will solve the fundamental problems—industry or academia—and whether it will become a viable business. For academia to put resources on solving the guard-banding and multi-level design issues it will need funding from the government (NSF) or industry to pay for the student and facilities needed to complete the work. If it is done by industry, companies need to know that when answers are found that customers will buy the products and that they will have some time advantage over competitors. With the scope and breadth of the new tools that are required, and the skyrocketing costs of building chips at these advanced node, the issue of, ‘Will there be enough people who need the results of the effort for the tool development to be a business,’was left open as one of the keys for addressing the next power plateau.

By Pallab Chatterjee
The theme for this years ISSCC (International Solid State Circuits Conference) is “Electronics for Healthy Living.” In addition to the new microprocessors, memory and data converter technologies, the focus and keynotes are directed toward health-care products.

The common theme between all the talks is that health-care is being driven by mobility, information flow, and power. The key to high quality data transfer is having enough power to complete it—either wired or wireless. The key to mobility is to have autonomous power for the devices for the duration of time that it does not impact the activity the user is involved with.

The keynotes cover the range of silicon’s impact on the health care. Medtronics is discussing the scope of implantable devices, the reliability, data transfer and the system architecture of the implanted and external portions of the system. IMEC then follows with a discussion of the invasion of specialized purpose sensors that are now possible, their inroads into health care and the creation and powering of body area networks. Samsung then speaks on a different twist for health care. Their angle is that the major cause of pollution is energy consumption and hence generation. The way to address this problem is through reducing energy use in the manufacturing process and in the design of devices that utilize less power and can take advantage of innovative packaging.

Following the keynotes is the inaugural Plenary RoundTable discussion on how to address the next 10X reduction in power. The discussion is is hosted by Jan Rabaey of UC Berkeley and features TSMC, Hitachi, STMicro, Infineon, IMEC and other senior experts from the semiconductor and university commnity. This challenge, encompassing process innovation, CAD, design flows for digital, RF, analog, and memory is one of the key drivers for the next generation of energy efficient electronics.

Energy efficiency has now earned its own session with Energy Efficient Digital, which will be detailing such projects as ultra-low-voltage standard cells that operate down to 62mv of supply. Other new technologies include a 28nm DSP from TI that can operate at 0.6V, and wireless sensor processor that utilizes only 10pJ per clock cycle.

The technology development sessions once again mix between high performance and low power. On the high-performance side, architectural design for Terahertz (300GHz to 3THz) imagers and associated device blocks—amplifiers/antennas are being shown. On the low-power side, a transceiver that can operate at 0.24nJ/b, and energy scavenging converters that are now up to 72% efficient and generating 95mv, will be presented.

Filling out the program are tutorials on ultra-low power digital design and a forum on ultra-low voltage VLSI for energy efficient ICs. These sessions are expecting large attendance as they are the dominant directions for the next decade.

The shift for the conference and the industry is dramatic. Historically over the past 40 years the conference has been the vehicle where the biggest and fastest semiconductors were debuted. These devices now have to share the spotlight with the smallest, highest-density and lowest-power devices. The show is focusing a lot more on architecture, device technology and the systems aspects rather than just circuit blocks. This focus accompanies the idea that SoCs are true systems, and the they need to be addressed as such with focus on function, performance, power and application. The body area network discussions and technology, which balance data transfer and power as the main tradeoffs, are representative of the future of the systems and IC discussions in the future.