By David Lammers
Since 1956, some of the top minds in information processing, including Claude Shannon and John von Neumann, have been pondering the problem of how to build reliable systems out of unreliable components. The communications industry embraced the challenge, and deployed error correction techniques to ensure that today’s most sensitive information is transmitted reliably over noisy transmission lines.

But in computing, the notion of probabilistic, error-resilient computing “never caught on,” said University of Illinois Professor Naresh Shanbhag. Probabilistic (stochastic) computing research is underway at Intel, IBM, and at a variety of academic research centers, including the University of Illinois, Stanford, and the University of California at Berkeley. And a new startup, Lyric Semiconductor (Cambridge, Mass.) has developed a chip architecture aimed at probability processing.

Jan Rabaey, a Berkeley professor and researcher at the Gigascale Systems Research Center, said the semiconductor industry faces a power-consumption wall that will require error-resilient computing. In a keynote speech at the recent International Symposium on Low Power Electronics and Design (ISLPED), Rabaey said, “Going forward, computing equals the cost of energy. The minimum energy point is set by the leakage in the transistors. From the 22nm generation and beyond, chip companies have not been able to scale the operating voltage. Going forward, capacitance may not go down that much. In fact, it may go up a bit.”

One path toward reducing power consumption is to reduce the supply voltage to a point where errors occur, but in small enough numbers that it is energy efficient to go back and correct the errors that matter. Rabaey said computer architects need to determine a “distribution of probabilistic outcomes” that would lead to what he calls a Probabilistic Turing Machine.

The power situation is exacerbated by the scaling-related issue of transistor variability, which also makes it more difficult and expensive to deliver deterministic outcomes.

“It might not be used for banks, but there are plenty of applications where customers don’t need absolute determinism,” Rabaey said. Among those applications are sensor networks, user interfaces, multimedia compression and graphics processing. A broad swath of RMS (recognition, mining, and synthesis) applications may only be doable, he argues, if designers consider the tradeoffs between power consumption and digital resolution, or accuracy.

“We can build machines to deal with lots of errors and still function,” Rabaey said, acknowledging that the approach would involve “a drastic redefinition in the way data is encoded and decoded.”

UC Berkeley's Jan Rabaey

“Some errors are catastrophic . We need an error model to brace against fatal errors. We need errors that have a smooth rolloff,” Rabaey said.

In stochastic computing, the system collects information from the application and from the circuit fabric. It determines which errors are bad and which are good, and provides a classification of errors. The result, proponents argue, is a system that is much more energy efficient.

Already, some MPUs include logic level techniques, such as error-detection blocks and shadow latches which sample the signal, detect an error, which, once detected, causes the processor to roll-back and recompute. “It is quite expensive in terms of power consumption if the chip has to roll back and recompute,” Shanbhag said. “That approach does not admit the possibility of having a benign error — all errors are equally bad. Today’s MPUs treat all errors as the same.”

Industry adoption slow
While MPU vendors are edging closer, using terms such as error-tolerant or self-healing processors, the concept of accepting that some errors may be tolerated may be a decade away from industry adoption.

Within the Gigascale center, ideas for error-resilient system architectures are various, including applications that could be served by an SoC with a super reliable core, supported by several reasonably reliable cores.

Before joining the faculty at Illinois, Shanbhag designed very high-speed digital subscriber line (VDSL) communications ICs at Bell Labs, incorporating the error-correction techniques that make it possible for consumers to bank on-line and trade stocks over noisy telecom networks. When he moved to academia in 1995, he began writing about computing applications that could would be well-served by similar error correcting architectures. However, after more than a decade of research, even relatively obvious applications such as PC graphics processing — where a few errant pixels usually would not be noticeable – remain based on deterministic techniques, he said.

Stochastic computing is the best way to keep power consumption under control, Shanbhag said, particularly for data-intensive applications such as extractions of features, models, and parameters, apps which draw upon huge databases in the process of serving decision makers.

Stochastic computation is based on a model that “allows one to achieve robustness and energy efficiency on SoCs.” Shanbhag is working on a P-encode acquisition filter for CDMA phones, a stochastic computing-based implementation that is two to three orders of magnitude more power efficient than conventional P encode acquisition filters.

Naresh Shanbhag

Lyric takes on Sudoku
So how does this all of this fit into the real world? Lyric Semiconductor emerged from stealth mode at the ISLPED 2010 conference last month, but the startup has kept much of its technology under wraps, partly because it attracted financial backing from DARPA.

Lyric applies statistical inference algorithms to a class of applications, mapping them onto its factor graph-based architecture. The approach creates an algorithmic description of statistical inferences, structures that can be used to derive conclusions from databases. The company has released its first chip, dedicated to error correction on flash memories, and is building a general purpose processor, said Theo Weber, a statistician at Lyric who spoke at the ISLPED conference in Austin last month.

“Lyric’s probability processing technology is designed from the ground up to efficiently consider many possible answers and find the most likely fit,” said Weber. Lyric’s factor graph approach estimates “how variables are connected, such as Sudoku-like problems. It infers meaning from imprecise data,” he said.

Lyric is working on a “GP5” general-purpose computer that Weber said is “1000 times more powerful than today’s processors.”

By Ed Sperling
Reducing the voltage in a system on chip is like turning down the water pressure on a home plumbing system. Pretty soon you find out that not all the faucets work properly because there isn’t enough pressure behind them.

While it’s vital to drop the voltage to boost battery life in mobile devices, not to mention reduce the overall power consumption in plug-in devices, the effects aren’t always well understood ahead of time. Power delivery changes with the voltage, and not always in anticipated ways. The problem is that chips are getting so complicated with power islands and multiple cores that it’s difficult to anticipate all the possible permutations up front.

“There are indeed challenges,” said Jan Rabaey, who heads the Wireless Research Center at the University of California at Berkeley. “Fluctuations in currents are an obvious result of turning domains on and off.”

In fact, the more abrupt the on/off states, the greater the likelihood of power delivery problems. “It’s like hitching a car to a trailer and taking off,” said Srikanth Jadcherla, group director for R&D in Synopsys’ verification group. “It doesn’t move the same way.”

And the more power islands, the worse those problems get. “This is something that’s well known in the cell phone industry,” said Bhanu Kapoor, head of Mimasic, a low-power consultancy. “They’ve got ARM cores, DSPs and memory blocks on a cell phone processor and they have a power supply for all of these different modules. But when you need to switch on a new block, the power supply has to deliver power to both. The power supply inductor tries to guard against any change, though, so it actually gives parts a lower voltage. That causes a temporary malfunction.”

Thinking about delivery in the architecture
While the effect of power islands have gotten the lion’s share of attention in low-power designs, they’re certainly not the only things that can go wrong. Failing to account for all possibilities up front can cause problems that grow as the chip moves from architecture to design and verification.

“Blocked frequencies and domains shutting off are a result of badly designed power distribution networks, which can happen even if you don’t have power islands,” said Rabaey. “By changing the resonant frequencies of the power network, you may see potential interplay with the clock frequency of the modules. But again, this is a generic problem with power distribution networks and has nothing to do with having power islands or not.”

Problems also grow as the semiconductor process shrinks. One of the problems in delivery of power at smaller geometries is the width of the wires themselves. While most engineers went through school with the assumption that electrons move through wires at a fairly constant rate–depending upon the type of wire rather than the thickness of that wire—that’s clearly not the case. IBM first began noticing earlier in the decade that resistance of smaller wires was increasing due to electron crashes with the atoms in the wires. Increased density meant more crashes.

The typical route for chipmakers is to engineer a solution to these kinds of problems. But that also increases the complexity and the price, because it usually means more parts. A 10-cent decoupling capacitor for a chip that is sold in quantities of 50 million adds $5 million to the overall price. And that doesn’t include the additional cost for assembly, which typically adds another nickel, or $2.5 million.

More parts also mean more complexity in the design. And more complexity means more things can go wrong.

“There was one chip we were developing where the clock gating domain produced a spike in current,” said one engineer, who asked not to be named. “We came up with logic to control the wake up, but when you shut down the clock it staggers it. As you’d expect, it got stuck. So we took off the clock-gating circuitry and there was a huge droop in voltage.”

In another real-world example, chip development was stopped the day before tapeout because there was insufficient decoupling capacitance. That affects timing. The chip arrived at tapeout two days later because a crew of engineers worked solidly for 36 hours to fix the problem. Needless to say, they wished the chip architects had figured this out ahead of time.

By John Blyler

Designing embedded systems in energy-sensitive environments requires both attention to power details and a system-level view of overall energy architectures. Successful designers must embrace both perspectives.

This isn’t easy. Most embedded hardware engineers are used to the fairly generous power offered by a wall socket or inexpensive traditional off-the-shelf batteries, where portability is a requirement.

But energy-sensitive embedded designs contain a time-dependency that many designers do not fully appreciate – one not associated directly the function of the battery. Instead, this time-dependency is related to the operation scenario of the application. More on this in a moment. First, let’s consider the power “pain points” that drive engineers to consider energy harvesting systems in the first place.

Pain points
A major pain point is the high cost associated with the use of wired power in any application for which traditional wall socket power is not readily available, such as wireless sensors in data acquisition devices for industrial processes, patient monitoring, remote data logging, agri-business and intelligent building energy controls.

In the past this problem was solved by using single-charge batteries, notes Steven C. Grady, vice president of marketing at Cymbet Corp. “However, the next pain point is having to deal with changing out batteries. The unknown time frame of battery failure and costs to change batteries has also been shown to be very expensive.”

This is where energy-harvesting techniques become attractive, because they can provide a relatively permanent source of energy. However, to qualify as a satisfactory solution, energy harvesting implementations must be on parity or even less cost to wired and battery solution. As Grady explains, the adage of ‘People go green, when it saves green ($)’ certainly applies to energy harvesting.

Other conditions make energy harvesting devices attractive. Sandip Kundu, professor at the University of Massachusetts in Amherst, Mass., says that in addition to being removed from typical power sources, energy scavenging is most attractive for portable devices that do not need large amounts of power and have low usage duty cycles. Low duty cycle of usage applications include food-tracking techniques that use smart labels that contain history of origin information, as well as routing and temperature data.

At the other end of the spectrum are energy scavenging devices used in the co-generation of power, such as with internal combustion engines and heat furnaces. Kundu notes that such cogeneration of power allows the design to combine techniques to improve overall efficiency, such as with the combination of a Sterling cycle engine and thermocouple-based electricity generator.

Servicing the Battery

The reason a designer would choose energy scavenging over a standard battery really boils down to cost and/or the constraints of serving a battery in the application, says Mark Buccini, microcontroller marketing director at Texas Instruments. He says that a simple solar calculator is a good example of the cost benefit of energy harvesters, because a solar cell is actually cheaper than a battery and can last for decades.

One of the best examples of the constraint imposed by servicing some battery-enabled applications is found in solar-powered satellites. Here’s where solar power scavenging really shines, Buccini says. “Solar power is abundant and the cost of replacing a battery in space is prohibitive.” Another more down-to-earth example of difficult-to-service battery applications would be implanted medical devices.

Even with multi-year battery life, most embedded applications eventually will need maintenance in the form of battery replacement. For example, low-cost systems such as underground water meters or tire pressure monitoring systems may require several hundreds of dollars in associated maintenance because they are hard to access.

Before jumping on the energy scavenging bandwagon, designers should heed the words of Jan Rabaey, Donald. O. Pederson Distinguished Professor at the University of California’s Berkeley Wireless Research Center. He says the size of the device dictates just how effectively it can scavenge energy. For example, most scavenging is a third-order factor of the volume of the node, although solar is a square of the node because it is a flat structure. “If you double the size of the device, you can roughly double the amount of energy you can scavenge,” he said.

Energy Storage is a Must

Almost all energy-harvesting scenarios require some sort of energy storage element or buffer. Even if the voltage and current requirements of an embedded application were so low as to be run directly on power captured or scavenged from the environment, such power would not flow in a constant way. The sun doesn’t shine all the time, or at least not on the same terrestrial spot. This means that some type of energy storage element is needed, if for no other reason than to provide a steady and predictable amount of power.

Storage elements or buffers are implemented in the form of a capacitor, standard rechargeable lithium battery, or a new technology like thin-film batteries (see Figure 1). What kind of energy storage is needed depends greatly on the application.

Some applications require power for only a very short period of time, as short as the RC time constant discharge rate of a capacitor. Other applications require relatively large amounts of power for an extended duration, which dictates the use of a traditional AA or a rechargeable lithium battery. Still other applications need the small footprint benefit of the capacitor and the low energy leakage advantage of a tradition battery. This is where the thin-film batteries are gaining acceptance, notes Adrian Valenzuela, product marketing engineer for ultra low-power MCUs at Texas Instruments.

Figure 1: Characteristics of typical energy storage options (Courtesy of TI)

Understanding the Dependency

It should be apparent that the type of energy storage needed to complement an energy harvesting approach is dependent upon the embedded application. Designers must determine the energy capture profile and compare it to the energy storage profile, both of which are functions of the operational scenario of the embedded application. The operational scenario captures dynamic duty cycle or the (often) non-period timeline of the embedded devices usage model.

What tools are available to help the system architect or designer balance energy harvesting and storage cycle that are dependent on the operational scenario of the application? Not many.

There are very-low-power microcontroller kits that help the designer manage power and energy storage. But robust software tools that model the system-level duty cycle given a particular embedded energy input and load output are not yet available. They will be soon, judging by the growing interest in energy harvesting technology.

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Want to meet most of the experts quoted in this story? Then be sure to attend the Design Automation Conference (DAC) Pavilion Panel, Power Scavenging: Waste Not, Want Not

Everyone talks about low-power designs, long battery life and the environmental effects of so much power consumption. However, the consumption of power is an ever-increasing need that must be faced. Are there alternatives to generating “small” amounts of power for low-power gadgets from really unconventional methods? Let the experts tell you where some of the hidden power is available and how they are harnessing it for some of the most complex applications.

Panelists:

Sandip Kundu – Univ. of Massachusetts, Amherst, Mass.

Steve Grady – Cymbet Corp., Elk River, Minn.

Mark Buccini – Texas Instruments, Inc., Dallas, Texas

Moderator: John Blyler, Chip Design magazine

Organizer: Yatin Trivedi, Synopsys, Inc.