Low-Power Engineering sat down to discuss what’s essential and what isn’t in EDA with Brani Buric, executive vice president at Virage Logic; Kalar Rajendiran, senior director of marketing at eSilicon; Mike Gianfagna, vice president of marketing at Atrenta, and Oz Levia, vice president of marketing and business development at Springsoft. What follows are excerpts of that conversation.

LPE: How do complexity and all the different levels of the flow affect signoff?
Buric: Signoff is necessary at every level. Signoff at the DRC level and the DFM level and the gate level will stay forever. However, what’s different is that if you don’t sign off at a high enough level you cannot get to the next gate.
Gianfagna: It used to be that you could leave it to the end and clean it up. You used to be able to leave OPC (optical proximity correction) to the end and fix the litho hot spots. You can’t do that anymore. There are too many hotspots. The tool will find them all but you can’t fix them all. That’s an opportunity for EDA to add more value further upstream so you don’t have to find all the problems at the back end. There are tons of examples like that with power, test, area and routing congestion where you have got to start earlier or you get crunched in the funnel at the back end.

LPE: Engineers have been postponing using power islands and clock gating as long as possible. They seem to have run out of options, even at even mainstream process nodes. Do they understand the difference of what’s needed vs. what’s not?
Levia: There are definitely companies that know what they need and which are very good at educating their suppliers. They’re very good partners for us. If you work with them, they have a very clear road map about what they’re going to do and they are very articulate in communicating what they’re going to need, when they’re going to need it and why. Sometimes they can even tell you how much they’ll need. But unfortunately there are not many companies in this category. More fall into the ‘need to be evangelized to’ category. ‘Let me tell you why you’re going to need power islands.’ Or, ‘Let me tell you why verification is different with power islands.’ So there are two distinct camps.
Rajendiran: The one thing that has changed from a market application perspective is more and more people are buying consumer parts. More people are buying a phone. If you’re a businessperson, you’re going to be using it equally for e-mail and phone. If you’re a teenager you’re going to be using it for texting. Some of them are so good they can text without even seeing a keyboard. So depending upon who it is, power consumption is going to be driven by the application. It’s not so much how much power you can put in, it’s now driven by the usage model. That’s a big change from 10 years ago when you worried about a processor that was 50% faster or one that consumed 20% less power. Those were the two slides you took to a VC to get funded. Now it’s usage. Even if you’re looking at infrastructure, it’s the green initiatives that are driving it. Intel changed five years ago when they went to multicore and power conservation. Bigger companies do a better job figuring this out and marketing it. Smaller companies are still struggling with it.
Gianfagna: Natural selection will weed out those companies.
Rajendiran: Yes, and it’s already happening.
Buric: There are a few customers—a minority—who understand what it takes. What we’re seeing as an alternative is coming from companies like TSMC with a reference flow. With the reference flow is a list of the tools needed to get you through the reference flow, which helps their business.

LPE: So they give the choice to their customers?
Buric: They’re not even choosing. They’re working with a few leading customers to learn what they need and then they have to decide whether customers can afford it or not.

LPE: Is GlobalFoundries doing that, as well?
Buric: Not yet but they will catch up. It’s a must. You cannot explain to most companies what they will need.
Gianfagna: There are a handful of customers who know what they need and drive the strategy. We all kind of work with the same customers. What’s different is the ‘have nots’ at least know what questions to ask and are looking at outsourcing more. They’re looking to understand the process better. It’s improving. The need to work differently is becoming a competitive advantage. There are some who don’t get it. You won’t see them in a year or two. That’s the opportunity for EDA. There’s a better-educated consumer base for what will bite them. You don’t think about some of this stuff at the gate level. You think about it way earlier when you have an architecture in mind, or even before. What processor will you use? What power domains? What throughput? These are high-level decisions, and it takes tools and IP. That’s the opportunity for us.

Low-Power Engineering sat down to discuss what’s essential and what isn’t in EDA with Brani Buric, executive vice president at Virage Logic; Kalar Rajendiran, senior director of marketing at eSilicon; Mike Gianfagna, vice president of marketing at Atrenta, and Oz Levia, vice president of marketing and business development at Springsoft. What follows are excerpts of that conversation.

LPE: Where is the most activity? What node?
Rajendiran: Over the last three years it has undergone a transition. At 180nm everyone looked to 130nm and then they were all looking at 90nm. The foundries started introducing processes sooner and sooner. It used to be about three years between nodes. Then it became two years. Between 90nm and 65nm it was really only a year. It confused everyone because the expense was going up. The IP companies had issues. Then the economic downturn hit. We saw a resurgence of a lot of designs going to 130nm again instead of 90nm and 65nm. There are companies that have chips and are thinking about taking what they have and combining them into an MCM (multi-chip module). It may not even be their own chip. They may be combining it with another company’s chip.

LPE: So it’s going in two directions?
Rajendiran: Yes. Some companies are looking at MCMs. Others are looking at 40nm and 28nm. There is a lot more risk, so people are really thinking out of the box.
Levia: Everyone looks at it from their perspective, but that can be really different depending upon the market they’re in, the size of their company, the geography they’re in. The economy comes into play whether you’re in China or the United States or Canada. What you’re trying to accomplish is very different.

LPE: In the past, when we pushed to the most advanced nodes, you were dealing with one or two problems. Now you’re dealing with all of them at each new node. How does the cost equation affect everything?
Levia: Fabless companies and IDMs, whether they’re moving to the next node or staying at existing nodes, haven’t always figured out up front what the compounded complexity will be. That may be in the form of verification or the design or integration or packaging, functionality, reliability or DFM. The demand that puts on the EDA industry is to come up with very quick solutions to second- and third-level integration problems. It also puts pressure on the cost function. We are expected to participate in that cost reduction. The problem has exploded, but the price of the phone has gone down and the revenue to the chip provider has gone down slightly, so you’re expected to take a haircut. It’s a problem, but it’s an opportunity for the companies that can automate difficult steps. These steps may be very mundane. It may be power estimate at the right time, or power-aware debugging at the right time. It may be DFM or DRC at the right time. You need to understand what is taking a lot of time and whether you can automate it. It’s shifting ground, though.
Gianfagna: The synthesis place and route flow is getting less interesting. Will you have a better product because you use synthesis place and route from Cadence vs. Synopsys? I don’t think so. Will you have a successful product because you chose the right IP or number of processors? Yes. The value for differentiation is moving up the stack, past the synthesis place and route flow to better IP reuse, better debug and better planning. There is a shift to put more effort on the front end because if you spend $1 on the front end you can save $3 on the back end. If you can eliminate a two-week place and route, that’s worth a lot. You also don’t need as many tools, but that’s a secondary benefit.
Rajendiran: At every handoff point you need certain things. But the industry has undergone so much pressure they don’t always think this through. You need clean deliverables at each point. There is value at every step to help with the cost of ownership. You may put a heat spreader into the package, but that may cause more harm than good. People don’t necessarily think that way, though. Given everything you’re doing, is that the right solution? Some companies are better at understanding the big picture. When you have a customer and they’ve established a methodology that they really think through, that’s usually better than a startup at understanding it. It isn’t the tools, the IP or the package. At the end of the day the product has to come out on time.
Buric: For most customers to move to signoff from the spec and all the way down is not always possible. I have seen designs people have finished and missed off spec by a few percent and they had to throw it away because it was designed to be on a PC board. There was no room for error. It doesn’t matter whether it comes from process, bad calculation or bad estimation. The industry is moving to very accurate analysis and signoff on an architectural level, and then at each level try to meet those specs. We are spending more and more on accurate modeling, and EDA companies are taking more spreadsheet functions to make high-level analysis as accurate as possible. On top of that, you can’t afford to move from a plastic package to a ceramic package because it costs too much. From the other side, I’m seeing more and more end users or system houses to provide a spec without getting involved in the design at all. They don’t see the value of design. They see the value of the box.
Gianfagna: That’s a perfect distillation of the process. The signoff need is unquestioned. There’s a long checklist of timing closure and design processes and electrical rules check for the gate-level netlist. That’s moving upstream. You want rigorous signoff earlier and earlier. The ultimate is a spec-level signoff, which will take awhile.
Levia: Let me inject a little bit of reality into this. Calibre is still not done at any high level—definitely not at RTL. But Calibre is signoff and it is doing quite well. The reality is that it’s only successful because it is offering a step that is absolutely necessary and is incapable of being accomplished any other way. You cannot do it by hand. At 28nm and 22nm, there are more rules but it’s still more complicated. There are 3D effects and the tools are conditional.
Buric: That started at 65nm.

By Ed Sperling
Synopsys bought Virage Logic today for $289 million, extending its IP portfolio well beyond just standard I/O and PHY into memory, logic and processor cores.

The move strengthens Synopsys’ position as an all-in-one powerhouse with IP that can fit into an integrated flow.

“A big part of the value is providing building blocks that work through the SoC flow,” said Joachim Kunkel, senior vice president at Synopsys. “We started out providing interfaces and PHY and then added common analog functions. Now we’re adding embedded memory, which is required by many chips to help with cost reduction.”

Synopsys has always had a tight working relationship with ARM. Kunkel said the acquisition of the ARC processor will not affect that relationship.

“SoCs typically have a main CPU, which is a multiprocessing slot occupied by ARM, MIPS or IBM’s PowerPC. Then they do other processing with another processor to offload the main CPU for things such as audio. That’s where ARC fits in. It is an ancillary processor offloading the CPU.”

All of the large EDA vendors have been looking for adjacent markets to help grow their top-line revenue and their bottom line profits as the number of players developing advanced chips remains flat to slightly down. While those chips are certainly more complicated, there are fewer design starts at the front edge of Moore’s Law.

IP is one such adjacent market. “Our role is to solve the issue of complexity in designing an SoC,” said Kunkel. “One side of this is the tools. The other is the basic building block to reduce cost and reduce risk.”

Synopsys’ IP and systems business has been responsible for about $200 million in revenue per year and represents about 13% of the company’s portfolio, including the recent VaST and CoWare acquisitions. Virage will increase that percentage by a significant amount once the deal closes in Q4.

Both boards have agreed to the terms of the deal, which is $12 per share for Virage stock, or $315 million. Virage has roughly $26 million in cash, making the net price about $289 million.

Low-Power Engineering sat down to discuss what’s essential and what isn’t in EDA with Brani Buric, executive vice president at Virage Logic; Kalar Rajendiran, senior director of marketing at eSilicon; Mike Gianfagna, vice president of marketing at Atrenta, and Oz Levia, vice president of marketing and business development at Springsoft. What follows are excerpts of that conversation.

LPE: What are companies trying to do now that they didn’t do in the past?
Gianfagna: The whole mantra that you can’t close a design without better tools and without better accuracy and that complexity is an imperative isn’t new. We’ve been saying that for 20 years. But what has changed in the past two years is that it’s gone from marketing hype to reality. Complexity is so high these days that no one would dream of handing off a design without routing estimation, power estimation, architectural focus and paranoia on meeting timing budgets. Complexity is driving need to have for better up-front planning, better IP re-use, more things like verification IP and standards interfaces. That’s all continuity. Discontinuity will come from 3D. I defy anyone to say they can iterate on a 3D stack by implementing four chips, deciding it’s not right and then re-implementing the four chips until they get the partitioning right. You can’t get there from here.
Buric: A single failure on advanced process nodes will cost six months of re-doing the design. And then it will cost another $3 million to $4 million. You spend much less money purchasing all the EDA that’s needed, including the training and implementation, whether you’re doing it yourself or going to a service partner. Nobody who is doing complex chips has a question anymore about whether EDA is needed or not. The only question is whether you have the tool you need that is fully supported so that you can use it. But it’s not a question of purchasing a tool. It’s too expensive to fail.
Gianfagna: That’s been a battle cry for EDA. If you’re late to the market it will cost you this much money. It’s intuitively obvious, but a lot of companies sat there patiently and said it’s a self-serving message. Now if you don’t get it right it’s game over because you don’t have enough money to do it over again.
Buric: As a point of reference, at 40nm the average cost of a mask set is higher than the cost of the IP on a design.
Levia: For a product or methodology to be a must-have it has to satisfy two criteria. One is that it enables a step—transformation, verification, or whatever the step is—that is essential. Not all steps are essential. Getting to GDSII is essential, however you get there. The second criteria is that the tool has to automate or enable something in a way that is incapable of being done manually—or practically manually. So if you have a one- or two-person startup and they have a complicated problem, and the choice for them is an expensive tool or a bunch of pizzas and people working 16 hours a day, the tool is not a must-have. But if you have a large verification organization of 30 to 50 people and an investment in customer orders and the good will you have with many suppliers and consumers of your product, then it is a must have. What is a luxury to someone else is something you cannot afford to go without. You can still incentivize people to work 16 hours a day, but the economies don’t work anymore. If you can have a team of 50 people instead of 80 people, it’s a no-brainer. You buy the tool. In addition, all customers are not the same. Reliability might be paramount for the military and automotive, while time to market is more essential for a consumer electronics design that has to do with Bluetooth.

LPE: What’s the user perspective?
Rajendiran: We look at it from a business practicality perspective. What’s needed to get a chip out the door? If you go to a market where labor costs are lower, you need more people to get something done because the expertise level is lower there. The efficiency isn’t there. In the U.S., because labor is more expensive, we’ve always focused on using tools to get the product out. Not all tools have been adopted at the same rate, though. High-level synthesis has been talked about for 20 years. Functional verification and high-level synthesis are now taking root because things are so complex, but how do you close the gap and do the correlation? You can have great tools but still not get the chip out the door. The reason the IP industry is there is to ease that problem. We have been talking more about a multi-chip module, which never really caught on in the past, but maybe it is coming to a head. Do you really have to migrate a chip to 28nm or do you just leave it alone because you know it’s functioning and put a smaller chip at 28nm and tie it together. What we need isn’t just the newest and best tool. We have to combine that with a business perspective. You may need point tools to get over a hurdle, but don’t just change everything over. Why not leverage more IP or MCMs?

LPE: Are all companies moving forward to the next node?
Levia: We see a lot of demand for 40nm, 28nm and a road map into 22nm. Are there many people using 28nm? No. Are your tools viable if you don’t have a road map down to 22nm? No. I don’t think people are sitting back anymore and saying 65nm is enough. Silicon is cheap, but it’s not free. People are still looking for ways to improve the cost and they’re looking for ways to integrate, both in custom design and in digital.
Gianfagnia: As an EDA supplier, by definition your biggest demand and your biggest customers will always be from the leading edge. They don’t need any new tools, but maybe they’ll renew and they’ll always be the ones to push the limits. From our point of view, our tools are very front-end loaded. If you’re doing a simple chip, you don’t need it. But in a design where a back-end synthesis/place-and-route iteration is two weeks or three weeks, you can’t iterate there. That’s where we’re seeing a pronounced change. There’s a growing demand for beating the RTL in every different direction or you don’t trust it. You’re afraid of those back-end loops. The cost and the time to get it closed are changing. What used to be ‘nice to have’ is now ‘need to have.’
Buric: We see a lot of unexpected activity at 40nm in this early stage process. We already have about 40 customers. At 65nm, it was not adopted so fast. We are seeing a lot of activity at 28nm, but 40nm will be a node where you will see a decline in the number of customers moving to a new process node. People aren’t moving for performance purposes as much anymore. They’re moving there because they can put more functionality in a single chip. But in the future there will be too many applications at this process node. At the same time, we are seeing customers and foundries are investing a lot in mature process nodes. Starting from 180nm, we are seeing new generations of processes including low leakage. There is a trend to actively use a wide spectrum of nodes. From a user perspective, it will be less expensive to do older designs in-house. We are seeing a big disconnect at 65nm, 45nm and below. Owning the design at those nodes is too expensive for most companies. It’s not a question of working through the night. It’s a question of whether you can afford the design or not.

By Ed Sperling
ARM, Freescale, IBM, Samsung, ST-Ericsson and Texas Instruments teamed up to create “Linaro,” an open-source software engineering company. The stated goal is to speed the development of Linux tools and foundation software. While this is great for large processors, the real question is just how much Linux technology will be scaled down. In many applications, size matters, and being able to work with open source software in a smaller footprint is a big plus when it comes to power issues.

MIPS added symmetric multiprocessing support for the Android platform using multicore MIPS SoCs. This gets particularly interesting because in addition to multi-threaded applications, there is a trend to dedicate specific functions for cores. The possibilities are enormous, both in terms of functionality and more efficient power utilization.

Mentor Graphics updated its verification lineup just in time for DAC. The company rolled out version 3 of its O-In formal verification, adding better support for mixed language design and tighter integration with its Questa platform. The company also released a O-In CDC update for clock-domain crossing verification. While these are interesting releases in their own right, it looks particularly interesting for SiP and 3D stacking.

Synopsys, meanwhile, rolled out high-level synthesis support for Xilinx’s Virtex-6 FPGAs. Design of FPGAs used to be relatively straightforward, but at advanced process nodes they encounter the same headaches that SoCs do—area, power, performance and verification.

Sound quality may be the next big selling point in the PC and netbook space, along with battery life and I/O speed. ASUS is betting the bank on Virage Logic’s Sonic Focus as a differentiator, complete with new enhancements. So much for the tinny-sounding speakers that make it next to impossible to understand anything.

Alex Shubat, CEO of Virage Logic, talks with Low-Power Engineering about the increasing role of IP in semiconductor designs along the Moore’s Law road map and why power is becoming so important.

By Ann Steffora Mutschler
Power may be expensive, but just turning off sections of a chip, lowering the voltage or using low-power manufacturing processes have their own costs.

Whether using power, or managing it, there is a price. As Brani Buric, executive vice president at Virage Logic says, “Power is not free.” But fortunately, other things in a design can be traded off in order to achieve the desired power budget.

Specifically, power can be traded off for the design domain, area and performance. Moreover, given the state of advanced technologies, designers also can choose between different process nodes that will give, for the same area, different power/performance tradeoffs.

Buric noted those tradeoffs can be achieved on different levels of design abstraction with an equal opportunities on every level. “For example, when a company like Virage Logic or ARM is designing a microprocessor that is delivered in RTL form we can still trade off performance for power or, in certain cases, area for power. Then, if you go down in abstraction, when it comes to physical IP, you have even more nodes where you can trade off performance for power, area for power, etc.”

A lot of power-saving techniques can be implemented in a memory, for example, but if RTL designers are not aware of power saving techniques they will implement a memory that doesn’t use those techniques.

“Designers or systems architects have to decide on that level where they are going to do tradeoffs between power, performance and area,” he said. “Based on that, they can select optimal IP that fits in their power algorithm concept. From our side, we essentially have all of our physical IP designed that way so that designers have ‘knobs’ and a dashboard of options to tune power – both dynamic and static (leakage) – to the desired level, trading off mostly performance and in certain cases, area.”

Competing IP provider Synopsys Inc. gets requests from customers for the lowest power with aggressive targets for area and other performance metrics, according to Navraj Nandra, director of product marketing for analog/mixed-signal IP. These requests require the IP vendor to simultaneously optimize for power and these other requirements. Specifically for analog/mixed-signal IP, this is achieved through design techniques such as low-power transmitters for USB and high speed SERDES, lower amplitudes for the I/Os in DDR and simplified analog stages with reduced biasing in data converters.

Nandra noted that these techniques deliver the lowest power but do not necessarily trade off performance, and that the biggest trade-off is speed and transmission distance when low power techniques are adopted in IP development.

Software analysis tools help make power tradeoff decisions
While Tensilica looks at power from the architectural level—if certain design decisions are made as to configuring a processor to fit a particular algorithm, then benefits of low-power can be had by being able to run the processor at a much lower clock rate than it would otherwise — the company has profiling tools to allow engineers to figure out what those instructions are that would help benefit optimizing the processor to fit the algorithm, according to Chris Jones, director of product marketing at Tensilica.

At the physical design layer, Tensilica has an energy estimator tool called Xenergy that gives real-time feedback on the relative power numbers based on the configuration attributes for chosen processors. Specifically, Xenergy gives dynamic energy consumed on a cycle-by-cycle basis, Jones explained.

“[SoC engineers] can take this algorithm, choose a processor with one set of attributes, render the energy estimator tool, and get a power number. If they want to add a couple of instructions or they want to grow the size of the caches or add a MAC instruction, they can then run the same algorithm again and run the Xenergy tool to see what power benefits they are able to gain by making those design decisions.”

Tradeoffs impact IP ecosystem
“We struggle with [making tradeoffs] today with our test chips because we don’t want to develop a complete SoC, but with our test chips we want to validate the technologies together and so fundamentally we are looking for functional things and best practices,” said Kevin Kitagawa, director of strategic marketing for MIPS Technologies. “Are we getting the fastest amount of performance? Absolutely not, because there are diminishing returns after you get to the 90% performance level. It is the same with power consumption: you can probably get 90% of the power savings out of a particular design, but the last 10% will take double the amount of effort. So we try to pick up where the knee in the curve is, where you’re starting to not get a lot out of the extra engineering effort.”

He noted that the availability of open source platforms such as Android is impacting the need to make tough design decisions.

“A lot of people are trying to squeeze in what used to be implemented in specific hardware. For example, people want to implement Android in a lighter sense, and in a cost structure that is probably one-third of what the requirements are for Android today. Instead of 256MB of main memory, they want to do it in 64MB of memory, so a lot of challenge is trying to get the benefits of Android into a cost structure that makes sense for them,” Kitagawa said.

It is possible to attain this, he said, but hard decisions would have to be made as to feature set and performance levels with some sacrifices along the way.

Whether it is sending in an expert or sending in software, there is opportunity on one side and a vital need on the other.

By Ed Sperling
Mentor Graphics added multicore solutions for symmetric and asymmetric multiprocessing to its Nucleus real-time operating system, building in support for the multicore communications application programming interface, aka MCAPI, for communications between processors. The standard was established by the Multicore Association.

Synopsys added support for Actel’s SmartFusion FPGAs, which add programmable analog on top of an FPGA. The Synplify Pro tools have been enhanced for timing optimization of the flash-based Actel architecture.
Synopsys also introduced its next-gen rapid prototyping system, the HAPS-60 series, for hardware-software co-verification.

Cadence contributed extensions for the Verilog-AMS standard to Accellera to improve accuracy and offer more plug-and-play in mixed-signal environments. That includes most SoCs these days.

Virage Logic qualified its AEON non-volatile memory EEPROM IP for 1 million cycles at 105 degrees Celsius. In event of severe global warming, you can be sure this will still work. In fact, it may be the only thing left working.

By Ed Sperling
At 90nm companies had to begin thinking seriously about how the signals inside a chip would begin interfering with each other. At 40nm and beyond, they have to consider how signals are interfering with each other across an entire device that may include multiple SoCs.

This marks an interesting shift in what companies have been calling holistic design for the better part of a decade. In the past, holistic design was considered the chip and the software. It now needs to include all of that, the IP, and the other components within an end-user device.

“As you lower the voltage the amount of radiation has less power, but as you raise the frequency you create different radiation in different frequency bands,” said Wally Rhines, chairman and CEO of Mentor Grpahics. “So there’s the on-chip issue of interference and cross-talk. On printed circuit boards we’ve had automated routing software that reduces cross-coupling by differential pair routing to improve signal integrity. That’s been in the software for a decade. But if you look at the revenue for the printed circuit board business, signal integrity and power integrity have gone from being negligible to being a substantial perception of the business.”

Where there is business there are problems, and the problems are growing by the process node. At 32nm and 28nm, which companies are just beginning to explore, the proximity issues are rampant.

“You also have gigabit signals on these boards and serialize and deserialize,” Rhines said. “If the 64-bit bus is replaced by a serial link, it runs at a pretty high frequency.”

History repeats
Ever since computer processors hit clock speeds of 1GHz there have been dire warnings about interference. At that frequency, computer makers had to certify they wouldn’t interfere with the communications systems of airplanes. Shielding components inside a computer has a long history.

Cell phones have their own long history, in part because of the radiation from the phones and in part to reduce cross talk and other electromagnetic interference.

“For some time, people have been spending a lot of time shielding critical signals in an SoC,” said Brani Buric, executive vice president at Virage Logic. “There is also process of shielding to avoid the negative effects of close proximity to the SoC. This has been done for a couple of generations inside the SoC, but it hasn’t been done much outside the SoC. But with higher frequencies you need to provide a methodology for electromigration.”

He noted that every interconnect now requires a very detailed signal integration and noise analysis, plus the ability to do adjustments in the design once engineers fully understand the environment and the interactions.

The price of progress
But it also requires a willingness to do that kind of analysis. Dian Yang, senior vice president of product management at Apache Design Systems, said economics are working against the investment in shielding in some products.

“A TV board may have 3,000 capacitors that cost $30, but if the margin on the TV is only $30 that doesn’t work. So they either buy a cheaper chip and keep the capacitors or they buy a more expensive chip and board. That becomes an architectural decision. It’s the same for the package. Do they add more layers?”

All of these cost considerations have an effect on the overall design because they also affect shielding. Fewer smaller devices on a board and smaller boards can reduce the overall power consumption. But there’s less room for shielding, as well.

There’s also less room for countering effects in advanced designs that shrink the margin in SoC designs, which is a prerequisite with some of the restrictive design rules handed down by foundries. Guardbanding makes chips more costly, lowers performance and increases power consumption. But it does sometimes compensate for proximity effects.

Conclusion
To a large extent, shielding also is a function of the companies developing chips and devices. Virage’s Buric says there are three distinct types of companies working in this market. The first uses companies like eSilicon or Open-Silicon to develop chips for them, and they have plenty of experience dealing with these kinds of effects. The second involves big integrated device manufacturers, which also are skilled in this area.

“The most exposed are the fabless companies, particularly those with enough interest to do it in-house but not enough expertise,” he said. And while Virage has been working with some of those companies, no one really knows how many are falling through the cracks.

By Ellen Konieczny
The air interface dubbed Long Term Evolution (LTE) hails the coming of fourth-generation (4G) cellular communications, which will benefit from both increased capacity and speed. Among the lofty goals of 4G technology is the promise of users being able to widely access streaming media, such as mobile television and video, in real time. Before such capabilities can be made available, however, designers on both the infrastructure and handset sides must overcome a number of steep hurdles related to power consumption.

Compared to third-generation (3G) communications, 4G networks will demand more power. Base stations must therefore provide higher power while limiting what they consume (See figure 1). For their part, handsets will struggle against shorter battery life. Already, smartphones tend to consume more power than traditional mobile phones. The added features and capabilities of the next generation will only add to this problem.

Fig. 1: The 9341 remote radio head (RRH) promises to reduce power consumption by as much as 50 percent. Mounting these RRHs close to the antenna virtually eliminates feeder losses, which lowers the RF power required.

“The main challenge posed by LTE for 4G terminals is in designing an extremely powerful and cost-effective communications IC that meets the stringent power constraints of battery-operated devices,” said Eyal Bergman, director of product marketing at CEVA. “This means an efficient 4G architecture has to be built using extremely efficient power-management techniques while addressing a dramatic increase in processing requirements.”

Bergman points out that LTE algorithms are highly parallel and demanding. With the use of the single-instruction, multiple-data (SIMD) architecture, for example, the same logic can be used for wide data elements with higher processing capabilities and lower power. One type of SIMD architecture that’s becoming increasingly popular for LTE is vector processors, which enable a deep-level SIMD for advanced communications. When used in conjunction with SIMD, the very-long-instruction-word (VLIW) architecture enables good isolation of parallel operations and higher power vs. performance efficiency. The different VLIW execution slots consume power only when they operate. Lastly, modern communication processors may incorporate a power-management unit to allow dynamic control of both voltage and clocks to minimize the power per use case as well as during standby.

LTE handsets also will reign in power consumption by using the Orthogonal Frequency Division Multiple Access (OFDMA) modulation scheme. As noted by Olivier Gueret, LTE Product Marketing Manager at Alcatel-Lucent, “OFDMA is a high-order modulation technique. It maximizes the number of transmitted bits per hertz, therefore allowing improved spectral efficiency. While the downlink uses plain OFDMA, the uplink uses a variant known as Single Code—Frequency Division Multiple Access (SC-FDMA). This technique has a low peak-to-average power ratio (PAPR), which translates into better power efficiency and thus, lower power consumption. This guarantees battery saving on LTE terminals.”

On the network infrastructure side, the advanced signal-processing features of LTE base stations also help to improve the quality of experience without additional transmitted power on the terminal side. For example, the Inter Cell Interference Coordination (ICIC) feature reduces interference at cell edge through smart-spectrum fractional reuse. LTE infrastructure has captured the most attention for its deployment of advanced spatial multiplexing with highly demanding multi-antenna schemes, such as multiple-input multiple-output (MIMO) 4×2 and 4×4. Such schemes promise to deliver major improvements in cell center and edge data rates. Yet their effect on the base station’s power consumption is still uncertain.

Although they concentrated on 2×2 MIMO, a group of researchers at the University of Bristol attempted to show that an efficient exploitation of multiple antenna techniques and multiuser diversity in the time, frequency, and space domains can significantly ease the power requirements of a base station. Their paper, titled “Power Efficient MIMO Techniques for 3GPP LTE and Beyond (2009),” examines the capabilities of various multiple antenna transmission and precoding techniques in combination with multiuser diversity. The researchers’ goal was to reduce the total power consumption needed for wireless system operation while improving energy efficiency. They examined a number of MIMO precoding techniques, which can be potentially applied to LTE, in terms of their combined spectral- and power-saving efficiency. The researchers found that all MIMO schemes benefit from multiuser diversity and show improved power efficiency as the number of users increases.

DSPs Serve Handsets And Infrastructure
As both the handsets and infrastructure equipment need to support uplink and downlink chains of the same standard, a lot of commonality exists between them. The similarities are typically in the basic algorithms and tasks. Of course, the network infrastructure must handle an added layer of complexity due to the need to support large numbers of users concurrently. Despite this difference, CEVA’s Bergman asserts that advanced digital signal processors (DSPs), if designed right, can be scaled from the terminal applications to also support the infrastructure side with the following main modifications:

1. • The use of multiple processors (multicore) vs. one to a few processors in the terminal side, which will allow a large number of users to be served in parallel, and
2. • The need to support transformations like FFT/IFFT/DFT/IDFT that can be supported on the processors themselves (if can do it with software) or by integrating additional logic.

Already, a number of high-performance, ultra-low-power DSPs have been designed and optimized for advanced wireless-communications processing in mobile handsets, as well as wireless-infrastructure applications. In fact, recent DSP releases claimed to be up to four times more power-efficient than general-purpose DSPs. To minimize power consumption they use features like power scaling to automatically scale speed and voltage for various units within the processor.

For both LTE handsets and infrastructure, low power consumption is being built into roadmaps for LTE’s future. Down the road, for example, Gueret notes that the LTE-Advanced uplink collaborative multipoint transmission (COMP) combines the signals received by several base stations to improve the quality on the uplink. In addition, LTE base stations should soon be able to dynamically adapt their emitted power to the traffic. This feature is part of the self-organizing-network (SON) initiative at the 3rd Generation Partnership Project or 3GPP.

Next year is slated to bring the next LTE protocol. Dubbed LTE Advanced, it is an order of magnitude more computationally intensive than the current version, says Mike Thompson, director of product marketing for processor solutions at Virage Logic. Thompson emphasizes that LTE is already very compute-intensive in its current state, making it hard to make cost-efficient implementations that comply with the protocol and have low power consumption. Obviously, every technology carries its own set of limitations. Yet not all of them are making such grand promises as LTE. If this small sampling of innovations represents the work going on around the globe, however, solutions will be developed in time to reign in power consumption from the base station to the handset.