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Archive for May, 2011

Top 5 Reasons For Power Delivery Failure

Thursday, May 12th, 2011

By Matt Elmore
Technology scaling has brought with it a myriad of causes for power delivery network (PDN) failure. Even a few years ago, it was simply enough to run static and dynamic power analysis to expose any voltage drops caused by weak power routing. No one cared about modeling the package and PCB. To account for clock jitter, you could simply throw in a whole nanosecond of clock uncertainty. Today, however, the scope and size of the problem is much worse. Demands for performance, cost, and size have brought us new design methodologies and more power delivery issues.

Designers targeting various end application markets such as mobile devices, computers, gaming consoles, automotive systems, etc., all have one thing in common—the growing concern for managing power, both consumption and delivery, by and to their circuits, respectively. There are always new and recurring issues that designers face with PDN design as they increase the levels of integration in their chips or move to smaller technology nodes.

In order to understand the causes behind PDN design issues, I conducted an internal survey of application engineers and product specialists, asking them to list the most commonly seen reasons for PDN failure. Here are the top 5 reasons, how to analyze for them, and what designers have been doing to correct these potential failures.

#1 – Insufficient Package and PCB Layout or High Impedance Profiles
Package and PCB designers are designing more complex layouts, using fewer layers and smaller real-estate footprints. These challenges necessitate decisions that often result in a package/PCB with higher loop inductance and characteristic impedance. The voltage drop over the package and PCB (V = L * di/dt) has become a critical issue for power delivery. In order to cope, designers are extracting parasitics early in the design flow. Models of the package and board are being used in on-die voltage drop analysis and are mandatory for an accurate sign-off. In a complementary way, chip designers are now providing Chip Power Models (CPM™) to their package/PCB colleagues so they can design and optimize their layouts more efficiently and accurately.

#2 – High Localized Switching
Simultaneously switching instances in a localized area can cause a sharp demand in regional current. If the power supply connection to these regions cannot supply adequate current, then timing can degrade to the point of failure. Take test-mode ATPG analysis, for example, a worst-case nightmare for simultaneous switching. A very large number of flops and most of the logic gates fire at the same time, spiking the current demand. A few years ago this power failure cause might have been first on the list, but industry-wide adoption of dynamic power analysis has helped alleviate this issue. Designers are using advanced techniques such as decap insertion, power grid optimization, and spreading clusterized switching instances to overcome this problem.

#3 – Poor or Incorrect On-die Power Route
High voltage drop is often caused by shorts, disconnects, and weak connections to the device transistors. This is one of the most common reasons for power failure, yet still remains at the top of the list. While LVS will highlight any shorts or isolated instances from the power grid, it takes power noise analysis, especially a Dynamic Voltage Drop (DVD) analysis, to expose the weak connectivity. Analyzing at the full-chip level is necessary, as well. A hard macro might pass voltage drop margins, but if the connectivity from the top-level is not robust it will show up in top-level dynamic voltage drop analysis.

# 4 – Voltage Drop on Critical Paths
STA doesn’t account for the time varying effective voltage that each cell experiences during each cycle of operation. The time it takes for a signal to go from one flop to another is affected by the effective voltage v(t) seen by each element of the logic cloud. This varies from pico-second to pico-second, and each cycle has a unique switching scenario to define the noise signature of the chip. Designers are now analyzing the timing of the critical path by annotating the effective voltages for each instance into transistor-level simulations.

#5 – Chip-Package-System (CPS) Resonance
System impedance varies over frequency and is a function of die, package and PCB parasitics. At various frequency points, coupling between the chip and PCB capacitance with package inductance causes system resonance. It is critical that the resonance points do not happen to coincide with chip operational frequencies. Voltage noise is exaggerated by the ringing effects perpetrated by resonance. To overcome this issue, designers are creating chip, package, and PCB models and performing AC analysis to determine system resonance. Using a CPS methodology now, designers have abandoned the silo-based partitioned approach and replaced it with a holistic approach, where each design team (chip, package, and PCB) builds their component with the knowledge of system impedance specifications, so they can avoid these resonance frequencies.

Some other good reasons for power delivery failure, but not in the Top 5, include: noise coupling in power-gated designs; ESD failure; lack of decoupling capacitance, and clock jitter failure.

Next time we will review the “Top 5 Reasons for Power Consumption Waste.”

–Matt Elmore is a Principal Applications Engineer for chip, package, system modeling and analysis at Apache Design Solutions