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Archive for January, 2012

Better Power Planning

Thursday, January 12th, 2012

By Preeti Gupta
Making the right architectural decisions for controlling power consumption and ensuring power integrity requires early identification and quantification of varying current demands in a semiconductor design. Furthermore, low-power designs pose complexities for power verification, such as significant current surges caused by clock gating or power gating transitions.

In last month’s blog on Power Delivery Networks (PDN), I highlighted the need for re-tooling traditional methodologies in order to ensure power integrity. I talked about how a paradigm shift of moving up earlier in the design flow allows designers to uncover and account for stringent current demands and ensure power integrity without over-design. But, can early analysis deliver sufficient accuracy to reliably guide early power grid prototyping and chip-package co-design? This challenge needs to be addressed for designing complex products in an unforgiving consumer-driven market with shortened schedules and no room for costly mistakes.

Early and reliable RTL power
Smart modeling approaches must make early analysis feasible despite the formidable gap between design information that is available early in the flow versus after implementation. The Register Transfer Language (RTL) description of a design offers the right balance between capacity and accuracy. RTL is the highest level of hardware design description that enables realistic full-chip power budgeting. However, it must account for the electrical effects of the fabrication technology, model clock trees representative of the implementation and low-power techniques such as multiple power/voltage domains, varying threshold voltages and clock gating, just to name a few. Using data-mining and pre-characterization techniques can help strengthen RTL analysis to compute reliable power estimation.

Critical power events from RTL vectors
Reliably estimating power is one aspect. But, is it representative of the design’s typical and worst current demands across multitudes of operating modes? With gate-level simulations limited in coverage and available too late in the design cycle to be useful, moving higher up in the design abstraction is again the best alternative. The design’s behavior and power profiles can be more readily simulated at RTL for the needed coverage with runtimes that are orders of magnitude faster and full-chip capacity. Further, millions of RTL vectors must be pruned to the power-critical subset of cycles including those consuming the worst transient and peak power, for both early and sign-off analysis. This would substantially boost power integrity analysis tools that operate at picosecond granularity and cannot afford to analyze milliseconds of simulation cycles.

RTL Power Model for early power planning
With realistic power estimates and critical power events identified, an “RTL Power Model” can be generated that is specifically intended for physical power planning and integrity tools. The model must have a well-defined syntax to bridge not only the “design” gap but also the “geographical” and “expertise” gaps between the logical and physical design teams. The model handshake must also be seamless with downstream design and verification tools. An example would be the construction of transient current profiles using the RTL Power Model in conjunction with additional pre-characterization data, thus enabling early dynamic voltage drop analysis. Aided by the RTL Power Model, an early chip-level power model representing current and parasitic profiles can also be generated for true chip-package co-design, well before chip layout is available. The power delivery network and the package can now be designed to meet the identified target constraints instead of being a costly afterthought.

RTL Power Model enables right-sizing the PDN and package early, avoiding costly late iterations.
Power grid layers/pitch, metal layers in the package, and decoupling capacitance on- versus off-chip are a few examples of the several decisions that cannot wait until the physical design for a chip is complete. Yet, an under- or over-design on any of these could be catastrophic. An RTL Power Model based approach can bridge the power gap between the RTL and implementation stages of semiconductor design to enable major power-related decisions early in the design flow when it matters most!

–Preeti Gupta is a senior technical marketing manager at Apache Design Inc. (a subsidiary of ANSYS).