So where is the agency investing its funding these days? In universities, of course. It has awarded more than $1 million to college teams for innovative environmental solutions, some of which involve energy efficiency that is literally thinking outside the box.

Some are winners, some are honorable mentions, but the key is that all of them are pushing in the right direction. Add this kind of technology to efficient SoCs—or have intelligent SoCs manage them—and the equation gets even more compelling.

What’s intriguing here is the understanding of what constitutes a system. Energy is a
a global concern in system design—it affects every part of a system. But with systems now defined on a much larger scale, the question now is exactly what is a system and how far the savings can reach.

Consider a program at Santa Clara University in Silicon Valley, for example. The school is developing a high-efficiency solar absorber/exchanger. The school’s mechanical engineering department also has applied some of that capability to clothes dryers, which it claims are the most inefficient appliances in the house. The heat exchanger recycles hot exhaust air back into the dryer. And the school has received an EPA grant for a fuel cell that is capable of continuous energy output.

The Rochester Institute of Technology, meanwhile, is designing a hydrofoil system that harvests energy from a river.

And the University of California at Riverside is designing a solar collector to heat ambient air for home appliances such as clothes dryers and space heaters to reduce home energy consumption.

There are many more examples on the EPA’s list. But the good news is that it’s not just the over-40 engineers who are working on this stuff anymore. The pipeline is full, and the number of new possibilities for commercially viable solutions is growing.

However, one current challenge is in manufacturing at low cost in ambient conditions. In order to create light or energy by injecting or collecting electrons, printed electronics require conductors, usually calcium, magnesium or lithium, with a low-work function. These metals are chemically very reactive; they oxidize and stop working if exposed to oxygen and moisture. This is why electronics in solar cells and TVs, for example, must be covered with a rigid, thick barrier such as glass or expensive encapsulation layers.

But Georgia Tech researchers have introduced what appears to be a universal technique to reduce the work function of a conductor. They spread a very thin layer of a polymer, approximately one to 10 nanometers thick, on the conductor’s surface to create a strong surface dipole. The interaction turns air-stable conductors into efficient, low-work function electrodes. The commercially available polymers can be easily processed from dilute solutions in solvents such as water and methoxyethanol, are inexpensive, environmentally friendly and compatible with existent roll-to-roll mass production techniques.

After introducing what appears to be a universal technique to reduce the work function of a conductor in printable electronics, a team led by Georgia Tech's Bernard Kippelen has developed the first completely plastic solar cell. (Source: Georgia Tech)

Bernard Kippelen, director of Georgia Tech’s Center for Organic Photonics and Electronics said, “Replacing the reactive metals with stable conductors, including conducting polymers, completely changes the requirements of how electronics are manufactured and protected. Their use can pave the way for lower cost and more flexible devices.” To illustrate the new method, Kippelen and his peers evaluated the polymers’ performance in organic thin-film transistors and OLEDs and have built a prototype of the first-ever, completely plastic solar cell.

–Ann Steffora Mutschler

An individual bio-solar cell. (Source: Vanderbilt University)

The large-scale biohybrid solar panel for power production is made up of many individual photoelectrochemical cells that employ photosynthetic proteins as the active elements for light-harvesting and energy conversion. A miniature bio-cell can produce minute electricity from Photosystem I (PSI), the protein in plant chloroplasts that converts light to electrochemical energy. The team extracted PSI from spinach and used it as the working medium in the bio-photovoltaic cells. The two scaled-up panels consist of 24 cells connected in series with each cell measuring 75 x 38 mm.

The researchers standardized a production and assembly scheme that can serve as a footprint for future scale up of next generation cells, which has not been attempted previously.

For their work, the researchers won a Phase II $90,000 grant at the 8th Annual National Sustainable Design Expo held at the National Mall in Washington, D.C., co-sponsored by the U.S. Environmental Protection Agency. The students – Eric Dilbone, Phil Ingram, Trevan Locke, Paul McDonald and Jason Ogg – had won a Phase I $15,000 grant in November from the EPA for their bio-inspired solar panel. Dilbone and Ingram are senior mechanical engineering majors; Locke, McDonald and Ogg are senior chemical engineering majors.

The funding will allow the team to work on the research aspects of achieving the higher energy conversion goals for the individual cells.

Viruses Convert Mechanical Energy to Electricity
The futuristic concept of charging your cell phone as you walk is a bit closer to reality with a paper-thin generator embedded in the sole of your shoe developed by scientists from the U.S. Department of Energy’s Lawrence Berkeley National Laboratory. The Berkeley Lab scientists developed a way to generate power using harmless viruses that convert mechanical energy into electricity.

To test their approach, the scientists created a generator that produces enough current to operate a small LCD that works by tapping a finger on a postage stamp-sized electrode coated with specially engineered viruses, which convert the force of the tap into an electric charge.

This generator is the first to produce electricity by harnessing the piezoelectric properties of a biological material, the scientists said. Piezoelectricity is the accumulation of a charge in a solid in response to mechanical stress.

The bottom 3-D atomic force microscopy image shows how the viruses align themselves side-by-side in a film. The top image maps the film's structure-dependent piezoelectric properties, with higher voltages a lighter color. (Source: Berkeley Lab)

This discovery could lead to tiny devices that harvest electrical energy from the vibrations of everyday tasks such as shutting a door or climbing stairs and point to a simpler way to make microelectronic devices since the viruses arrange themselves into an orderly film that enables the generator to work.

—Ann Steffora Mutschler

For reasons of digital scalability thanks to Moore’s Law, handset developers traditionally have focused on the processor and transceiver designs. The radio frequency (RF) front-end was seen as a specialty area best left to the black-art world of analog design. But consumers demand ever-smaller, lower-power handsets with increasing feature sets and performance. This means the RF front-end must move away the discrete analog component chains that are needed to support a broad range of carrier frequencies, especially with the advent of 4G and LTE. But what can be done?

Like the digital world, the answer lies in both software and CMOS-based hardware. But instead of transistors as in the digital world, RF front-ends will use micro-electro-mechanical systems (MEMS) as the enabling passive technology. MEMS have been around for several decades. These mechanical structures tend to be oriented to specific products and applications, which meant very customized solution using a very customized fabrication process. This is one reason why MEMS have not been widely adopted.

Today, things are different. Over the last five-plus years, MEMS companies have begun to move away from the customized development paradigm to a scalable CMOS-based model. In so doing, these companies have taken advantage of the large manufacturing infrastructure enjoyed by the digital CMOS community.

The timing of such a move couldn’t be better, with continued strong growth in the global cellular handset. The Navian Market report predicts RF fronts-ends to grow from 488 million in 2010 to 2,826 million units in 2020 – including Advanced LTE, LTE and UMTS systems (see figure 1). Each of these handsets will consist of a chain of discrete RF components for every supported frequency band. Today, the build of material (BoM) for the RF components costs about $8 to $12 US. That amount will rise significantly over the next couple of years with the new frequencies modes require by 4G and LTE operations. Tablets, readers, laptops and other wireless devices will also be affected.

Figure 1: Navian report predicts strong growth for RF front-end modules.

What will be required for RF front-ends to meet the demands of 4G? The increase in component chains must be balanced by shrinking handset sizes. This means that all of the discrete RF components around the transceiver needed to down-convert a wireless signal to the digital baseband domain must be modularized. These components perform functions of power amplification, filtering, impedance matching, and more. Modularizing these analog chains is a complex task that requires trade-offs in RF performance.

“Fast forever to fully employed 4G architectures and theoretically that number will rise to 43 chains in the front-end of every globally-enabled handset,” said Jeffrey Hilbert, president of WiSpry. Today’s handsets typically have 5 to 8 RF component chains. That’s a lot of hardware—too much so for handsets that are continually shrinking in width.

In addition to getting thinner, handsets are becoming dominated by the display. The trend in handset design is to increase the screen size by the bezel and keyboards. While great from a user interface perspective, this trend is bad for RF systems due to antenna placement. For example, removing the keyboard means that the display must be touch screen. But touch screens have metal plates behind them, which interfere with antenna performance.

Other problems abound, ranging from handset OEM supply chain issues to special material restrictions in the front-end components.

The traditional answer to most of these challenges has been to integrate more functionality at the board-level. For example, several discrete filters have been packaged into one module so the handset OEM has a smaller BOM and fewer insertions on the board. Moving to module-level integration is a step in the right direction, but even more integration is needed. In today’s 3G and even 4G system architectures, there are still separate digital basebands and transceivers components, not to mention numerous structures in the RF front-end (see Figure 2)—from low noise amplifiers (LNA) and power amplifiers (PA) to filters and duplexers.

Figure 2: Typical functional architecture for today’s 3G and 4G handsets.

In the near future, basebands and transceivers will be integrated together as multicores on the same die. A similar consolidation will have to occur on the RF front-end to meet consumer form-factor desires, lower power and 4G-LTE multi-radio operations.

Ever-smaller form factors present real problems for the radio antenna. Today, there is typically less and 1cc of space available for the main antenna in a cell phone. This is particularly challenging from the perspective of electromagnetic design since so many structures can interfere with the antenna’s performance. Additionally, LTE deployment in the US will occur in lower frequency bands, which generally require larger antennas. The net result is that antenna design is getting more complex.

This is where MEMS are helping. MEMS are tiny mechanical structures built on the surface of CMOS wafers. They are controlled by software to perform the same analog functions as much larger discrete analog components. For example, WiSpry MEMS are built on a 0.18 micron CMOS process, fabricated on 8-inch wafers by IBM Microelectronics. These devices function as an array of tunable RF passive components (see Figure 3). Each of the individual mechanical elements in the array is separate from the others and is independently addressable. Designers can connect the cells together on the single die or in a package as individual pieces. Arranging these individual cells allows designers to create tunable RF devices used in filters, power amplifiers, antenna tuners, impedance network matching and general purpose capacitors.

CMOS tunable filters will help reduce power consumption by decreasing the number of inactive yet current drawing discrete components. More power will be available to drive the antenna with less power being wasted as heat in components.

Figure 3: MEMS cells are programmable and can work independently on a die.

In the near future, such MEMS devices will be reconfigured in real time by software running on the baseband processor. Real-time processing is needed to maintain the low latency required to adjust the RF properties of power amplifiers and filters. “In some sense, we will be virtually emulating the hardware components that we’ve replaced by making these programmable components using the MEMS devices,” explained Hilbert. “That is where the RF adaptability comes in.” While this goal has been realized in the lab, for now discrete components are implemented in the handset marketplace.

MEMS in CMOS are not without shortcomings, especially in terms of latency. One of the disadvantages of MEMS is they are slow compared to the speed of transistors. For a small fraction of the market applications, this may be a problem.

Where are MEMS being used today? For the most part, in microphones and sensor arrays for motion sensing accelerometers and gyros. These sensors perform the magic that tell the handset to turn off the display to save power when the phone is placed next to the user’s head. MEMS gyros are begin to find use in camera stability subsystems and handset pico-projectors.

Where will MEMS be used in the future? For front-end architectures, Hilbert foresees MEMS devices physically attached to the antenna to affect different resonant modes. This will save size and power. Another trend will be the usage in a variety of different filters, from duplexing for Wideband-CDMA to notch and bandpass filters.

Power amplifiers will also be improved with MEMS (see Figure 4). Programmable structures will improve the efficiency of power amplifiers and provide impedance matching so less power has to be driven across the handset. This will decrease wasted energy lost as heat.

Figure 4: Tunable RF front-end power amplifier using MEMS technology.

CMOS is not the only approach to creating MEMS. Other technologies include Barium Strontium Titanate (BST) ferroelectric thin films, GaAs-based and Silicon-on-Insulator (SOI). Each technology has its advantages and disadvantages in terms of the key tradeoffs of capacitive change, RF quality factor, and controllability. WiSpry uses CMOS MEMS to create digital capacitors. Partec employs BST technology for analog variable capacitors. Sony uses GaAs-based for its switched passives. Perigrine Semiconductor is an SOI-based implementation of switched passives—using Safire. (see, “Noble Award Honors Low-Power RF Technology” (http://chipdesignmag.com/display.php?articleId=4977&issueId=43

Choosing the best technology for a given application is tricky. The scale of the RF front-end market is large so potential customers is reluctant to change. The best approach may be to appeal to the entire RF ecosystem, from consumers to carriers and handset OEMS. Each has their own needs. Consumers want longer battery life (lower powered devices), better performances, and global connectivity—all at a cheaper cost.

Carriers want to avoid capital expenditures by lowering their infrastructure costs. One heuristic is the decibel (dB) change. To realize 1 dB change in performance improvement, a carrier’s network would require 14% more cell sites. This translates into several million dollars in capital expenditures, which can be a huge cost for the carriers.

Handset OEMS want improved power efficiency and RF performance gain with decrease BOM cost and supply complexity.

Tunable RF (CMOS) MEMS will not solve all of the consumer, carrier and OEM needs. But MEMS does balance many tradeoffs, especially where battery life and form factor are concerned, in next-generation 4G (LTE) wireless systems.

In addition, at sub-65 nm process nodes, different biasing techniques are being combined with power gating in order to minimize leakage power. Employing low power techniques, such as power gating and substrate biasing, gives rise to many thorny verification challenges. For example, are the power control sequences correct; is my biasing strategy functionally correct; do the “awake” portions of the design still function correctly when other domains are powered down; is adequate state information retained when state retention is employed; is the proper retention protocol followed; and is my isolation strategy functionally correct.

To download this white paper, click here.

To put it in perspective, when CPF and UPF were first introduced power was something of an afterthought in design. At 65nm it ceased to be something that could be dealt with later in the design process, and at 28nm it has become an essential part of the architecture. But as battery life, mobility, and energy costs even for plugged-in devices become overriding concerns, power now needs to be considered at full system level, which could mean everything from a rack of servers to an automobile.

Much of this is being driven from the chip level, and in the software that manages chips and interactions between chips. There are at least a half dozen new standards efforts under way or on the drawing board. Most heavily leverage the expertise of chipmaker and where they have encountered or expect to encounter pain in designs, most notably in stacked die or in planar SoCs below 20nm, or from tools vendors that have gained expertise in a specific area.

Si2 currently has one standard in legal review for system-level power modeling. The standard is called “atomic” power modeling, based on the assumption that the model cannot be broken down into smaller pieces, although it can be used at various levels of abstraction.

Also in the works is a standard for co-design, which is one of the most difficult challenges facing design today. While hardware engineers are well versed in how to build an energy-efficient chip, that engineering effort can be wasted if the software running on an SoC isn’t energy-efficient, as well.

“The first step is to get there with the architectural ESL level,” said Steve Schulz, president and CEO of Si2. “Then, we will look at how the software runs and develop a bridge. You will never get the software community to adopt the hardware approach to design. That community is 20 to 30 times larger than hardware engineers and they have their own tool flows. We have to think about a minimally intrusive solution. We’ve called it a bridge to the software world, and if it’s not intrusive then the software teams will use it. Most of them will never understand concurrency and how to get to a GDS II stream, but there are characteristics that are reasonable proxies of the details. You don’t simulate all the code, but you do generate enough discrete choices so everyone can get on the right track for power.”

A first step in that direction is finding data objects that can be passed back and forth between the software and hardware teams. From there a power model will need to be created across both. The power-flow group within Si2 has been reactivated to develop a source for the power model. “The focus this year will be hardware,” said Schulz. “In 2013 we will turn our attention to understand the data objects stored.”

That puts the likely adoption timeframe a of a co-design framework for power in the 2015 time frame—roughly at the 14nm process node and at a time when 2.5D stacking is expected to be mainstream and 3D stacking will become more commonplace.

Stacking effects
“There are two new requirements for design,” said Andrew Yang, president of Apache Design. “The first is a 3D IC flow. The second is an RTL-to-gate power methodology.”

Included in the 3D requirements is the need for multi-die thermal and stress analysis. Yang said the key is the amount of current a design can sustain without failure over time, and it gets worse at advanced nodes and sometimes in stacked configurations because wire handling capability is decreasing, power density is increasing, and electromigration is increasing.

3D IC thermal stress analysis. Memory die is impacted by power distribution of logic die. Source: Apache Design.

“This can be a safety issue,” he said. “You need to make sure the metal topology is handled correctly. Electromigration is affected by heat. The hotter it gets, the less current a metal wire can sustain. The electromigration rules are increasing, which is why GlobalFoundries, Intel and TSMC are all coming up with complex electromigration rules.”

Front to back, back to front
Being able to get a chip out the door at all is a challenge, which is why there are more standards being dictated from the foundries these days. In addition to process variation, continually shrinking geometries is making it harder to obtain adequate yields as quickly as in the past. That has led to more rules for place and route, test, IP, and layered across all of those is power.

“We’re seeing it in the available sizes, speeds, memory and logic cell sizes,” said Chris Rowen, CTO at Tensilica. “That’s what we target—area, power and process compatibilities. Whether that’s stacked or conventional die is affected only subtly. But with die stacking you will see significantly higher bandwidth and less latency, which will have an effect on modeling of the system. It’s not a qualitative change, but it is a quantitative change. It won’t change how one DSP communicates with another, but it will change how DSPs communicate with memory.”

How much of that will be standards promoted by standards bodies versus de facto standards from the largest foundries remains is unknown. Also missing are good open standards for on-chip debug and trace, said Rowen.

ESL standards
One of the most glaring holes in all of this is at the ESL level, where standards for power models are non-existent. While this isn’t a big problem in a single vertically integrated company, it’s a huge problem in a disaggregated supply chain where various companies work on designs—something that will become even more pronounced in stacked die where subsystems at different process geometries need to be integrated with other subsystems.

“What’s missing is something that allows companies to exchange power models, especially for IP-based designs” said Ghislain Kaiser, CEO of Docea Power. “In an ideal flow you would be able to take the IP from the IP suppliers and put together a power model and assess the power impact on the underlying hardware. But you also need to have interoperability between suppliers and customers that goes beyond the semiconductor level. It has to be optimized at each level—the SoC, the chip set, the PCB and above. So there won’t be only one number.”

The accuracy of those power models also will shift throughout the design. At the beginning a model may be only 40% accurate, but at the end it may need to be accurate to plus or minus 5%, Kaiser said.

Other pieces are missing, as well. Kiran Vittal, senior director of product marketing at Atrenta. “Right now, when a designer uses memory they don’t realize the code they are writing is not optimized for power. When you read memory you get a redundant read. The controller code isn’t optimized for memory. And all of that has to be networked, because you may have as many as 2,000 memories in a design. If you do it right you can save about 20% of the memories and the power needed to run them.”

To show just how bad this can get, a large systems house was designing a chip was required to give an early indication of its power budget to the OEM. The OEM used that estimate for calculating its own power budget and came up with a spreadsheet that represented the total design. The problem was that the spreadsheet ultimately was off by 100% in its power estimate, which in turn caused problems with the final device and greatly increased the amount of time it took to successfully bring a product to market.

“A lot of the ESL tools today know performance and area, but they don’t have a clue about power,” said Vittal. “This is fertile ground for innovation.”

Back in the early days of semiconductor design engineers could count the number of transistors on their chip with their own two eyes. They designed and worked at the same level of design abstraction when doing the timing analysis. Tools were SPICE-like, maybe abstracted with slightly simpler timing models than the SPICE-level transistor models.

Thanks to Moore’s Law, the number of transistors that can fit on a chip has grown to the billions, which obviously can’t be counted with the naked eye. But they also no longer scale with SPICE. Abstraction has been the way out by providing a higher-level view on the design.

“Clearly, even when I’m at gate level, I know I’m not getting the same accuracy that I would be getting at SPICE level, but if my models are good enough and it is close enough, I’m willing to take that slight hit to be able to do bigger designs,” noted Barry Pangrle, a solutions architect for low-power design at Mentor Graphics. “That’s the progression that we’ve gone from—transistors to gates. Then people were doing schematic capture and everything was gate-level models. Then we went to RTL and we started moving to RTL models. Now we are moving on into system and bigger components and functional blocks. At each level, we’re giving up some measure of accuracy—it’s just not going to be as detailed. It’s not going to be as fine-grained and the hope is though that we have enough information that we can make the decisions at that level of abstraction.”

The abstraction levels in use today were developed over a long period of time. They are well-defined because a huge amount of work was done in terms of both modeling, to make sure we can move between levels, and to ensure there is the appropriate level of detail to accomplish what needs to happen in that level.

“Today, we’ve tuned it and created enough modeling around it so we can get the information that we need out,” said Cary Chin, director of technical marketing for low-power solutions at Synopsys. “But I would say that the model isn’t general enough if we thought of some new use of these connections and voltages and expected it to give us the data that we wanted. Whereas if you did that all in SPICE, it likely would [provide the right data] because that’s one indication of the maturity of the model—whether you can use it for things that weren’t anticipated originally when you built the model.”

At the RTL level engineers synthesize down to a gate-level netlist so that they can bring in their gate level models, Pangrle said, with the hope that based on the information they get from those models, they can create something that’s going to be representative of what they need at the RTL level. “Now we’re looking at going one level beyond that and saying, ‘Okay, at the next level of abstraction what kind of information can we capture here?’ The tricky part is making sure that you still have the level of accuracy that you need to be able to make the types of design decisions that you’re going to rely on that information.”

But these levels of abstraction are not all fun and games. For engineering teams doing low-power designs, there are many challenges moving between these different design abstraction views, the biggest one between the RTL to gate because these two abstraction levels have too many big differences, explained Qi Wang, technical marketing group director for low power and mixed signal at Cadence. “On top of that, there is a lot of handshake of tools between those two levels.”

For example, he said an important aspect of low-power design is to gather activities. RTL simulation is run to collect activity, so all of the signal activity is annotated along with all the signal names. The engineer hopes to re-use that activity at the gate level, but the problem is the name seen at the RTL may not be the name seen at the gate level because the synthesis tool renames the files.

Power formats

In addition to this renaming, a lot of optimization can happen between the RTL and the gate level, which means that some signal may simply optimize out. Another possibility is that the logic may not optimize out but the representation can be changed, Wang said. “On the activity side, this is a flow challenge. The activity file you get for the RTL you hope you can re-use for the gate level, but many times you will find it is very difficult.”

Another kind of difficulty involved is with the power format, no matter what standard is, Wang noted. “The whole idea is that you describe your power intent in another file… If you write a power format file for RTL, which means it will be used for the RTL so all the names you refer to would be the RTL names. Now when you get to the gate level you hope you can use the same RTL level power intent because I want to keep my golden power intent through the design and verification flow.” But this will have the same problem as in the activity file.

To address this formal verification techniques can be used to indicate which RTL register names map to the corresponding flip flop on the netlist with a name-mapping file.

Then on the power intent side, he suggested the easiest way to deal with the renaming issue to have the synthesis tool write out a new power intent file, which automatically will reflect the name changes and the hierarchy ungrouping. When it comes to enabling the flow, however, the power intent written out by the synthesis must be equivalent to the original power intent, which is where power-aware equivalence checking tools are utilized to prove that the new power intent and the old power intent are equivalent.

Twenty years of hard labor

Traditionally, traversing levels of abstraction has been relatively straightforward—it’s just a lot of work. “If you look at the library modeling process that has evolved to go from kind of transistor level to gate level, things are very well defined today,” Chin said. “Libraries are super solid and vendors know how to characterize things even as the technology changes. That’s an example of a level of abstraction that’s pretty mature because over the last three, four or five generations of technology, we haven’t had to make major changes. There have been many, many little extensions and timing models and functionality and things like that but basically since we haven’t changed the fundamental design flow, the models and libraries have stayed pretty much the same, which is great.”

There have been similar advances in synthesis. “If you look at this between RTL and gate level, synthesis has changed a lot over that time, as well, but in general if you couple synthesis with verification tools and formal verification tools, things have actually grown nicely so that we still have very dependable flows that most people are still pretty happy with. You can push the button and trust what comes out at the other end. And as you recall, it took us 20 years to develop that level of trust,” he concluded.

Once the engineering community moves en masse to the system level, that 20 years could easily be duplicated.

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“These are certainly not new phenomenon,” said Carey Robertson, director of product marketing for Calibre at Mentor Graphics. “We’ve had to wrestle with them for some time. Fifteen years ago when I was doing microprocessor design at 0.35-micron at DEC (Digital Equipment Corp.) we had an electrical migration budget and the reason for that requirement was that DEC—which put chips into VAXes and things that would do your financial statements—essentially had budgets that said our chips will last 10 years and expected 1%t of them to have failures due to EM.”

That type of requirement was never applied to the mobile market because devices aren’t expected to last that long, and fabless companies historically have not been particularly concerned about EM. Automotive companies have been a different story because cars are expected to last for a decade or more. That’s all changing as designs scale and chips get smaller and smaller, however.

“There was an inflection point some time ago when we switched from aluminum to copper—at about the 65nm/40nm process node,” Robertson said. “The characteristics of copper made them much more robust against electromigration, so we bought ourselves a couple of generations of time. At 28nm and 20nm, the wires are now thin enough that regardless of the chip, they are running at very high frequencies so electromigration is a concern for nearly any type of designer, not just for those who expect their chips to last 10-plus years. It’s a concern for those who expect them to last one to even five years. It really gets down to the scaling of the geometries and why it’s such a concern.

ESD and EM require analysis of power/ground nets at the full-chip level. Source: Mentor Graphics

Smaller nodes magnify electrical effects
When the design moves to advanced nodes, reliability becomes one of most important challenges. Reliable chip operation increasingly is affected by environmental conditions, such as electrostatic discharge (ESD), electromagnetic interference (EMI), and soft error rate from radiation (SER), and these things could even damage devices on a chip, according to Tianhao Zhang, senior product marketing manager at Cadence. “In the meantime, the multiple power domain application requires the appropriate signal protection to make a device work, which is more susceptible to ESD.”

Arvind Shanmugavel, director of applications engineering at Apache Design said in terms of electromigration, the single biggest driving factor for making things more complicated is process migration. “What we have noticed over time is the transistor drive strength has almost remained constant over the different technology nodes, meaning they can push out the same amount of current from 65 to 40 to 28 and even going down to 20nm, but the wire geometries have decreased over these generations. The wires have become thinner and they have decreased in overall geometry sizes and the EM limits for these wires have also decreased over these different technology nodes. The EM limit is essentially how much current can be pushed to a unit area of metal for a particular technology node. This depends on the metal properties and so on. We have noticed that those limits have also decreased with technology migration.”

ESD on the other hand, is an event-based failure. Technology migration as well as design styles have affected ESD design. In terms of technology migration, ESD needs to be designed within the operating window of device breakdown and normal operation. “As we move from one technology node to another, our device breakdown characteristics have drastically decreased, meaning that the drain-to-source breakdown, the gate-to-source breakdown voltages have drastically decreased but the operating voltage of ICs has not really changed that much,” he said.

Interestingly, Mentor’s Robertson said some fabless semiconductor companies aren’t necessarily so concerned with reliability of chips over a 5- to 10-year span and equate ESD failures to yield issues/the cost of doing business. ‘It’s a hard problem so we’re willing to lose a couple of percent due to this simply because it’s difficult to verify or difficult to protect against.’ However a greater and greater portion of your circuit is going to be susceptible to ESD failures. The oxides of your transistors are so small these days that it’s not just a human with a large piece of static electricity that’s a concern, it is potentially what we would consider rudimentary voltages in the past not dissipated correctly and blowing the oxides of a delicate 28nm or 20nm oxide. A larger portion of the chip could fail due to these events and so there’s been a push for new techniques.”

New techniques fall into a couple of camps, none of which are really new. “Since the beginning, we’ve always been able to simulate. We could always run circuit simulation for electromigration or ESD. The problem, however, is as these chips get bigger, this really requires a transistor-level simulation, and transistor-level simulators cannot accommodate today’s chips because of the size of the designs–multi millions, billions of transistors. In order to do this appropriately, you need a transistor-level simulator. Even the best Fast SPICE tools are not going to accommodate today’s designs. And static timing, while people are doing full chip static timing sign-off, with these ESD, electromigration issues many times you need to go down to the device level. At 20nm, you need to have even more stringent rules that identify what’s possible or not [with EM] and I think you have to be more sophisticated with your analysis. For ESD I don’t think it changes all that much because you’re trying to find out which are the sensitive devices and what they can tolerate, and then if there are protection devices that will accommodate the charge or currents that are possible. It’s essentially a math problem.”

Cadence’s Zhang said a new industry approach called design for reliability is emerging, which consists of adding more protection to minimize or even solve the impact of ESD and EM. However the verification this protection is extremely challenging. Right now most of design houses do the verification manually by experts, which has the significant risk of missing design flaws.

Cadence, Apache, Mentor Graphics, Synopsys and others provide tools here to help designers automatically verify their designs.

Looking ahead
Solving full-chip challenges for reliability are very interesting because, “when you put more components on the same die or when you put more dies in the same package, you’re affecting the reliability behavior of that system,” Apache’s Shanmugavel said. “With IC integration, for example, we have seen a lot more IPs being integrated on the same piece of silicon and that really effects the ESD design of the full chip. Because every IP has its own power delivery network and for each PDN, we need to have ESD protection devices protecting the power, the ground and the signal nodes associated with that particular domain. With the increasing number of IPs being used today comes an increasing number of voltage domains. Similarly with the increasing number of voltage islands for low-power design comes a higher complexity of verifying ESD protection for all these domains.”

ESD has to be verified not only on every domain but must also be checked cross-domain. This means that between every power domain and any other domain on the chip, there must be some kind of an ESD protection to make sure that there is a reliable discharge path of current during an ESD event. “This is no longer possible by visible checks. ESD is one of those art forms where people have visually looked at a layout and qualified that it’s ESD ok. But that’s no longer going to be possible—it has to be translated into a rule-based check and not just an art form,” he explained.

“The ESD limits have not really changed over time — it’s the same ESD standard that we’ve been using for the last 25 years but the geometry sizes have obviously gone down quite significantly, so pushing the same amount of ESD current through the geometries and the geometry sizes going down, there is a higher propensity to metal burnout. That is a huge aspect in terms of ESD verification that has to be available in your analysis platform,” Shanmugavel concluded.

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