Comments for VoltEdge http://chipdesignmag.com/lpd/kapoor Making Semiconductor Architectures More Efficient Tue, 25 May 2010 22:45:55 +0000 hourly 1 http://wordpress.org/?v= Comment on Why So Formal? by Tom Anderson http://chipdesignmag.com/lpd/kapoor/2010/05/21/why-so-formal/comment-page-1/#comment-109 Tom Anderson Tue, 25 May 2010 22:45:55 +0000 http://chipdesignmag.com/lpd/kapoor/?p=109#comment-109 Bhanu, good summary on the use of formal techniques for low-power verification. I'm not sure that I understand your distinction between assertion checking and model checking. For example, safety of a power management scheme can be verified by assertions ensuing that the total number of powered-up domains does not exceed the input power capacity or trigger thermal runaway. Our customers often do this as part of using assertions and formal to verify proper sequencing of power-control signals. Are you perhaps using "model checking" to refer to formal analysis using some form of specification not in the form of assertions/properties? Thanks. Tom A. Bhanu, good summary on the use of formal techniques for low-power verification. I’m not sure that I understand your distinction between assertion checking and model checking. For example, safety of a power management scheme can be verified by assertions ensuing that the total number of powered-up domains does not exceed the input power capacity or trigger thermal runaway. Our customers often do this as part of using assertions and formal to verify proper sequencing of power-control signals. Are you perhaps using “model checking” to refer to formal analysis using some form of specification not in the form of assertions/properties? Thanks.

Tom A.

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