Often, designers have experience with the design, or the process or (ideally) both, and they know timing closure may be difficult for certain modules. In this case, our RTL power estimation can be “precalibrated” to account for the higher drive cells or higher power microarchitectures in these areas. For designers who are working on a brand new design in a brand new technology, there is no “magic bullet” which will perform highly accurate estimation purely from the RTL. Early estimates will still have value, but “calibration” information can be added as trial synthesis results are done. This improves the accuracy.

Even for designers who have no “calibration” information, our RTL power estimation is highly valuable to guide designers. If there are two possible architectures, designers can quickly and easily estimate both architectures. One will often have much better power behavior. Waiting until fine-tuned, highly accurate gate level estimates are available is too late; by that time, only the smallest design changes can be made. Similarly, investigating the power behavior early in the design process can uncover “power bugs” such as modules which are still fully clocked in idle mode. Many designers consider this early feedback to be a requirement for the lowest power designs.

Our customers have told us that “estimate early, estimate often” is the best approach to ensure the best power architecture with no power bugs. This can be augmented by very late stage, highly accurate gate level estimates; but the ability to do early power estimates should be part of every designer’s toolbox.

- Dave Allen is the engineering director for power products at Atrenta