Comments for Power Awareness http://chipdesignmag.com/lpd/mutschler Making Semiconductor Architectures More Efficient Thu, 07 Oct 2010 18:37:04 +0000 hourly 1 http://wordpress.org/?v= Comment on Connecting IP Blocks by David Murray http://chipdesignmag.com/lpd/mutschler/2010/10/07/connecting-ip-blocks/comment-page-1/#comment-74 David Murray Thu, 07 Oct 2010 18:37:04 +0000 http://chipdesignmag.com/lpd/mutschler/?p=39#comment-74 IP-XACT doesn't have any standard provision for capturing power information. The IPXACT technical committee has been reformed under Accellera recently and are going through a rapid requirements gathering session so if anyone is interested in championing power extensions then...... get on to Accellera quickly! I did an IPXACT survey recently and people thought that power extensions are an important part of the evolution of the standard. It will be interesting to see how both UPF (Unified Power Format) and IP-XACT will evolve as they are both under Accellera.--Dave Murray IP-XACT doesn’t have any standard provision for capturing power information. The IPXACT technical committee has been reformed under Accellera recently and are going through a rapid requirements gathering session so if anyone is interested in championing power extensions then…… get on to Accellera quickly! I did an IPXACT survey recently and people thought that power extensions are an important part of the evolution of the standard. It will be interesting to see how both UPF (Unified Power Format) and IP-XACT will evolve as they are both under Accellera.–Dave Murray

]]> Comment on Optimizing Physical IP For Applications And Processors by Raj Nair http://chipdesignmag.com/lpd/mutschler/2010/05/13/optimizing-physical-ip-for-applications-and-processors/comment-page-1/#comment-12 Raj Nair Thu, 13 May 2010 19:59:36 +0000 http://chipdesignmag.com/lpd/mutschler/?p=15#comment-12 If it's all about power, then it's very much the operating voltage... a fundamental means to reduced power is lowered voltage. Just as clock-gating is a means to bring average clock frequency down, for a linear benefit in P=CV^2f, power gating, common in SoC's today, brings the average operating voltage down, gaining quadratically in power. Bringing the nominal operating voltage down while maintaining performance requires careful attention to POWER INTEGRITY... this is the next critical design challenge that impacts chip resource and physical IP optimization. A book on this topic: http://www.informit.com/title/9780137011223 If it’s all about power, then it’s very much the operating voltage… a fundamental means to reduced power is lowered voltage. Just as clock-gating is a means to bring average clock frequency down, for a linear benefit in P=CV^2f, power gating, common in SoC’s today, brings the average operating voltage down, gaining quadratically in power. Bringing the nominal operating voltage down while maintaining performance requires careful attention to POWER INTEGRITY… this is the next critical design challenge that impacts chip resource and physical IP optimization.

A book on this topic: http://www.informit.com/title/9780137011223

]]> Comment on New x86 Technology For The Datacenter? by Power Awareness » Blog Archive » Optimizing Physical IP For Applications And Processors http://chipdesignmag.com/lpd/mutschler/2010/03/11/new-x86-technology-for-the-datacenter/comment-page-1/#comment-11 Power Awareness » Blog Archive » Optimizing Physical IP For Applications And Processors Thu, 13 May 2010 18:10:24 +0000 http://chipdesignmag.com/lpd/mutschler/?p=9#comment-11 [...] a separate note, following up on my first post, it turns out that the ’silicon innovation’ referred to by IBM is the company’s [...] [...] a separate note, following up on my first post, it turns out that the ’silicon innovation’ referred to by IBM is the company’s [...]

]]>