Power verification often meanders into talk of the di/dt voltage drop across inductors. A high level water cooler primer of such topics ensues.
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On the surface, the Internet of Things theme of IDF2013 was a good umbrella over Intel’s stated goal of “leading in all the segments” where the company plays. According to CEO Brian Krzanich, this includes portables, smartphones, tablets, ultrabooks, desktops, server/enterprise and a new category Intel’s coining called “2 in 1 convertibles.” The Intel Advantage is all about systems integration, and it’s one the company started at the chip level and can now exploit at the system level in these new product categories. And there was (finally!)a healthy dose of product announcements around security—with concrete and substantive details on how vPro will strengthen the enterprise and Windows-based devices.
John Blyler from Extension Media interviews Jell De Smet, a senior researcher on smart contact lenses, Centre for Microsystems Technology (CMST), imec and Ghent University. This video was shot during the Imec Technology Forum in Oct. 2013 in Leuven, Belgium.
- San Kun: Nice Article
Jim Kobylecky Besides, eating a coding rivet from time to time has to be a whole lot less painful than the alternative. Hmm,...
jblyler Hi Steve. Thx for the correction. I mentioned it to the editor and updated the post. Cheers. -- John
Windy Windy... DAC 2013 Pictures | JB's Circuit...
stevesliva Fab 8 in NY is GlobalFoundries, not Samsung. But they are qualifying the same process in Korea and Dresden/NY: http://www.globalfoundries.com/newsroom/press-releases/2011-press-releases/2014/03/01/globalfoundries-and-samsung-extend-fab-sync-to-new-high-performance-28nm-technology-for-mobile-applications
Samuel Ye The introduction of common database which are used among chip designers, package designer as well as systel solution...
Rodrigo Gonzalez Mr. Speers, in order to improve your post you should name the sources of all these power data. Best regards. Rodrigo...
Verifying the robustness of secure data access and the absence of functional paths touching secure areas.
How to identify design weaknesses, automatically repair the supply noise source, analyze the impact of dynamic voltage drop and verify power and signal EM.
While formal can be applied to entire blocks, it can be more valuable to apply it within blocks.
Learn more about a design-for-power methodology, from early in the design process at the RTL for maximum impact on power.
What technology and methodology are needed to verify the robustness of secure data access and ensure the absence of functional paths touching secure areas of a design.
A look at the challenges in designing smaller, faster and lower-cost products and how to enable comprehensive chip-package-system benefits across multiple disciplines.
Using the JasperGold low-power verification app to address power-aware verification challenges and requirements and overcome limits using traditional tools.
How to meet smart device requirements with high levels of sophistication and reasonable battery life.
Beginning early in the design process at the RTL level provides the largest impact on power.
Learn how to effectively manage design specifications (performance) and margins (price) with an accurate and predictive simulation-driven chip–package–system convergence methodology.