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Verifying Security Aspects Of SoC Designs

Verifying the robustness of secure data access and the absence of functional paths touching secure areas.

SoC Power Integrity And Sign-Off For 28nm Designs

How to identify design weaknesses, automatically repair the supply noise source, analyze the impact of dynamic voltage drop and verify power and signal EM.

Where Should I Use Formal Functional Verification?

While formal can be applied to entire blocks, it can be more valuable to apply it within blocks.

RTL Design-for-Power Methodology

Learn more about a design-for-power methodology, from early in the design process at the RTL for maximum impact on power.

Verifying Security Aspects Of Designs

What technology and methodology are needed to verify the robustness of secure data access and ensure the absence of functional paths touching secure areas of a design.

Technologies For Power, Signal, Thermal, And EMI Sign-Off

A look at the challenges in designing smaller, faster and lower-cost products and how to enable comprehensive chip-package-system benefits across multiple disciplines.

Formal Verification Of Power-Aware Designs

Using the JasperGold low-power verification app to address power-aware verification challenges and requirements and overcome limits using traditional tools.

Optimizing Cost-Performance-Schedule With A Chip-Package-System (CPS) Methodology

How to meet smart device requirements with high levels of sophistication and reasonable battery life.

RTL Design-For-Power Methodology

Beginning early in the design process at the RTL level provides the largest impact on power.

ANSYS And Apache Technologies For An Integrated Chip-Package-System Flow

Learn how to effectively manage design specifications (performance) and margins (price) with an accurate and predictive simulation-driven chip–package–system convergence methodology.

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