Verifying Security Aspects Of SoC Designs
Verifying the robustness of secure data access and the absence of functional paths touching secure areas.
White Papers Archive
SoC Power Integrity And Sign-Off For 28nm Designs
How to identify design weaknesses, automatically repair the supply noise source, analyze the impact of dynamic voltage drop and verify power and signal EM.
Where Should I Use Formal Functional Verification?
While formal can be applied to entire blocks, it can be more valuable to apply it within blocks.
RTL Design-for-Power Methodology
Learn more about a design-for-power methodology, from early in the design process at the RTL for maximum impact on power.
Verifying Security Aspects Of Designs
What technology and methodology are needed to verify the robustness of secure data access and ensure the absence of functional paths touching secure areas of a design.
Technologies For Power, Signal, Thermal, And EMI Sign-Off
A look at the challenges in designing smaller, faster and lower-cost products and how to enable comprehensive chip-package-system benefits across multiple disciplines.
Formal Verification Of Power-Aware Designs
Using the JasperGold low-power verification app to address power-aware verification challenges and requirements and overcome limits using traditional tools.
Optimizing Cost-Performance-Schedule With A Chip-Package-System (CPS) Methodology
How to meet smart device requirements with high levels of sophistication and reasonable battery life.
RTL Design-For-Power Methodology
Beginning early in the design process at the RTL level provides the largest impact on power.
ANSYS And Apache Technologies For An Integrated Chip-Package-System Flow
Learn how to effectively manage design specifications (performance) and margins (price) with an accurate and predictive simulation-driven chip–package–system convergence methodology.
Videos/Podcasts
Imec-SmartLens
John Blyler from Extension Media interviews Jell De Smet, a senior researcher on smart contact lenses, Centre for Microsystems Technology (CMST), imec and Ghent University. This video was shot during the Imec Technology Forum in Oct. 2013 in Leuven, Belgium.
Recent Comments
- San Kun: Nice Article
Jim Kobylecky Besides, eating a coding rivet from time to time has to be a whole lot less painful than the alternative. Hmm,...
jblyler Hi Steve. Thx for the correction. I mentioned it to the editor and updated the post. Cheers. -- John
Windy Windy... DAC 2013 Pictures | JB's Circuit...
stevesliva Fab 8 in NY is GlobalFoundries, not Samsung. But they are qualifying the same process in Korea and Dresden/NY: http://www.globalfoundries.com/newsroom/press-releases/2011-press-releases/2014/03/01/globalfoundries-and-samsung-extend-fab-sync-to-new-high-performance-28nm-technology-for-mobile-applications
Samuel Ye The introduction of common database which are used among chip designers, package designer as well as systel solution...
Rodrigo Gonzalez Mr. Speers, in order to improve your post you should name the sources of all these power data. Best regards. Rodrigo...
Resource Center
White Papers
Verifying Security Aspects Of SoC Designs
Verifying the robustness of secure data access and the absence of functional paths touching secure areas.
SoC Power Integrity And Sign-Off For 28nm Designs
How to identify design weaknesses, automatically repair the supply noise source, analyze the impact of dynamic voltage drop and verify power and signal EM.
Where Should I Use Formal Functional Verification?
While formal can be applied to entire blocks, it can be more valuable to apply it within blocks.
RTL Design-for-Power Methodology
Learn more about a design-for-power methodology, from early in the design process at the RTL for maximum impact on power.
Verifying Security Aspects Of Designs
What technology and methodology are needed to verify the robustness of secure data access and ensure the absence of functional paths touching secure areas of a design.
Technologies For Power, Signal, Thermal, And EMI Sign-Off
A look at the challenges in designing smaller, faster and lower-cost products and how to enable comprehensive chip-package-system benefits across multiple disciplines.
Formal Verification Of Power-Aware Designs
Using the JasperGold low-power verification app to address power-aware verification challenges and requirements and overcome limits using traditional tools.
Optimizing Cost-Performance-Schedule With A Chip-Package-System (CPS) Methodology
How to meet smart device requirements with high levels of sophistication and reasonable battery life.
RTL Design-For-Power Methodology
Beginning early in the design process at the RTL level provides the largest impact on power.
ANSYS And Apache Technologies For An Integrated Chip-Package-System Flow
Learn how to effectively manage design specifications (performance) and margins (price) with an accurate and predictive simulation-driven chip–package–system convergence methodology.