Part of the  

Chip Design Magazine

  Network

About  |  Contact

White Papers Archive

RTL Design-for-Power Methodology

Having maximum impact requires beginning very early in the design process at RTL.

Technologies For Power, Signal, Thermal And EMI Sign-off

A look at the challenges associated with designing smaller, faster and lower-cost products.

Meeting Emerging Needs For Next-Generation 3D-IC And Sub-20nm Designs

Meeting performance, power and price goals requires new design approaches, including 3D stacked-die architectures.

Power And Signal Line Electromigration Design And Reliability Validation Challenges

A look at the various process and design trends that are increasing the likelihood of EM-induced failure—and what to do about it.

PathFinder Solution For Full-Chip IC ESD Integrity

How to identify weak areas of the layout or circuit that are most vulnerable to ESD failures.

Electronic Power And Thermal Management

A critical engineering challenge for next-generation unmanned systems.

Technologies For Power, Signal, Thermal And EMI Sign-off For Chip-Package-PCB Designs

A look at the challenges associated with designing smaller, faster, and lower cost products and the necessity for an analysis methodology that addresses the cross domain effect in today’s advanced process designs.

Power and Noise Integrity for Analog/Mixed-Signal Designs

A look at the benefits of the Totem platform, its usage model in a design flow and results from simulation and correlation measurements

RTL Design For Power Methodology

Why power budgeting has to start early in the design process to have a significant impact on power.

Power Noise Analysis For Next Generation ICs

New considerations for 3D stacking and for high-performance and low-power circuits.