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The Essentials Of Power Budgeting

By William Ruby

The drive to low-power design has many reasons. A quick look at consumer reviews for the latest smartphones demonstrates the incredible utility of these devices in our everyday lives with a multitude of “pros,” such as Web browsing, video streaming, and cool new apps. And yet, there is one common thread among the “cons” – battery life, or the lack thereof. Cars today have dozens of microprocessors, and the increasing power consumption of automotive electronics is forcing manufacturers to consider 48-volt systems. Data centers have a seemingly insatiable demand for power. Now, more than ever, integrated circuits (ICs) are being designed to stringent power specification limits—or power budgets.

Power budgeting represents a holistic approach to managing power consumption and power integrity throughout the IC design flow, supported by a comprehensive Electronic Design Automation (EDA) methodology. An EDA methodology for power budgeting must address four fundamental issues in order to meet the demands of today’s designs: predictability, efficiency, consistency and integrity.

Predictability enables engineers to understand the power consumption profile of their IC early in the design cycle, as a function of various operating modes and conditions. At the same time, predictability of power integrity on the IC is essential to enable early design of the on-chip power deliver network (PDN) to make it ‘just right.’ That means not over-designed with the associated cost impact, and robust enough to handle the power demand. Moreover, with a suitable modeling technology designers can perform early chip-package-system co-design to explore system-level implications of power.

Efficiency in the design starts with power-aware architectural decisions, and is further improved with ‘power debug’ at the hardware design level of abstraction – at the Register Transfer Level (RTL). Power debug at RTL is an interactive process to find and correct wasted power conditions in the design that are otherwise functionally correct. Power debug in the power budgeting methodology is complemented with automated RTL power reduction, as well as RTL power regressions – a rigorous power tracking mechanism to eliminate unpleasant ‘surprises’ post-synthesis.

Consistency of power consumption analysis throughout the design flow is paramount to the ultimate success of the power budgeting methodology as a whole. Early power analysis, at RTL or above, must be consistent with downstream post-synthesis and post-layout analysis. This consistency, typically with +/- 20% from RTL to layout, is essential to making informed decisions with confidence.

Integrity of the on-chip power delivery network, as well as power integrity on the board and in the system, must be preserved under a multitude of complex functional scenarios. Indeed, low-power design techniques such as clock gating and power gating result in large power gradients – surges that can cause the power delivery network to fail.

The essential elements of the automated digital IC design flow have not changed in more than two decades. Hardware Description Language (HDL) simulation, synthesis, and place-and-route tools form the backbone of this flow. And yet, insatiable consumer demand for “mobile everything” and system power requirements are compelling design teams to expand their EDA portfolios to include world-class power budgeting methodologies.

–William Ruby is senior director of RTL power product engineering at Apache Design Solutions.

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