What’s intriguing about economic downturns is that technology companies race to innovate, but the majority of their customers don’t want to risk using new technology until they’re sure the downturn is firmly behind them.

Nowhere is that more evident than in low-power design. The majority of companies developing complex SoCs still don’t use multiple power island, they don’t build power considerations into the initial architecture and they don’t model power the same way they model transactions.

There are several explanations for why this is happening. One is that while companies are just beginning to get used to the concept of transaction-level modeling, they’re simultaneously adjusting to the realization that you don’t need to understand all the pieces in a design to create a working chip. What used to be a badge of honor in chip design—knowing how everything worked and where the potential problems would be—is a potential weakness in system-level design because it can slow down the process. Low-power design is the latest addition to that equation, because the classic tradeoffs between area and performance have been expanded to area, performance and power.

Second, modeling is expensive. There’s a lot of finger pointing going on about who should create the models—whether it’s the IP vendors, the EDA tools vendors or even the foundries. Some of the largest semiconductor companies have bitten the bullet and created their own re-usable models, but there’s a risk in being too far ahead of the curve in case something changes that could make that kind of investment obsolete. Power modeling can work great, but only if it’s part of an overall modeling approach for an SoC.

Finally, there’s a risk in every new technology. These days, getting it wrong can completely blow a market window. And if companies are investing tens of millions of dollars in developing new chips, they need to be darn certain it will reach tapeout on schedule. Adding multiple power domains can significantly lower the power consumption on a chip, but it requires a change in thinking from the initial architecture all the way to validation and final verification. Accepting these risks is inevitable, because power is so integral to all designs at advanced process nodes, but it’s going to take some time before acceptance is universal.

The good news is that the downturn is drawing to an end after nearly 22 months. That means companies will begin looking ahead to future process nodes and mapping out plans for new chips at those nodes. After that, they’ll have no choice but to figure out how they’re going to manage their power budget and what tools and approaches they’ll need to get there.

–Ed Sperling

Being power-efficient evokes all sorts of images. In the consumer space, it’s a major convenience because it allows users to do more between charges. In the automotive space, it allows people to drive their hybrids or electric cars for greater distances. But in the commercial space, the real attraction is the amount of money it can save.

What drives business is profit. The very image of being green and environmentally friendly is largely a marketing ploy in public corporations. The fact that it benefits the planet is great, but the vast majority of companies would never give it a second thought if it wasn’t in their own best interest—namely saving on electricity costs, or in severe cases, warding off government oversight.

In data centers, which currently consume about 2% to 3% of all electricity in the United States, the big cost is cooling the racks of servers and powering them when they’re not in use, which is why virtualization of applications has become so popular. Most servers have been running at between 5% and 15% utilization, while the cooling costs are skyrocketing. In addition, some software is so inefficient that it keeps the processor cycling even when no one is using the application.

Desktops and laptops, with all their inefficiency—and some of them use as much as 150 watts—don’t compare to the amount of energy required to cool a rack of servers, power it and monitor it. And in places like New York or Boston there are no new power plants being built so power consumption is allocated by the power company. In some cases, even when there is a need for more electricity companies can’t get it.

Variable speed motors and more efficient lighting are the other pieces of the commercial picture. One-speed motors—basically on or off—are about as inefficient as servers running one application even when no one is in the building. And when you have thousands of them—motors or servers, or both—the costs continue to grow with no benefit to the business.

High-intensity lighting has the same effect. It offers no advantage over fluorescent or LED lighting, but it costs more and generates more leakage in the form of heat. The basic incandescent bulb hasn’t changed much since it was invented by Thomas Edison in the late 1800s.

What’s interesting about all of these pieces is the bulk of electronic design is still focused on the consumer space, where the goal is to cut pennies from the price of product. In the commercial space, the goal is to reduce costs by many billions of dollars, but the amount of innovation pales in comparison to what’s going on in the consumer space. While it’s true there are billions of users in the consumer market, the real opportunity in low-power design has barely been tapped.

–Ed Sperling

The annual Design Automation Conference is over, but the consensus of dozens of experts interviewed during the gathering confirms a number of things most experts working in low power may already know.

First, power now defines the SoC as much as the architects define the power envelope. At 45nm and below—and probably even starting at 65nm—power is now one of three factors to consider along with area and performance. Tweak any one of those factors and the other two are affected.

Second, no matter how you much you can automate the first two parts—performance and area—verification gets even worse at advanced process nodes because of power constraints, power islands and various power states.

Third, power trumps performance in battery devices, and increasingly it is as important or even more important in plug-in devices. This is particularly true in data centers, where the cost of cooling racks of servers is sometimes higher than the cost of the machines themselves (figures vary depending on the cost of the power and how much cooling is necessary).

Finally, layout-dependent effects are not always understandable prior to layout at advanced process nodes. In the past the way around this was to increase margins to allow for these unexpected results, but at advanced nodes there is no room for excess margins. Many of those effects are power-related, as in portions of the chip overheating unexpectedly.

And for those engineers and architects who have ignored power-related issues in the past, the next couple nodes may come as a rather unpleasant shock.

–Ed Sperling