While the use of power islands and clock gating has so far been something to think about down the road for many engineers, far fewer will need high beams in the future.

For many SoCs at 65nm, and for most designs at 45nm, these kinds of techniques are a requirement. The experience of companies that have been wrestling with these issues is these tools require a lot of trial and error, and power needs to be modeled well ahead of the design—in some cases, several generations before it’s actually required.

Verification can turn particularly ugly if it isn’t thought through well ahead of time. While the number of combinations of on, off, sleep and deep sleep are mind-boggling, the architect can establish a far more limited number of possible combinations and prioritize them. And while efforts to trim static leakage have garnered the most attention, at future nodes dynamic power leakage is becoming a problem, too.

These are not simple changes in the engineering of semiconductors. Proximity issues are causing signal integrity problems that only get worse when coupled with heat. And they get worse at each successive node as leakage increases.

These are not simple issues, but they can be dealt with given enough time and planning. And according to engineers at some of the largest chip companies, the standard word of advice these days is that it’s time to start planning.

–Ed Sperling

One of the messages repeated in almost all sectors of SoC design these days is that power constraints will make semiconductor design more complicated, more time-consuming, and potentially less reliable.

In some cases, this is pure conjecture. It’s like crossing a threshold where you don’t know what lies on the other side. While there has been a lot of research into power-saving techniques such as power modeling for various states of on, off, almost on, almost off and everything in between—not to mention lots of work in power islands and power delivery—for most engineers this is still theory. Only a few of the largest companies actually have invested in the engineering manpower to make all this stuff work and verify it. And as most of those engineers will attest, the devil is the details.

The problem is the vast and seemingly endless number of details. And no matter how many levels of abstraction are added into the mix, that number is still mind-boggling. Power, like almost everything else, can be modeled and synthesized at a high level. But it still has to be checked, debugged and verified.

The pain point in SoC design for years has been verification, as evidenced by numbers ranging from 50% to 70% of the non-recurring engineering costs and development time. With power modeling and various power-conserving techniques thrown in, it’s gets more time-consuming and more expensive.

This is where the race for solutions is heading now, and it’s where the next big opportunities will be. Place and route, at one point a mainstay of chip design, has become relatively routine, and it’s only going to become more so as restrictive design rules become commonplace at 32nm and beyond. The next big hurdles are modeling at a complexity level never conceived of before, synthesizing everything from the software to how the power flows through a device, and then testing not only the circuitry but the software and the packaging—the whole shebang.

While most engineers who have been around awhile like to remind us that semiconductor design has always been a serious of engineering hurdles ranging from lithography issues to manufacturability, power has never really been a critical factor. At 90nm, the big concern was static current leakage. At 32nm it will be power states. And at 22nm and beyond, it will be both of those and more.

There is no longer just one problem to solve at each node. Now there are many, including repeats of the same ones. And for the most part, power is the overriding and most complicating factor that simply refuses to go away.

–Ed Sperling

There has been much talk about smart meters and intelligent use of resources lately, largely because when some users installed those devices their utility costs went up instead of down. (The power companies called it a glitch.)

Smart meters make lots of sense—at least on paper. In apartment buildings in many cities, for example, individual apartments have no idea how much water they are using. And there is something to be said for electric meters that tell you how much electricity you are using at peak hours so you can reduce the cooling in the hot part of the day when no one is home.

But however sophisticated these techniques are, the average person isn’t going to program them. Decades after digital clocks were introduced, so many VCRs were blinking on 12:00 that manufacturers removed the clocks. DVD players don’t have clocks. And no matter how obvious the gains of smart metering, the average person isn’t going to be programming them, either.

From an engineering-centric view of the world, this all makes sense. But if it were up to computer engineers, everyone would be using Unix commands on their PC and Microsoft would never have existed. (Yes, we all know people who run Unix commands even though Windows and Mac OSX are now basically Unix.) And if it were up to German car engineers, we still wouldn’t have decent cup-holders in our cars.

What’s needed alongside all of this technology we’re being bombarded with—and some of it is brilliant technology, indeed—is a way to make this technology easier to use. All the low-power engineering on the planet won’t make a dent if the average person either can’t install it or figure out how to use it once it is installed.

At least as much effort has to be put into an intuitive interface and programming as the ability to reduce power consumption, and that means more collaboration between the people writing the software, those developing the components and those dictating the functionality in the devices. Standardized hooks in the hardware would go a long way to making a dent in this problem.

Without that, the effectiveness of any technology—and the ability to sell more of it—will be greatly diminished. There are plenty of brilliant products that never got out the door because no one could explain what they did. There will likely be many more that do get out the door but fall flat because it’s just too hard to use them.

–Ed Sperling