The Power To Complicate
One of the messages repeated in almost all sectors of SoC design these days is that power constraints will make semiconductor design more complicated, more time-consuming, and potentially less reliable.
In some cases, this is pure conjecture. It’s like crossing a threshold where you don’t know what lies on the other side. While there has been a lot of research into power-saving techniques such as power modeling for various states of on, off, almost on, almost off and everything in between—not to mention lots of work in power islands and power delivery—for most engineers this is still theory. Only a few of the largest companies actually have invested in the engineering manpower to make all this stuff work and verify it. And as most of those engineers will attest, the devil is the details.
The problem is the vast and seemingly endless number of details. And no matter how many levels of abstraction are added into the mix, that number is still mind-boggling. Power, like almost everything else, can be modeled and synthesized at a high level. But it still has to be checked, debugged and verified.
The pain point in SoC design for years has been verification, as evidenced by numbers ranging from 50% to 70% of the non-recurring engineering costs and development time. With power modeling and various power-conserving techniques thrown in, it’s gets more time-consuming and more expensive.
This is where the race for solutions is heading now, and it’s where the next big opportunities will be. Place and route, at one point a mainstay of chip design, has become relatively routine, and it’s only going to become more so as restrictive design rules become commonplace at 32nm and beyond. The next big hurdles are modeling at a complexity level never conceived of before, synthesizing everything from the software to how the power flows through a device, and then testing not only the circuitry but the software and the packaging—the whole shebang.
While most engineers who have been around awhile like to remind us that semiconductor design has always been a serious of engineering hurdles ranging from lithography issues to manufacturability, power has never really been a critical factor. At 90nm, the big concern was static current leakage. At 32nm it will be power states. And at 22nm and beyond, it will be both of those and more.
There is no longer just one problem to solve at each node. Now there are many, including repeats of the same ones. And for the most part, power is the overriding and most complicating factor that simply refuses to go away.
–Ed Sperling