Power Management Approaches Mainstream
While the use of power islands and clock gating has so far been something to think about down the road for many engineers, far fewer will need high beams in the future.
For many SoCs at 65nm, and for most designs at 45nm, these kinds of techniques are a requirement. The experience of companies that have been wrestling with these issues is these tools require a lot of trial and error, and power needs to be modeled well ahead of the design—in some cases, several generations before it’s actually required.
Verification can turn particularly ugly if it isn’t thought through well ahead of time. While the number of combinations of on, off, sleep and deep sleep are mind-boggling, the architect can establish a far more limited number of possible combinations and prioritize them. And while efforts to trim static leakage have garnered the most attention, at future nodes dynamic power leakage is becoming a problem, too.
These are not simple changes in the engineering of semiconductors. Proximity issues are causing signal integrity problems that only get worse when coupled with heat. And they get worse at each successive node as leakage increases.
These are not simple issues, but they can be dealt with given enough time and planning. And according to engineers at some of the largest chip companies, the standard word of advice these days is that it’s time to start planning.
–Ed Sperling
