3D is great when it comes to movies. It’s quite another when it involves semiconductor design.

For the past several years, large companies have been experimenting with ways to reduce power in SoCs by stacking them together. In theory, at least, performance can increase and power can decrease because there is less distance to travel. A signal might only have to travel nanometers with a through-silicon via instead of millimeters across a two-dimensional layout.

While memory companies have been slapping together layer upon layer of memory cells, building a 3D SoC is a lot more complicated. Heat is one issue. Getting the heat out of a vertical die is like cooling the inside of a brick. And making sure there are no thermal effects is far more difficult when the chip includes multiple cores, multiple voltages and multiple states.

Even worse, at 22nm and beyond the likelihood that 3D structures such as FinFETS will be introduced is very high. That makes stacking particularly difficult. In addition, while most of the verification and synthesis tools can be extended into the 3D world, it becomes far more difficult with things like parasitic extraction. There is more data to process in three dimensions—if it can be modeled in the first place. The same applies to synthesis and simulation.

The upside, of course, is that not everything has to be reinvented for each new process node. Portions of chips will be re-usable, even at older nodes, with structures that benefit from moving to new nodes. Processes are better understood at those nodes, and particularly in analog/mixed signal chips, there’s no advantage to pushing analog down to the latest node. Timing closure is simpler and verification is greatly reduced.

Companies are betting that the 3D problems can be solved and that business needs will push it quickly. But they were also betting that EUV would be ready for the 32nm process node, and now they’re wondering if it will ever appear. While 3D stacking makes sense, it also raises some issues no one has ever dealt with before, and most of them are either driven by the need to reduce power or the steps that were taken to alleviate them already.

–Ed Sperling

For anyone versed in the fine art of actually getting a low-power semiconductor to tapeout and into real products, there is a firm understanding that much still can be done to reduce power consumption. More cores can be added, those cores can be sized appropriately with tightly written software, controlled by power islands and appropriate voltage levels. Packaging can help, as well, with everything from silicon-on-insulator to some of the more exotic substrates such as graphene that are now the subject of laboratory studies.

But one question that has never been effectively answered is for how long? How long will these techniques continue to change the equation for area, performance and power? As we move from one process node to the next, what are the limitations to these low-power techniques?

As an industry we’re pretty knowledgeable about the limitations of CMOS and lithography. We can even make educated guesses about the limits of software. What we don’t know is how much room there is in power-reduction techniques, in large part because this has been carried on by individual chipmakers. There has never been an effort to commercialize this knowledge.

All of that starts changing at 90nm and below, and it continues to become more of a challenge at each successive node. Moving into stacked die will help significantly. So will better lithography, which will ease some of the restrictive design rules and allow more freedom within designs. But at 20nm and beyond, it begins getting more difficult to see exactly what the tradeoffs will be, how they’re going to be verified and what the impact will be of everything from process variation to higher defect density on power budgets.

The power-saving techniques are readily available now. Enjoy them while they last.

–Ed Sperling

It probably doesn’t sound like much—$47 million in grants paid out to HP, IBM and Yahoo, among others for advanced research in low-power engineering. But the intent is clear: The government is holding out a carrot to the companies that contribute to one of the biggest energy-hogging sectors on the planet and advising them to clean up their act.

Regardless of whether you think these companies should get the money—or whether they be forced to pump money into a research fund rather than receive public money, as some engineers have suggested privately—the interesting part is what they’re working on.

One of the more intriguing projects receiving funding is at SeaMicro, which is looking at overall server architectures and how to add hundreds of interconnected low-power processors rather than multiple processors with multiple cores. The approach is a different approach but the same trajectory as Intel’s experimental many-core chips that basically can provide a cloud on a chip for the equivalent power drain of two incandescent bulbs.

What’s changing here is a deeper understanding of exactly what’s involved in processing and just how much power needs to be devoted to individual tasks. Much of the engineering work in this field already has been pioneered by consumer electronics, where power islands, multiple voltages and a variety of power states—on, off, almost on, almost off, deep sleep and comatose—are regular features. Those devices also are beginning to add heterogeneous cores to the chips that are sized appropriately for the task and with the appropriate amount of current. These types of power-saving techniques are almost unknown in the server world, or for that matter almost anything with a plug instead of a battery.

All of that has to change. The question is how far it can change given the fact that the amount of data is now measured in petabytes and soon will likely be measured in exabytes and zettabytes. (The next extension is yottabytes.) Online, it appears no one ever throws anything away, and the ability to process more of that information at a higher and higher level of abstraction only makes it less likely that this global storage of data will ever be tamed.

For decades, power budgets inside of data centers have been creeping upward. It takes more power to process faster, more power to store more data and more power to cool it all. All of this has to be engineered to use far less power in the future with more data processing than what is being used now, including everything from processing power to cooling the processors with either air, water, liquid metal (IBM) or ways to turn that heat into something useful.

The money being spent by the government is almost beside the point. The big question is whether all of this can be accomplished, how quickly, and whether enough systems engineers can be trained on all of these pieces to accomplish this task. This is nothing short of creating a massive electronics infrastructure with a heavy focus on power consumption, and it’s something that could provide one of the biggest boosts to low-power engineering since the invention of the first battery-powered cell phone.

–Ed Sperling