But For How Long?
For anyone versed in the fine art of actually getting a low-power semiconductor to tapeout and into real products, there is a firm understanding that much still can be done to reduce power consumption. More cores can be added, those cores can be sized appropriately with tightly written software, controlled by power islands and appropriate voltage levels. Packaging can help, as well, with everything from silicon-on-insulator to some of the more exotic substrates such as graphene that are now the subject of laboratory studies.
But one question that has never been effectively answered is for how long? How long will these techniques continue to change the equation for area, performance and power? As we move from one process node to the next, what are the limitations to these low-power techniques?
As an industry we’re pretty knowledgeable about the limitations of CMOS and lithography. We can even make educated guesses about the limits of software. What we don’t know is how much room there is in power-reduction techniques, in large part because this has been carried on by individual chipmakers. There has never been an effort to commercialize this knowledge.
All of that starts changing at 90nm and below, and it continues to become more of a challenge at each successive node. Moving into stacked die will help significantly. So will better lithography, which will ease some of the restrictive design rules and allow more freedom within designs. But at 20nm and beyond, it begins getting more difficult to see exactly what the tradeoffs will be, how they’re going to be verified and what the impact will be of everything from process variation to higher defect density on power budgets.
The power-saving techniques are readily available now. Enjoy them while they last.
–Ed Sperling
