3D is great when it comes to movies. It’s quite another when it involves semiconductor design.

For the past several years, large companies have been experimenting with ways to reduce power in SoCs by stacking them together. In theory, at least, performance can increase and power can decrease because there is less distance to travel. A signal might only have to travel nanometers with a through-silicon via instead of millimeters across a two-dimensional layout.

While memory companies have been slapping together layer upon layer of memory cells, building a 3D SoC is a lot more complicated. Heat is one issue. Getting the heat out of a vertical die is like cooling the inside of a brick. And making sure there are no thermal effects is far more difficult when the chip includes multiple cores, multiple voltages and multiple states.

Even worse, at 22nm and beyond the likelihood that 3D structures such as FinFETS will be introduced is very high. That makes stacking particularly difficult. In addition, while most of the verification and synthesis tools can be extended into the 3D world, it becomes far more difficult with things like parasitic extraction. There is more data to process in three dimensions—if it can be modeled in the first place. The same applies to synthesis and simulation.

The upside, of course, is that not everything has to be reinvented for each new process node. Portions of chips will be re-usable, even at older nodes, with structures that benefit from moving to new nodes. Processes are better understood at those nodes, and particularly in analog/mixed signal chips, there’s no advantage to pushing analog down to the latest node. Timing closure is simpler and verification is greatly reduced.

Companies are betting that the 3D problems can be solved and that business needs will push it quickly. But they were also betting that EUV would be ready for the 32nm process node, and now they’re wondering if it will ever appear. While 3D stacking makes sense, it also raises some issues no one has ever dealt with before, and most of them are either driven by the need to reduce power or the steps that were taken to alleviate them already.

–Ed Sperling

Tags: 3D, vertical stacking

This entry was posted on Friday, January 29th, 2010 at 12:01 am and is filed under Editorial, Opinion. You can follow any responses to this entry through the RSS 2.0 feed. You can leave a response, or trackback from your own site.