Global Domination
There are few problems in semiconductor design that can span an entire device. Timing can affect how blocks function. Verification affects the functionality of a complete chip. But power can affect the entire device.
Power—and its ugly byproducts leakage and heat—are becoming even more troublesome. They now reach beyond the SoC and across the board. It affects battery life and the user experience on a portable device. And it affects power bills and operating expenses in the corporate data center.
It’s also the one problem that doesn’t get better. EUV may improve the manufacturability of chips. More regular structures makes it easy to lay them out. And verification tools, used effectively, can have a significant impact on the time it takes to get a chip out the door. The same goes for high-level modeling and hardware-software co-design and software prototyping.
But power doesn’t go away. It gets worse at every node. Even with new approaches such as 3D stacking, power is the real trouble. Hot spots need to be accounted for and dealt with because they can affect everything from signal integrity to the life of the chip. Electromigration and electrostatic discharge need to be addressed. Even at the architectural level, systems designers need to figure in the power budget and how it needs to be dealt with across the board, using everything from clock gating and multiple power islands to independent features and potentially different ICs.
This is tough stuff, but it’s also the future of all semiconductor engineering and design. In the past, power was something that had to be dealt with at the most advanced process nodes by the largest companies. It’s now the No. 1 issue, and that is unlikely to change for many generations and design approaches to come.
–Ed Sperling
