Matching hardware to software, and software to hardware, is an interesting discussion. It’s also one that usually happens at a very high-level of abstraction, which renders many of the conclusions less than helpful.

The software stack is not a single thing. It’s a group of things, all incredibly complex in their own right and increasingly in need of some very detailed integration. The fact that complex hardware blocks and entire chips at advanced nodes are pushed out the door before an application is even completely coded, let alone verified, says something about the interaction of code and the entire software coding process.

Despite decades of advancements in software development, the sheer magnitude of interactions and the volume of code still makes it impossible to develop applications quickly. That’s the reason software teams are regularly scheduling time on hardware emulators. They need enormous amounts of number crunching power to handle all the assertions and possible interactions. As a result, trying to get application developers to now think about writing code to more effectively utilize hardware is futile. Hardware will have to be optimized to the applications, and in some cases that may mean specialized chips to run specialized applications.

But looking at software as a whole is like looking at a complex SoC as a single piece of technology. There are many things that make up an SoC, and increasingly not all of them are developed in one place even by the largest IDMs. Software drivers and firmware definitely can be tailored to the hardware, and operating systems may be something of a compromise between the hardware and software teams if they can find a way to work together.

That may be the biggest problem to overcome, because these groups are used to functioning autonomously. Politics inside of companies, and particularly between companies, is the biggest issue in a disaggregated market. Apple’s recent acquisitions speak volumes about this problem. So do Intel’s acquisition of Wind River and Synopsys’ acquisition of the major software prototyping companies.

Still, from a power and performance perspective, working together can result in huge improvements in efficiency of devices. The question is who’s going to drive this effort—and whether they will ever be able to rise above politics and finger-pointing when something goes wrong to achieve better performance and bigger energy savings.

–Ed Sperling

One of the great debates is whether low-power devices can actually use less power than previous generations of those devices. The answer is a resounding yes when looked at in a single point of time, but over time the answer isn’t so clear cut.

Home on-demand water heaters are a great example. While most manufacturers post large yellow labels showing it costs less to run these devices, the average homeowner finds little change—and in many cases they find these suddenly essential devices actually cost more. Given unlimited hot water, people use more.

The same is true with portable devices. While the battery on smart phones will last longer for listening to music or making phone calls in areas with reasonably good reception, most people still have to charge their phone as often as with previous models. There are more functions to use, and those functions in aggregate use more energy.

Perhaps even more daunting, there are simply more of them. The number of phones being sold—particularly advanced smart phones—continues to rise. That’s more energy being spent globally, and while the chips inside those phones may be more efficient in total they are drawing far more energy than previous generations that were not available to as many people.

Road builders in the United States in the 1940s and 1950s discovered this same phenomenon. No matter how many new roads they built to relieve congestion, the minute they were opened traffic increased everywhere. More cars were sold to take advantage of the new roads and even more roads were needed to handle the new cars.

The real problem with energy consumption isn’t the efficiency of devices. There have been some amazing advances in technology to extend battery life by shutting down blocks with power islands, reducing dynamic and static leakage, and reducing the voltages on chips to an absolute minimum. But all this has only whetted the appetite of consumers who will continue to demand more functionality and more performance now that batteries can last even longer.

By nature, people don’t conserve. They consume. And the more technological advances that are made, the more they will consume. While this may be great for business, it also will raise lots of red flags along the way from power companies, consumers complaining about energy higher bills, environmental groups, and everyone else who wants to chime in. Beware of the cross traffic from unexpected places.

–Ed Sperling

The oil industry makes a good comparison to what’s going on in the semiconductor world. While everyone talks about the end of the oil era, the fact is that there is still plenty of oil left in the ground. It just gets harder to extract.

The same is true of power savings on a piece of silicon. It’s still possible to save lots of power in devices. It’s just harder to do—and more expensive. It will require new materials, new techniques, and in some cases a new way of thinking.

The materials that are likely candidates for lowering power and minimizing the effects of shrinkage at each new node are well known and have been tested for years. SOI leads the pack—particularly fully depleted SOI—but there also are some more exotic combinations that could play an important role for certain industries.

The techniques for lowering power are also well known. At 45nm, almost everyone is working with power islands, power modeling and multiple voltages, and at 28nm and beyond there will need to be standards for how to bring all of this stuff together in a more consistent manner. The problem gets even worse in 3D, because power equates to heat, and heat is much tougher to get rid of in a multi-die stack.

The new approaches are something of a shift in approach. While the semiconductor industry has been marching to the beat of smaller, faster and cheaper (or at least less expensive) for nearly half a century, the answer may no longer be from the standpoint of a single chip. It may be multiple chips, in addition to multiple chips in a stack. If one chip can do a specific function with less power, then that can be a significant gain for conserving overall system power. The problem is that most engineering teams aren’t organized to make this type of approach work.

Power is global in a device, though, which means it will require a global approach among systems companies—reaching far beyond an individual chip and across the PCB, which in some cases may mean across multiple geographies and time zones. This isn’t so simple, and it may be the hardest piece for chip developers to come to grips with. Internal organizations and politics are common tripwires for companies, and that becomes even harder when it’s built around a somewhat vague concept such as power.

Nevertheless, power will define which companies are competitive over the next decade and which ones are not, and the companies that embrace it first will be the ones best positioned to deal with it when their customers begin asking for bids on a more effective approach to extending battery life or cutting the power in plug-in devices, which soon will be measured directly by consumers.

–Ed Sperling

There seems to be little doubt that the semiconductor industry is moving to 3D stacking. It’s simply too expensive for most companies to develop SoCs at advanced nodes from scratch when they can use existing blocks of pre-verified IP—particularly analog IP developed for older processes.

Since the semiconductor industry emerged from the downturn one of the biggest shifts has been to integrating rather than developing everything from scratch. It still has to be laid out using normal place and route tools and it still has to be painstakingly verified. In fact, the verification problem has grown worse because it now includes software.

But the bulk of the existing EDA tools will only need to be tweaked for this to happen. Executives say privately they aren’t expecting huge increases in tools revenues from existing customers because they will simply do more with the same tools. The real opportunity is to sell to new customers, who now have the same integration headaches as existing customers. And while their old tools worked fine at 130nm, 3D stacking allows everyone to feel the same pain of integration and verification.

That also means more number crunching with emulation tools. More formal verification tools because assertions will become a requirement. But the biggest winners will be companies developing point tools to identify thermal issues caused by inadequate power modeling and proximity effects related to power—and those that can ease the integration of multiple layers of chips.

Heat, electromigration and electrostatic discharge are the main issue that needs to be addressed in 3D structures. Chips that work fine in 2D may not work properly in 3D because of both dynamic and static leakage on an adjacent layer. At 20nm, everything leaks. And discharge that may not cause any damage on a single layer can move through a through-silicon via like lightning to an unprotected middle or bottom layer.

This is a huge opportunity for startups and established EDA companies, which will develop their own tools and likely buy up others. It also is a huge opportunity for the industry to begin showing mega growth again. The only question now is exactly when 3D really kicks into high gear, because there are a lot of companies waiting for that answer.

–Ed Sperling