One of the interesting things about low-power designs in ICs is just how effectively power-saving techniques are being designed into chips these days. At most of the larger chipmakers, and even at an increasing number of midsize fabless companies, the concepts for implementing low-power techniques are well understood, well tested and thoroughly familiar.

Two years ago, when the mainstream of design was at 65nm and in some cases 90nm, only the largest chipmakers had worked with multiple power island and multiple voltage rails. At 45nm, this has become standard practice, and the number of companies that are pushing into 45nm is growing as this node becomes mainstream.

The good news is a lot of work already has been done in these areas. The concepts of power intent are relatively well defined, even if there are two standards, and the verification of multiple modes and states and an understanding of how to turn off and on various power islands with the least energy are well tested. There has been much work in these areas.

The challenge, however, is getting companies that buy these chips to actually utilize all the power-saving features. Time-to-market pressures by OEMs have trumped power savings so far. Putting a chip into an end-user device and getting that system out the door is more important than saving a few minutes of battery life.

That will change over the next couple of process nodes as more features are added into devices and leakage forces most blocks to be in the “off” state when they’re not in use. At that point, wake-up time will have to be defined by OEMs because it will become increasingly critical to the user experience and the overall perception of performance.

There has been a tradeoff between power and performance four at least the past decade, but what will change is that the perception of overall performance will now include how fast power domains can be switched on and off rather than just how fast a processor runs. This is a significant shift, and it will do more to drive attention to low power designs than years of advancements in this area could ever achieve.

–Ed Sperling

Emulation, which has been used for developing low-power chips, is now being viewed by large chipmakers at as a way of reducing costs in simulation farms.

This is an interesting twist on the economics of some very pricey hardware, which wasn’t considered a huge growth market over the past decade because of the upfront costs, and it follows what’s been going on across large IT departments. Enterprise IT departments have been wrestling with the problems of energy consumed by servers for the past half-dozen years. In addition to machines drawing power while being underutilized—the key drivers behind virtualization and cloud computing—the cost of cooling densely packed racks of air-cooled servers has been skyrocketing.

It’s ironic that Moore’s Law is to blame for all of this. Advanced chip geometries have allowed for much more computing capability, but they also have been responsible for driving up the heat inside these cabinets to the point where air is no longer a sufficient cooling medium. In some cases the noise from circulating fans has risen above the safe levels allowed by OSHA, which is why water cooling is making a comeback in some of the largest installations. Water is a more efficient medium for cooling chips than air.

Emulation is benefiting from the same kinds of dynamics in simulation. As Jim Kenney, product marketing manager at Mentor Graphics noted, “Power, cooling and facilities space are part of the cost of ownership. For an equivalent amount of work, emulation is smaller and uses less power than an equivalent server farm.”

Business is up at all three of the major emulation companies—Mentor, Cadence and EVE. Our guess is it will continue to rise, in part because of these kinds of economic tradeoffs and in part because the software development teams need all the help they can leverage in getting software to run on chips out the door in a reasonable amount of time.

But putting this all in perspective, it’s the chips that caused the overheating in the first place. Now the machinery used to create those chips is overheating because of those chips, driving a new market for even bigger machinery. It’s an odd development, but it could be one of the most innovative business models ever created.

–Ed Sperling

One of the strange effects beginning to show up at 32/28nm is that existing design team structures and tools aren’t working optimally, and sometimes they’re not working at all.

The problems that Intel just reported with its latest Sandy Bridge processors are probably the most visible indication that change is needed. Problems at other companies range from inability to meet power budgets, failure to meet deadlines, and extremely low yields.

In the majority of cases, power is the culprit. Dropping the voltage too low can cause reliability problems. Keeping it too high can overheat the chip. And trying to verify across all of the power islands, multiple states and modes and an increasing number of functions that have to work within a given power budget is turning into a mind-numbing challenge.

Add to that software, which is used to control the on-off-sleep states and the switching and surge protection, and some changes are in store from the front end to the back end. In fact, what’s becoming increasingly apparent is that in the future there may not be a well-defined front or back end. Power considerations, physical stress, thermal effects, and the need for up-front exploration based on those issues and many others is forcing a rethinking of all flows, as well as how and when tools need to be used.

The ideas of concurrent design and system-level design have been around for years. So far, the uptake in these areas has been slow, and most of it by companies working at the most advanced process nodes. That will change over the next couple years as 45nm and 32nm become mainstream processes, with an added push once 2.5D and 3D stacking become the norm.

To make these ideas work effectively, though, designers will need to re-examine their design teams and how they utilize tools—including new tools they’ve never worked with before—and tools providers will have to figure out how teams will actually use existing and new tools.

What’s becoming clear is that we have reached an inflection point. It’s time now to start planning for the changes ahead.

–Ed Sperling