Electronics has always been about convergence, and convergence inevitably spawns new companies while forcing consolidation of others.

What used to be in a device moved to a board, from a board there has been a perpetual push to put things in a chip. At one point, circa 2000, analog companies claimed that mixed signal chips were a thing of the past and that there would be separate analog chips in addition to digital chips. There may be again in 2.5D stacking, but the whole thing will still end up in a package with much shorter wires and greater bandwidth.

Even processors are converging with SoCs. Intel’s top execs have been saying more forcefully for the past few years that the future is SoCs, and that the bulk of Intel’s future revenues will come from SoCs rather than monolithic processors. While that has yet to materialize in Intel’s earnings reports, at least there is a nod from the world’s most successful chipmaker that more has to be integrated into a chip than in the past. Apple, which is a partner and a rival for Intel, has already migrated a good portion of its product line to SoCs. And Panasonic and Fujitsu are in talks with Renesas to create a single SoC giant in Japan.

But there are some unusual changes in this march toward convergence and consolidation that are also showing up in the market, mostly because of power issues. Power is now dragging other disciplines into the basic design and engineering of an SoC, determining what goes where, how it gets put together and by whom, and notably how it can be made more efficient and cooled.

Cary Chin’s blog this week about solar smartphones is a case in point. So is the increasing role of mechanical engineering in SoCs for everything from cooling closer to the core to MEMS sensors that eventually will be built on a stacked die to energy scavenging using a combination of electrical and mechanical approaches. There is even work underway in research labs for chemical engineering to generate energy inside of devices. And increasingly there is a feedback loop to the software world to improve efficiency in software engineering.

The question is what other disciplines will begin to take a front-seat position in SoC design. One big change on the horizon is in the area of physics, which has always been a combination of observed and theoretical. In the past five years we have been able to actually see atoms, but over the next decade the expectation is that we will start seeing subatomic particles. At that point, theoretical physics becomes observed physics, and after that anything is possible.

How much of this will remain in the IC realm, and how much will filter out into other areas is unknown. But one thing is certain—we’ve only scratched the surface of possibilities.

–Ed Sperling

Ever since Moore’s Law passed 65nm, the discussion has focused on power versus performance. Do you run a chip faster and hotter, or do you keep performance about the same from one chip to the next and improve battery life.

At 28nm and beyond, there are other factors that begin to weigh into this discussion. One is reliability. Can a chip developed at the forefront of Moore’s Law be as reliable as one that is developed at older nodes? The gut reaction is yes, but the answer isn’t always so simple. The reason goes well beyond ensuring physical effects such as electromigration, cross-talk and even electron crashes don’t affect signal integrity. It also has to do with guard-banding—those extra wires and circuits put in to ensure the chip continues to work in the event of problems such as electromigration and even radiation effects—which can eat into both performance and energy efficiency.

Ultimately there may be ways to make up for some of this excess margin in 3D stacks. Overall margin can be held relatively constant by rationalizing memory usage for each processor on an SoC, particularly when there are multiple processors scattered throughout the design with dedicated functionality. This type of approach may take years before it becomes mainstream, however. In the meantime, designers will have to slim down the circuitry on their existing models and pray that it all works as planned.

A second reason, which is related, has to do with commercially available IP. Until now, the real value in IP is the speed and ease with which it can be implemented in a design. A Lego-like approach is a huge win when it comes to addressing time-to-market pressure. Being sure that an IP block or subsystem will work in any design is incredibly difficult, and it requires a lot of pre-characterization so designers know how it will perform in the context of a specific design. But flexibility also comes at a price, and again the problem is margin. The problem is that this time it’s from a supplier and it comes a ready-made black box that isn’t so easy to alter.

There are no simple answers to how to solve these problems, and there certainly is no single answer. The only thing that is certain is that these issues will become more glaring as we march forward to 20nm and 14nm, and power will continue to be the main driver for slimming margins on every front. The only question now is what the ultimate cost will be.

–Ed Sperling