What used to be in a device moved to a board, from a board there has been a perpetual push to put things in a chip. At one point, circa 2000, analog companies claimed that mixed signal chips were a thing of the past and that there would be separate analog chips in addition to digital chips. There may be again in 2.5D stacking, but the whole thing will still end up in a package with much shorter wires and greater bandwidth.

Even processors are converging with SoCs. Intel’s top execs have been saying more forcefully for the past few years that the future is SoCs, and that the bulk of Intel’s future revenues will come from SoCs rather than monolithic processors. While that has yet to materialize in Intel’s earnings reports, at least there is a nod from the world’s most successful chipmaker that more has to be integrated into a chip than in the past. Apple, which is a partner and a rival for Intel, has already migrated a good portion of its product line to SoCs. And Panasonic and Fujitsu are in talks with Renesas to create a single SoC giant in Japan.

But there are some unusual changes in this march toward convergence and consolidation that are also showing up in the market, mostly because of power issues. Power is now dragging other disciplines into the basic design and engineering of an SoC, determining what goes where, how it gets put together and by whom, and notably how it can be made more efficient and cooled.

Cary Chin’s blog this week about solar smartphones is a case in point. So is the increasing role of mechanical engineering in SoCs for everything from cooling closer to the core to MEMS sensors that eventually will be built on a stacked die to energy scavenging using a combination of electrical and mechanical approaches. There is even work underway in research labs for chemical engineering to generate energy inside of devices. And increasingly there is a feedback loop to the software world to improve efficiency in software engineering.

The question is what other disciplines will begin to take a front-seat position in SoC design. One big change on the horizon is in the area of physics, which has always been a combination of observed and theoretical. In the past five years we have been able to actually see atoms, but over the next decade the expectation is that we will start seeing subatomic particles. At that point, theoretical physics becomes observed physics, and after that anything is possible.

How much of this will remain in the IC realm, and how much will filter out into other areas is unknown. But one thing is certain—we’ve only scratched the surface of possibilities.

–Ed Sperling

At 28nm and beyond, there are other factors that begin to weigh into this discussion. One is reliability. Can a chip developed at the forefront of Moore’s Law be as reliable as one that is developed at older nodes? The gut reaction is yes, but the answer isn’t always so simple. The reason goes well beyond ensuring physical effects such as electromigration, cross-talk and even electron crashes don’t affect signal integrity. It also has to do with guard-banding—those extra wires and circuits put in to ensure the chip continues to work in the event of problems such as electromigration and even radiation effects—which can eat into both performance and energy efficiency.

Ultimately there may be ways to make up for some of this excess margin in 3D stacks. Overall margin can be held relatively constant by rationalizing memory usage for each processor on an SoC, particularly when there are multiple processors scattered throughout the design with dedicated functionality. This type of approach may take years before it becomes mainstream, however. In the meantime, designers will have to slim down the circuitry on their existing models and pray that it all works as planned.

A second reason, which is related, has to do with commercially available IP. Until now, the real value in IP is the speed and ease with which it can be implemented in a design. A Lego-like approach is a huge win when it comes to addressing time-to-market pressure. Being sure that an IP block or subsystem will work in any design is incredibly difficult, and it requires a lot of pre-characterization so designers know how it will perform in the context of a specific design. But flexibility also comes at a price, and again the problem is margin. The problem is that this time it’s from a supplier and it comes a ready-made black box that isn’t so easy to alter.

There are no simple answers to how to solve these problems, and there certainly is no single answer. The only thing that is certain is that these issues will become more glaring as we march forward to 20nm and 14nm, and power will continue to be the main driver for slimming margins on every front. The only question now is what the ultimate cost will be.

–Ed Sperling

In high-end devices, the incremental cost of adding even additional processors tends to get buried. In extremely price-sensitive markets, it will not be. So one big question beginning to percolate around the industry is just how lucrative this extended battery life will be. Will it just be the high end of the laptop, smart phone and tablet markets? Or will it also carry over into the second-tier versions of these devices, where volume is significantly greater but budgets are tighter?

These are important questions for engineers, even though they may seem one step removed, because it affects their development budgets. Those budgets are used for training, for hiring more engineers, and ultimately for boosting compensation of team members.

The issues here are both convenience and electricity costs. The convenience is well known. If you don’t have to charge a device immediately after extended use, or you can use your laptop productively flying between San Francisco and Beijing without worrying about plugging it in, that’s both convenient and a major productivity gain.
But in price-sensitive markets, the cost of charging a device also enters into the picture, and a similarly priced efficient device will probably win over one that is less efficient.

So given that the demand for low-power engineering is growing, who’s actually reaping the rewards for all of this effort? Is it incremental or just a prerequisite for winning a design? And will that change in the future?

–Ed Sperling

Over the past few years, power has moved from an afterthought to the front of the pack because of the emphasis on mobility and battery life. Even in data centers, power has suddenly emerged as the low-hanging fruit for cutting energy costs.

In the future, engineers will have to consider another factor: function. Just as power is a global issue—it affects all parts of a device rather than just a single portion of an SoC, for example—function has a direct effect on area, power and performance. Adding more functions, or enhancing those functions, requires tradeoffs, re-thinking and sometimes re-engineering every facet of PPA.

The real driver behind this shift in functional importance is the need to do more useful things with portable electronics. It’s not enough just to check e-mail or make voice calls anymore. Devices now need to stream video, do intensive graphics for gaming, and increasingly they need to do real work such as spreadsheets and document creation.

But they don’t necessarily need to do it as well as a powerful desktop computer with all the same options, which can save on power, performance and area. The 80/20 rule applies here, and it’s being looked at carefully by the engineers who create the specs for devices. You don’t have to do everything to perfection. You just have to do it well enough to make it useful.

To accomplish this also requires tradeoffs. Slick interfaces such as voice commands may require more energy to stay awake and responsive, which means less performance and a lower power budget for other portions of an SoC. This helps explain the proliferation of multicore and multiprocessor architectures optimized for individual functions rather than trying to power up and power down a single processor that offers maximum performance for a function that doesn’t require it.

Stacking of die will improve this recipe even further. Being able to directly connect to portions of memory rather than sharing resources will make individual functions much more controllable from a PPA standpoint. But as we begin building these 2.5D and 3D stacks, increasingly it will be function that determines PPA rather than the other way around.

–Ed Sperling

Worse, energy efficiency has long been at the bottom of the list of attributes that consumers of technology recognize as critical. Historically it has been a nice-to-have feature, but the real battle was between cost, features, and those annoying delays that are equated with performance. In fact, until recently, many of the power-saving features that were painstakingly developed by design teams were completely ignored by device manufacturers.

That’s changing, of course. More features, particularly streaming video and gaming, mean even more energy-efficient designs are required. And being able to eke more battery life out of a design has now become a competitive advantage. Being able to carry around a charger with a device is not. And even in data centers, being able to keep performance consistent while chopping energy bills for both powering machines and then cooling them is being closely watched.

Blame flows downhill rather quickly. Recognition does not. In fact, sometimes it never reaches the bottom. But that recognition is necessary because it often is directly tied to higher profits, providing the market isn’t grossly overcrowded. With the focus on efficiency, there is plenty of room for companies to stretch out and find a sparsely populated niche—providing they can get recognized for it.

Many engineering-driven companies assume they will win if they create the best products. That’s increasingly true with low-power designs. But reaping the full rewards of their efforts requires them to be able to think up several levels of abstraction in the supply chain and to market the end-customer benefits and options. This is marketing at its finest, and it’s something engineering-driven companies don’t do very well even in the best of times, let alone when markets become overcrowded and mature.

Energy is a new wrinkle in all of this. It’s resonating with the end customer, the device manufacturer and all the way throughout the supply chain. In business timing is everything, and when it comes to energy the time is now. So what’s your company saying about it? And even more important, what’s it doing?

–Ed Sperling

We’re about to find out if they’re right. Stacking die will, to a much greater extent, decouple analog from digital and leave it open for examination. That may help to explain at least part of the motivation behind Synopsys’ proposed purchase of Magma Design Automation this week. Analog engineers, who have spurned automation flows in favor of point tools, will now have to play in the same sandbox as engineers working on other chips—and on the same time-to-market schedule.

They also will have to be part of the overall team that tackles power budget issues, which means trimming wherever possible. This isn’t so easy in analog, because maintaining high signal-to-noise ratio is more difficult in noisy environments. Moreover, in stacked configurations they won’t always know what chips will go where and what kinds of physical effects those other chips will have on their analog functionality. More analysis in this area will help, but with die thinned to as little as 50 microns and connected by TSVs, which can reverberate noise, this will be a major challenge.

Tools will help—particularly system-level tools that can analyze all pieces of the design early in the process. What-if tradeoffs will be necessary at the architectural level, and analog will be a key component in those decisions. Turning on and off analog die and/or blocks also is different than digital blocks. And process variations will affect each of them differently.

But no matter how different these worlds, they are now about to become part of the same team—along with software engineers, who often don’t even attach the same meanings to words. In many ways, stacked die will become a melting pot of talent—and they will expose rather vividly where the flaws are.

–Ed Sperling

This is an interesting shift, and it will drive sweeping changes that will affect all parts of the semiconductor supply chain, from design to manufacturing and everything in between. One of the biggest changes will be in the supply chain itself. Unlike performance, which can be localized, power is a system-level consideration. A processor may increase or decrease in clock frequency, and the materials and structures used to create it may change, but it doesn’t necessarily affect everything inside an SoC.

Power does. There is only one power budget for a system. Moreover, that power budget has to be managed from the architecture, to the IP that’s chosen or developed, all the way to the process and materials used to create it. It also requires much more collaboration at each step from design through manufacturing, with information flowing in two directions instead of just one.

This isn’t new to the IDM world, but it is unique for a disaggregated supply chain. Until the mid-1990s, information always flowed in two directions because companies had their own fabs. It wasn’t until the cost of digital processes began exploding that companies began regarding process data as proprietary. But those escalating costs also have caused a shakeout in the leading edge of the foundry business, which allows the survivors to be more comfortable with sharing that data.

It’s a good thing, too. Collaboration will be essential for adding making SoC designs more energy efficient. These new chips will require new structures, new packages, well-tested and characterized IP, better-written software, new materials and potentially new business models and strategies. But it also will require many of the basics that have made IC development so successful over the past 50 years—a determined focus by lots of smart people working together to solve some very difficult problems.

Fortunately, most of the pieces are in place to begin this shift. Now the question is what kinds of advances can be made, where the roadblocks will be, and how we will get around them. This is an industry that was supposed to come to a grinding halt at 1 micron. The next challenge is to deliver the same functionality of a desktop computer on a mobile device with no loss in performance, at a reasonable cost, using the same battery technology that currently doesn’t even last a day of continuous use. It will be done. The only question is when, with what new approaches, and by whom.

–Ed Sperling

There also is much more that can be done to improve energy efficiency, ranging from writing more efficient software code to dropping the voltage in devices, changing out the substrate material and widening the I/O channels while also shortening the distances signals have to travel. Memory can be matched more efficiently to processors, and processors can be customized for specific functions or applications.

That this can be done at all is a testament to the advances in semiconductor engineering. After 60 years, engineers have become incredibly proficient at solving problems at the nanometer level—and probably soon in distances that will best be measured in Angstroms.

The only challenge now will be the intersection of technology and money. Can all of this be done for a reasonable cost? And if it can’t, then who’s going to take the hit?

These kinds of questions need to be answered rather soon. In a disaggregated ecosystem with extremely complex technology, having even closer partnerships will be a prerequisite to progress. Companies already are pouring millions of dollars into joint development efforts, but they also need to feel as if they’re reaping equal returns from that effort. So far, this hasn’t been a problem because these efforts are relatively new. But as time goes on, the real friction point may be less about the technology and processes being jointly developed and more about the value of that investment to each of the partners.

We are headed into some of the thorniest, as well as the most interesting, problems ever encountered in IC design. Power is front and center in all of this, and from the looks of it solving these issues won’t be cheap. In fact, it likely will be beyond the scope of any single company, no matter how large its pile of cash. The question now is what the leverage points will be for companies working together and how they will shape or reshape the industry.

–Ed Sperling

This is the subject of research inside of dozens of companies and universities, and there are several different approaches being taken. The reason is that while existing performance levels will suffice for awhile, particularly in mobile devices, the competitive edge in the future will be provided by faster searches, connections, better quality for streaming video and—yes—fewer dropped calls. But it will all have to happen using a battery that can last a day or more between charges, even while operating at full tilt. And it also will have to happen using existing battery technology, because improvements in that area are extremely slow.

There are four main approaches to this problem. One is to develop chips that can power down and up much more quickly, with much bigger swings between the two. Work in this area ranges from different memory technology to different gate structures and new materials.

A second well-publicized approach is the 2.5D and 3D stacking of die. The advantage with stacked die is that it takes less power to drive signals because the distances are shorter and the pipes through which signals travel—either TSVs or interposers—are much wider. The challenge in this area will be getting packaging costs under control and providing a more consistent TSV manufacturing process.

A third approach will be to supplement this with some sort of energy scavenging technology that can either power devices or simply amplify the signal so that mobile communications require far less power. Work is under way to improve base station technology, as well, so that signals can be shared across multiple towers.

And finally, there is work under way to significantly lower the operating voltage inside of SoCs, which is probably the longest-range approach because it will require changes at the gate level and in memory to be able to retain data and functionality.

It’s likely that no single approach will suffice. A combination of two or more of these approaches may be be necessary, along with tweaks at every level to reduce leakage, improve throughput, eliminate bottlenecks and minimize physical effects. Taken separately each of these approaches represents a big step forward, but taken together they can change the power/performance equation forever.

–Ed Sperling

The problem is that while people are buying these new devices in record numbers, they’re actually consuming more energy than in the past. That may explain why the number of complaints about smart phone battery life is on the rise. In fact, these complaints are almost ubiquitous these days, largely because smart phones have replaced basic phones.

While it’s true that users can do more with a smart phone than a regular phone—they can text with ease, search, stream videos, add GPS devices—all of that requires additional energy, not less energy. The chips inside are more efficient, but they’re also doing more. And while tablets and the latest generation of laptops are significantly better on battery life than previous versions, they’re also being used longer and often in addition to existing desktops and laptops.

The world is certainly going more mobile. It’s more connected than ever before. And it’s consuming and generating more information at a faster rate and with more consistency. But all of that takes power. And no matter how efficient the devices, the sheer volume of them, coupled with a rising amount of information to process, will take more energy.

There are two ways to reverse this trend. One, of course, is to cut back on usage, which is unlikely to happen. The floodgates are open, and information will continue flowing in all directions, even if much of it is useless, misleading, or just plain wrong. Conservationists have been warning of impending danger since at least 1306, when the first known air-pollution restriction was enacted in London.

The second path is to figure out better ways of providing energy for these devices, and work is underway in this area through a slew of efforts into renewable energy sources and energy scavenging. We’ve figured out how to create these devices. Increasingly, we’re figuring out even better ways to regulate their usage. The next step is to figure out better ways to power them up. This is where the real effort needs to be for our wildly escalating consumptive habits to continue.

–Ed Sperling