While SoC developers in the mobile space continue to develop power-management capabilities, the reality is many of them either are ignored or underutilized by the system makers. Whether a battery lasts an extra hour often is less important than getting a functioning product to market on time and on budget.

In the enterprise space, better energy efficiency can mean millions of dollars in electricity costs each year, both for powering big iron and for cooling it. That means companies are willing to pay for technology that will reduce costs. They’re also willing to pay for the tools to design and cool data centers, which is partly why Mentor Graphics’ thermal modeling software has done so well.

But what’s equally good from a design and development standpoint is that enterprise buyers are methodical and cautious. The cost of getting something wrong and having server or storage outages can impact a corporation’s quarterly earnings, its stock price, and even its competitive standing in a market. That means they’ll wait for new technology even if it takes a few extra months, and they’ll fund the research.

The big technology investment is still in the mobile area. Billions of devices, even with lower margins, are a bigger market than one with thousands of devices with higher margins. But as data moves from mobile to server and back again, there is an interesting crossover because everything has to work together. That means some of the power management techniques developed in the mobile world will find their way into the enterprise. And some of the techniques developed in the enterprise—virtualization, multiprocessing, and security—will find their way into the mobile arena.

Specializing in one or the other will no longer an option, and we are witnessing the first pieces of that shift. What will be interesting to watch is just how closely these two worlds converge, and what happens when they really do come together.

—Ed Sperling

Research is already well under way in these areas. TunnelFETs use electrons to literally tunnel through the walls of a device such as a nanotube or nanostructure. Atomic-level memory slashes the size and power needed to retain data. Foundries are seriously looking at self-assembly of atoms inside templates rather than waiting for EUV lithography. And substrates such as fully depleted silicon on insulator (SOI) with exotic thin films are looking far more promising for some pieces of an SoC.

Stacking of die will change the dynamics of who actually interacts with these advanced technologies and processes, as well. For the most part, it will be everyone. To gain economies of scale, platforms for highly advanced logic and memory will make their way into nearly all designs—amortized across many vendors’ packaged products rather than just a few. We saw this trend begin in cell phones and in processor cores. It will escalate over the next few process nodes, including a raft of knobs to turn for better performance or better energy efficiency—or both.

These knobs are the result of very significant changes at the most basic level. A better understanding of atomic structures and how to manipulate sub-atomic particles—in all likelihood we will actually be able to photograph them over the next decade, thereby turning theoretical physics into observable physics—opens the doors to vast new possibilities. Already graphene sheets—lattices that are one atom thick—are being doped to behave as if they are in magnetic fields even when they aren’t. That can affect the path of electrons, the speed at which they travel, and the energy required to manipulate them.

These changes also mean we can pack everything together more densely, move subatomic particles more effectively, and gain control of a world that until now has been largely a mathematical model. And it will carry over into the realm of software, which may be increasingly be as much about the control of those subatomic particles as the exchange and flow of bits of data.

All of this is evolutionary. It builds on research, manufacturing techniques, IC design, and the confluence of software, hardware, and physical problems that are already being addressed. But it’s all coming together at future process nodes, which will open the door into a much larger world that no one has ever effectively controlled before. The result, to say the least, should be very interesting.

—Ed Sperling

There are rumblings that’s about to change. Top systems companies are talking about ramping up the pressure to really cut the top-line number as more electronics go mobile. This is significant, because to win a socket—not to mention literally avoid burning the hands that feed even vertically integrated chipmakers—that overall budget has to shrink accordingly.

Some of this will be relatively easy. Many chips already come with sophisticated power management schemes that are rarely utilized by OEMs. Just turning on the features, and turning off more of the chip when it’s not in use, is pretty straightforward. Just changing the substrate to materials such as fully depleted silicon on insulator can help control leakage.

Some of it will be more difficult. A bridge between hardware and software will have to be constructed, which means automation tools will have to dig much deeper into new areas and provide a sort of Rosetta stone that provides feedback to hardware and software engineers about how each development throughout a flow affects the other side. Just being able to provide that kind of detail to software engineers can go a long way in helping reduce power and improve performance.

And some of it will consist of amazing engineering feats like the ones that have dotted the history of semiconductor design. Solving issues such as stacking die, reducing physical effects and being able to do more with less become more difficult as the laws of physics begin playing a bigger role in shrinking designs. We are already at the point where we can see a clear role for carbon nanotubes, graphene, tunnelFETs and atomic memory, not to mention new insulation and manufacturing schemes that are beginning to look more viable. A shrinking power budget runs through all of these schemes, interlaced with business and technology issues and greater integration with a much larger system.

How all of this unfolds, and what a flow ultimately looks like remains to be seen. But power, along with shrinking processes, will force changes in every part of design—and dramatically reduce the silo approach that currently defines the ecosystem. Cutting the power budget will only hasten these changes, and so far no one seems to know what the result will be.

–Ed Sperling

But getting the power management features already being built into chips to be fully understood and utilized by the companies assembling systems may be an even bigger problem. Software has to be written to make these kinds of tradeoffs, and software always lags hardware. That’s true at the embedded level inside of chips—or processor cores or various subsystems—and it’s true at the system level. The dirty secret in software development is that it can never be fully tested until it’s in the hands of consumers or businesses, which is one of the key reasons why they’re constantly barraged with updates.

That doesn’t mean all software updates are fixing bugs, of course. New features and capabilities are added through these updates, as well, which ultimately slow or kill older hardware unless the software is completely removed and new software is loaded. But the real challenge remains finding all the unexpected and unplanned interactions that can negatively affect a device.

Power concerns are the last in a long line of problems that need to be dealt with along the way from conception to implementation. Software is needed to manage power-saving features, but software teams are stretched so thin that their main concern is just getting the device to function reasonably well. Even the biggest companies have trouble with this. Apple is probably the best-known example, but Intel has had its share of issues with chip projects that have been quietly killed because of thermal issues. And these are two of the best-funded, vertically integrated companies that typically focus on the bleeding edge of power and performance. Data centers are full of server racks where power issues have crept in slowly over a span of several decades.

It gets worse in a supply chain where chips are chosen for a socket based primarily upon area, performance and cost. Power is a “nice-to-have” concern, and it may even cement a deal, but the software teams inside of companies under intense market pressure to get increasingly complex products to market on time and on budget generally consider power last—and sometimes not at all. Good enough may not be optimal, but it’s better than missing a deadline.

What’s becoming clear is that the real challenge isn’t getting hardware engineers to think about power issues. They’re already well down the road to solving some intensely complex issues. It’s also not a blame game, because software engineering teams are achieving some unbelievable coding feats of their own. The problem is adding capabilities that allow software teams to take advantage of advanced power features in the hardware without slowing them down.

This is way outside of the normal focus of tools developers on both the hardware and software side, and it’s even outside the realm of hardware-software co-development. But it’s something that needs to be done to even utilize the power features that are already being developed. Opportunity is knocking, but it appears that the the sound has been turned off to save the battery.

–Ed Sperling

What that means is that there will not be a single solution to reducing power. It can’t be fixed anymore just with a new process technology or by shrinking feature size. Instead, it has to be conceived at the front end and addressed in small increments at every step of the design process all the way through to manufacturing.

This raises several challenges:

1. Power cannot have a significant impact on design time or cost or there won’t be a market for the chips. That means new tools, new understanding of how power will affect designs at every step of the flow, and new flows that are power-aware, with an emphasis on physical verification and yield using low-power processes.
2. Power issues must be dealt with holistically. Because power budgets are flat from one generation to the next, any increase in one area will require decreases in others. Moreover, they will have to be properly timed—which is no simple task—to avoid creating hotspots. Turning off one area of a chip without considering when another area is active and generating heat can cause all sorts of unwanted physical effects.
3. Tools will be needed to fine-tune designs based upon power, and they need to be able to test them with the same granular approach. As Halepete noted, on, off, power-down, power-up states can be interlaced much more densely using automation than even the best designers can do today—and that’s the lowest hanging fruit.

Power has been recognized for several nodes as being a global issue for design. It is now a global issue for entire systems, whether it’s a smartphone or a car. Moreover, it spans everything from initial architectural conception to manufacturing and final test. But what’s changing is that it now also has to be dealt with by everybody, at every stage, and inside of every tool.

–Ed Sperling

At the center of this cornucopia of challenges is power, because more functions and more things now have to fit into a power budget that remains fixed. While some components in a complex SoC may run at lower voltages, you can be assured that others will run hotter and at higher voltages—at least during peak demand for a logic subsystem or a processor core. And the spikes that result still have to be taken into consideration and modeled effectively enough so they don’t burn a hole in the chip or otherwise render it inoperable.

So what’s different? Power is no longer just a factor in design. It has become a starting point that is every bit as important as function. The two are intertwined like some Gordian knot. And whatever is considered the maximum voltage is probably already too high at advanced nodes and inside of stacked die. More area has reduced the opportunity to solve some problems with guard-banding because the overhead is unacceptable, both from a cost and performance standpoint.

There are some exotic solutions being considered. Microfluidics pulsing liquid through a chip really can cool it effectively. But designing this kind of mechanical microchannel architecture where liquid is propelled through tiny chambers isn’t isn’t in the budget for most chips–and possibly not any chips. And, of course, it’s not very convenient to carry around a container of liquid nitrogen with your portable device.

The more realistic solutions will come in two places. One is from the design side, where stacking and Wide I/O have the ability to dramatically reduce the amount of power needed to drive signals by reducing the distances and widening the channels. The EDA industry is just beginning to take this approach very seriously.

A second solution will come on the manufacturing side in a couple of areas. One is new structures—FinFETs, carbon-nanotube FETs, tunneling FETs—which control leakage much more effectively than planar FETs. It remains uncertain whether EUV will ever become commercially viable or whether self-assembly—using a template that allows finFETs to literally set up automatically on a substrate—will replace it. The second part of this comes from new materials, such as fully depleted silicon on insulator and new gate oxides and insulating strategies, such as air gap, which can better control leakage.

But in all cases power will remain one of the key components of design, from the initial architecture stage to final manufacturing signoff and test, and touching everything in between from ESL models to RTL and verification.

–Ed Sperling

Why? Because unlike the mobile space, where you need billions of units to make margins, in the corporate enterprise you only need millions. Those extra zeroes can mean a lot for IP and tools sales, as well as processor core margins.

Even better, in the mobile world it’s the OEMs that usually determine the price and what technology gets sold. In the enterprise, the customers have a much stronger hand in what they buy—and a lot more negotiating power.

That doesn’t mean change comes quickly in the corporate enterprise. If there are big savings to be had, then corporations will do the necessary number crunching and determine what changes are worth the risk and new investment. Enterprise computing remains one of the most conservative bastions of technology on the planet because so much is riding on consistency and uptime. But once changes are approved, fully tested and rolled out, they tend to provide a steady stream of revenue for years—and sometimes even decades.

The obvious improvements in server utilization through virtualization have already been implemented. Private clouds are also being installed inside of companies to centralize computing and make it more efficient, as well as more secure. The next step is to improve the efficiency even further, either with more efficient processors or more efficient storage, such as solid-state drives. And wherever possible, companies will improve their software, leveraging open source whenever they don’t need a proprietary application and a specific operating system.

The movement by EDA and IP vendors into this space isn’t just a fluke, and it will likely ramp up over the next couple years as the trend toward efficiency continues to pay measurable dividends for large corporations. But it remains to be seen just how large of a dent these companies can make in a market that was considered almost impregnable market fortress just several years ago. If they are successful, these and other companies could find a huge new opportunity for their expertise in design, low-power engineering and the power-performance-area equation. If not, we will likely see this effort quietly slip into the background without much notice.

–Ed Sperling

Since then there have been steady predictions that display resolution had maxed out. Those predictions were proved wrong because companies figured out how to power down those displays quickly enough to be able to prolong battery life sufficiently. And while the display still is estimated to consume half the battery, battery times continue to grow along with display quality.

There are some tricks being used, of course. Granularity allows displays to control pixels better than in the past. Backlighting can be improved with LEDs to limit the overall energy consumption. And streaming doesn’t require the same quality display as a photograph.

Still, these tricks can only go so far. More megapixels in cameras, better graphics in games and smoother motion all require more battery life, which means that what is lost in one place has to be made up in another. This is where things get interesting. If battery technology is relatively fixed and display technology isn’t decreasing, then the next targets are logic, transport fabrics and architectures, and memory.

The only way to make significant dents here are to rethink how processors are used, what runs on top of them—the entire software stack—and how chips are packaged together. This is an architecture issue, and the next likely solutions are more reliance on the GPU and other application-specific processors, shorter distances through stacking die, faster pipelines with wide I/O, and more rational usage of memory tied to more specific processor applications.

The direction is clear. To be competitive you need better display resolution, clearer sound and at least reasonable video quality, and to do that you have to make up the efficiency somewhere else. With battery technology improving only about 3% per year, that puts the onus on SoC engineering teams to come up with some significant improvements.

This is a big opportunity as well as a major challenge, and it’s one that likely will reshape the IC industry for the next decade. It’s also one that should provide huge growth for tools vendors that can support this next inflection point.

–Ed Sperling

What used to be in a device moved to a board, from a board there has been a perpetual push to put things in a chip. At one point, circa 2000, analog companies claimed that mixed signal chips were a thing of the past and that there would be separate analog chips in addition to digital chips. There may be again in 2.5D stacking, but the whole thing will still end up in a package with much shorter wires and greater bandwidth.

Even processors are converging with SoCs. Intel’s top execs have been saying more forcefully for the past few years that the future is SoCs, and that the bulk of Intel’s future revenues will come from SoCs rather than monolithic processors. While that has yet to materialize in Intel’s earnings reports, at least there is a nod from the world’s most successful chipmaker that more has to be integrated into a chip than in the past. Apple, which is a partner and a rival for Intel, has already migrated a good portion of its product line to SoCs. And Panasonic and Fujitsu are in talks with Renesas to create a single SoC giant in Japan.

But there are some unusual changes in this march toward convergence and consolidation that are also showing up in the market, mostly because of power issues. Power is now dragging other disciplines into the basic design and engineering of an SoC, determining what goes where, how it gets put together and by whom, and notably how it can be made more efficient and cooled.

Cary Chin’s blog this week about solar smartphones is a case in point. So is the increasing role of mechanical engineering in SoCs for everything from cooling closer to the core to MEMS sensors that eventually will be built on a stacked die to energy scavenging using a combination of electrical and mechanical approaches. There is even work underway in research labs for chemical engineering to generate energy inside of devices. And increasingly there is a feedback loop to the software world to improve efficiency in software engineering.

The question is what other disciplines will begin to take a front-seat position in SoC design. One big change on the horizon is in the area of physics, which has always been a combination of observed and theoretical. In the past five years we have been able to actually see atoms, but over the next decade the expectation is that we will start seeing subatomic particles. At that point, theoretical physics becomes observed physics, and after that anything is possible.

How much of this will remain in the IC realm, and how much will filter out into other areas is unknown. But one thing is certain—we’ve only scratched the surface of possibilities.

–Ed Sperling

At 28nm and beyond, there are other factors that begin to weigh into this discussion. One is reliability. Can a chip developed at the forefront of Moore’s Law be as reliable as one that is developed at older nodes? The gut reaction is yes, but the answer isn’t always so simple. The reason goes well beyond ensuring physical effects such as electromigration, cross-talk and even electron crashes don’t affect signal integrity. It also has to do with guard-banding—those extra wires and circuits put in to ensure the chip continues to work in the event of problems such as electromigration and even radiation effects—which can eat into both performance and energy efficiency.

Ultimately there may be ways to make up for some of this excess margin in 3D stacks. Overall margin can be held relatively constant by rationalizing memory usage for each processor on an SoC, particularly when there are multiple processors scattered throughout the design with dedicated functionality. This type of approach may take years before it becomes mainstream, however. In the meantime, designers will have to slim down the circuitry on their existing models and pray that it all works as planned.

A second reason, which is related, has to do with commercially available IP. Until now, the real value in IP is the speed and ease with which it can be implemented in a design. A Lego-like approach is a huge win when it comes to addressing time-to-market pressure. Being sure that an IP block or subsystem will work in any design is incredibly difficult, and it requires a lot of pre-characterization so designers know how it will perform in the context of a specific design. But flexibility also comes at a price, and again the problem is margin. The problem is that this time it’s from a supplier and it comes a ready-made black box that isn’t so easy to alter.

There are no simple answers to how to solve these problems, and there certainly is no single answer. The only thing that is certain is that these issues will become more glaring as we march forward to 20nm and 14nm, and power will continue to be the main driver for slimming margins on every front. The only question now is what the ultimate cost will be.

–Ed Sperling