Over the past couple of years the electronics industry has woken up to the fact that saving energy and prolonging battery life is a very good thing. It can be marketed, used as a differentiator, and companies can charge a premium for battery-saving technology.

In high-end devices, the incremental cost of adding even additional processors tends to get buried. In extremely price-sensitive markets, it will not be. So one big question beginning to percolate around the industry is just how lucrative this extended battery life will be. Will it just be the high end of the laptop, smart phone and tablet markets? Or will it also carry over into the second-tier versions of these devices, where volume is significantly greater but budgets are tighter?

These are important questions for engineers, even though they may seem one step removed, because it affects their development budgets. Those budgets are used for training, for hiring more engineers, and ultimately for boosting compensation of team members.

The issues here are both convenience and electricity costs. The convenience is well known. If you don’t have to charge a device immediately after extended use, or you can use your laptop productively flying between San Francisco and Beijing without worrying about plugging it in, that’s both convenient and a major productivity gain.
But in price-sensitive markets, the cost of charging a device also enters into the picture, and a similarly priced efficient device will probably win over one that is less efficient.

So given that the demand for low-power engineering is growing, who’s actually reaping the rewards for all of this effort? Is it incremental or just a prerequisite for winning a design? And will that change in the future?

–Ed Sperling

For the past five decades, the tradeoffs in IC design have always been between power, performance and area. Performance dominated for most of the history of IC development—remember the MIPS and MHz/GHz wars—followed closely by area because of the need to cut costs.

Over the past few years, power has moved from an afterthought to the front of the pack because of the emphasis on mobility and battery life. Even in data centers, power has suddenly emerged as the low-hanging fruit for cutting energy costs.

In the future, engineers will have to consider another factor: function. Just as power is a global issue—it affects all parts of a device rather than just a single portion of an SoC, for example—function has a direct effect on area, power and performance. Adding more functions, or enhancing those functions, requires tradeoffs, re-thinking and sometimes re-engineering every facet of PPA.

The real driver behind this shift in functional importance is the need to do more useful things with portable electronics. It’s not enough just to check e-mail or make voice calls anymore. Devices now need to stream video, do intensive graphics for gaming, and increasingly they need to do real work such as spreadsheets and document creation.

But they don’t necessarily need to do it as well as a powerful desktop computer with all the same options, which can save on power, performance and area. The 80/20 rule applies here, and it’s being looked at carefully by the engineers who create the specs for devices. You don’t have to do everything to perfection. You just have to do it well enough to make it useful.

To accomplish this also requires tradeoffs. Slick interfaces such as voice commands may require more energy to stay awake and responsive, which means less performance and a lower power budget for other portions of an SoC. This helps explain the proliferation of multicore and multiprocessor architectures optimized for individual functions rather than trying to power up and power down a single processor that offers maximum performance for a function that doesn’t require it.

Stacking of die will improve this recipe even further. Being able to directly connect to portions of memory rather than sharing resources will make individual functions much more controllable from a PPA standpoint. But as we begin building these 2.5D and 3D stacks, increasingly it will be function that determines PPA rather than the other way around.

–Ed Sperling

One of the common complaints from around the semiconductor industry is that design teams don’t get recognized. Appreciation comes readily to brands such as Apple or Samsung, but it is several levels of abstraction removed from the companies that develop the processors, let alone the tools, materials, methodologies or processes that make those processors possible.

Worse, energy efficiency has long been at the bottom of the list of attributes that consumers of technology recognize as critical. Historically it has been a nice-to-have feature, but the real battle was between cost, features, and those annoying delays that are equated with performance. In fact, until recently, many of the power-saving features that were painstakingly developed by design teams were completely ignored by device manufacturers.

That’s changing, of course. More features, particularly streaming video and gaming, mean even more energy-efficient designs are required. And being able to eke more battery life out of a design has now become a competitive advantage. Being able to carry around a charger with a device is not. And even in data centers, being able to keep performance consistent while chopping energy bills for both powering machines and then cooling them is being closely watched.

Blame flows downhill rather quickly. Recognition does not. In fact, sometimes it never reaches the bottom. But that recognition is necessary because it often is directly tied to higher profits, providing the market isn’t grossly overcrowded. With the focus on efficiency, there is plenty of room for companies to stretch out and find a sparsely populated niche—providing they can get recognized for it.

Many engineering-driven companies assume they will win if they create the best products. That’s increasingly true with low-power designs. But reaping the full rewards of their efforts requires them to be able to think up several levels of abstraction in the supply chain and to market the end-customer benefits and options. This is marketing at its finest, and it’s something engineering-driven companies don’t do very well even in the best of times, let alone when markets become overcrowded and mature.

Energy is a new wrinkle in all of this. It’s resonating with the end customer, the device manufacturer and all the way throughout the supply chain. In business timing is everything, and when it comes to energy the time is now. So what’s your company saying about it? And even more important, what’s it doing?

–Ed Sperling

The shift into stacked die, expected to begin late next year with a big ramp in 2013, will shine a spotlight on analog design and its effect on power. For years, analog engineers have bragged about just how efficient their portion of a chip was versus digital.

We’re about to find out if they’re right. Stacking die will, to a much greater extent, decouple analog from digital and leave it open for examination. That may help to explain at least part of the motivation behind Synopsys’ proposed purchase of Magma Design Automation this week. Analog engineers, who have spurned automation flows in favor of point tools, will now have to play in the same sandbox as engineers working on other chips—and on the same time-to-market schedule.

They also will have to be part of the overall team that tackles power budget issues, which means trimming wherever possible. This isn’t so easy in analog, because maintaining high signal-to-noise ratio is more difficult in noisy environments. Moreover, in stacked configurations they won’t always know what chips will go where and what kinds of physical effects those other chips will have on their analog functionality. More analysis in this area will help, but with die thinned to as little as 50 microns and connected by TSVs, which can reverberate noise, this will be a major challenge.

Tools will help—particularly system-level tools that can analyze all pieces of the design early in the process. What-if tradeoffs will be necessary at the architectural level, and analog will be a key component in those decisions. Turning on and off analog die and/or blocks also is different than digital blocks. And process variations will affect each of them differently.

But no matter how different these worlds, they are now about to become part of the same team—along with software engineers, who often don’t even attach the same meanings to words. In many ways, stacked die will become a melting pot of talent—and they will expose rather vividly where the flaws are.

–Ed Sperling

Over the past five decades, Moore’s Law has been a powerful guiding principle for shrinking process geometries and improving performance. But with performance now considered secondary to energy and power efficiency, the same forces that have worked to commoditize performance increases while slashing costs will be applied to saving battery life and drawing less energy from the wall.

This is an interesting shift, and it will drive sweeping changes that will affect all parts of the semiconductor supply chain, from design to manufacturing and everything in between. One of the biggest changes will be in the supply chain itself. Unlike performance, which can be localized, power is a system-level consideration. A processor may increase or decrease in clock frequency, and the materials and structures used to create it may change, but it doesn’t necessarily affect everything inside an SoC.

Power does. There is only one power budget for a system. Moreover, that power budget has to be managed from the architecture, to the IP that’s chosen or developed, all the way to the process and materials used to create it. It also requires much more collaboration at each step from design through manufacturing, with information flowing in two directions instead of just one.

This isn’t new to the IDM world, but it is unique for a disaggregated supply chain. Until the mid-1990s, information always flowed in two directions because companies had their own fabs. It wasn’t until the cost of digital processes began exploding that companies began regarding process data as proprietary. But those escalating costs also have caused a shakeout in the leading edge of the foundry business, which allows the survivors to be more comfortable with sharing that data.

It’s a good thing, too. Collaboration will be essential for adding making SoC designs more energy efficient. These new chips will require new structures, new packages, well-tested and characterized IP, better-written software, new materials and potentially new business models and strategies. But it also will require many of the basics that have made IC development so successful over the past 50 years—a determined focus by lots of smart people working together to solve some very difficult problems.

Fortunately, most of the pieces are in place to begin this shift. Now the question is what kinds of advances can be made, where the roadblocks will be, and how we will get around them. This is an industry that was supposed to come to a grinding halt at 1 micron. The next challenge is to deliver the same functionality of a desktop computer on a mobile device with no loss in performance, at a reasonable cost, using the same battery technology that currently doesn’t even last a day of continuous use. It will be done. The only question is when, with what new approaches, and by whom.

–Ed Sperling

Some of the hardest stuff is already done when it comes to saving power. Many engineers are quite well versed in managing multiple power islands and designing with sometimes dozens of voltage rails. There has even been massive progress in controlling gate leakage through a variety of materials and now 3D structures.

There also is much more that can be done to improve energy efficiency, ranging from writing more efficient software code to dropping the voltage in devices, changing out the substrate material and widening the I/O channels while also shortening the distances signals have to travel. Memory can be matched more efficiently to processors, and processors can be customized for specific functions or applications.

That this can be done at all is a testament to the advances in semiconductor engineering. After 60 years, engineers have become incredibly proficient at solving problems at the nanometer level—and probably soon in distances that will best be measured in Angstroms.

The only challenge now will be the intersection of technology and money. Can all of this be done for a reasonable cost? And if it can’t, then who’s going to take the hit?

These kinds of questions need to be answered rather soon. In a disaggregated ecosystem with extremely complex technology, having even closer partnerships will be a prerequisite to progress. Companies already are pouring millions of dollars into joint development efforts, but they also need to feel as if they’re reaping equal returns from that effort. So far, this hasn’t been a problem because these efforts are relatively new. But as time goes on, the real friction point may be less about the technology and processes being jointly developed and more about the value of that investment to each of the partners.

We are headed into some of the thorniest, as well as the most interesting, problems ever encountered in IC design. Power is front and center in all of this, and from the looks of it solving these issues won’t be cheap. In fact, it likely will be beyond the scope of any single company, no matter how large its pile of cash. The question now is what the leverage points will be for companies working together and how they will shape or reshape the industry.

–Ed Sperling

A new race is beginning in the SoC world. While performance has been supplanted by battery life as the top goal for the next process node, that prioritization isn’t going to last. The ultimate challenge will be to achieve both—higher performance with substantially lower power.

This is the subject of research inside of dozens of companies and universities, and there are several different approaches being taken. The reason is that while existing performance levels will suffice for awhile, particularly in mobile devices, the competitive edge in the future will be provided by faster searches, connections, better quality for streaming video and—yes—fewer dropped calls. But it will all have to happen using a battery that can last a day or more between charges, even while operating at full tilt. And it also will have to happen using existing battery technology, because improvements in that area are extremely slow.

There are four main approaches to this problem. One is to develop chips that can power down and up much more quickly, with much bigger swings between the two. Work in this area ranges from different memory technology to different gate structures and new materials.

A second well-publicized approach is the 2.5D and 3D stacking of die. The advantage with stacked die is that it takes less power to drive signals because the distances are shorter and the pipes through which signals travel—either TSVs or interposers—are much wider. The challenge in this area will be getting packaging costs under control and providing a more consistent TSV manufacturing process.

A third approach will be to supplement this with some sort of energy scavenging technology that can either power devices or simply amplify the signal so that mobile communications require far less power. Work is under way to improve base station technology, as well, so that signals can be shared across multiple towers.

And finally, there is work under way to significantly lower the operating voltage inside of SoCs, which is probably the longest-range approach because it will require changes at the gate level and in memory to be able to retain data and functionality.

It’s likely that no single approach will suffice. A combination of two or more of these approaches may be be necessary, along with tweaks at every level to reduce leakage, improve throughput, eliminate bottlenecks and minimize physical effects. Taken separately each of these approaches represents a big step forward, but taken together they can change the power/performance equation forever.

–Ed Sperling

The wave of portable devices being sold these days are far more energy-efficient than in the past, and viewed in isolation they constitute a major step forward in the push toward a greener world.

The problem is that while people are buying these new devices in record numbers, they’re actually consuming more energy than in the past. That may explain why the number of complaints about smart phone battery life is on the rise. In fact, these complaints are almost ubiquitous these days, largely because smart phones have replaced basic phones.

While it’s true that users can do more with a smart phone than a regular phone—they can text with ease, search, stream videos, add GPS devices—all of that requires additional energy, not less energy. The chips inside are more efficient, but they’re also doing more. And while tablets and the latest generation of laptops are significantly better on battery life than previous versions, they’re also being used longer and often in addition to existing desktops and laptops.

The world is certainly going more mobile. It’s more connected than ever before. And it’s consuming and generating more information at a faster rate and with more consistency. But all of that takes power. And no matter how efficient the devices, the sheer volume of them, coupled with a rising amount of information to process, will take more energy.

There are two ways to reverse this trend. One, of course, is to cut back on usage, which is unlikely to happen. The floodgates are open, and information will continue flowing in all directions, even if much of it is useless, misleading, or just plain wrong. Conservationists have been warning of impending danger since at least 1306, when the first known air-pollution restriction was enacted in London.

The second path is to figure out better ways of providing energy for these devices, and work is underway in this area through a slew of efforts into renewable energy sources and energy scavenging. We’ve figured out how to create these devices. Increasingly, we’re figuring out even better ways to regulate their usage. The next step is to figure out better ways to power them up. This is where the real effort needs to be for our wildly escalating consumptive habits to continue.

–Ed Sperling

Prior to the invention of the railroad, the fastest anyone or anything traveled on the planet was the fastest horse, which is what made horse racing particularly interesting for centuries. And most SoC designers are old enough to remember the days when overnight delivery was considered a good thing. Even the Millennials are old enough to remember hourglasses on the screen, and the X Gens can easily remember the sound of dial-up modems making a connection.

It’s not unusual to go into an office and see someone cursing their PC because the back-end system is slow. And most people don’t have the patience to deal with a slow site. They simply move on to another site.

We have very rapidly—in the span of 10 years—become a global community of impatient people. Waiting is the enemy. And while this probably will have some really weird psycho-social effects in the long term, it’s also changing the dynamics of how we communicate. We seem to be very tolerant of dropped calls, but we are absolutely livid when a search function is slow or a streaming video gets interrupted.

And all of this leads to the next piece of the equation—how to provide sufficient performance to satisfy the most time-obsessive consumers while allowing them to go longer between charges.

This will likely be tackled in several ways. First, the battery charge issue will have to be addressed from some sort of energy scavenging rather than battery improvement. There are some interesting technologies being developed today that will provide watts rather than microwatts of power. You might even be able to use this kind of generation capability to charge your household in case of a power outage.

Second, SoC designs will have to be done in an increasingly holistic manner, incorporating everything from hardware to the full stack of software so that applications are provided the right amount of performance and energy. One size fits all no longer works, and it will look increasingly obsolete in a 2.5D or 3D stack.

Finally, more attention will need to be paid to the power of a signal and how that gets transmitted and used by a mobile device. It’s amazing how well a device works in airplane mode and how little battery it uses. That’s the base point for what can be done with a better baseband infrastructure.

This will all take time, of course. And by the time it all gets put in place, consumers will be clamoring for even fewer and shorter delays. This will provide plenty of work for SoC engineers for years to come, but they may have to work even faster than before, which will make them even less tolerant of delays in design flows. In the end, no one will escape this snowball.

–Ed Sperling

For years data center operations managers have been complaining that they can no longer cool racks of servers enough to bring them down to the maximum temperature. The increasing density of chips, thinner servers packed more tightly together and the usual current leakage have become so bad that it’s impossible to blow enough cool air through the server cabinets. In fact, it’s gotten to the point where noise of the fans blasting air has exceeded safe working limits.

There are several ways of dealing with this. One is to change from air cooling to water cooling. Water is much more effective at removing heat than air, and some of the newer data centers are being built using this method. IBM now offers a water-cooled option for its largest servers. The downside is that you need plumbing to make this work, limiting the flexibility of moving equipment in and out and raising the possibility of a different kind of very costly data leak. This is why plumbing was replaced by air cooling in the first place.

A second approach is to remove the cabinets entirely and allow air to flow freely through racks of servers. Companies such as Google and Microsoft reportedly have done this in places like the Columbia River Gorge. “Ambient” air, the stuff you blow in from the outside, doesn’t have to be chilled so it’s far less expensive to run these data centers. This is considered one of the greener approaches, and it works especially well in places where there is plenty of cool air and lots of wind. The Columbia River Gorge is a world-class windsurfing spot.

A third approach, and one introduced recently by Dell, is to change the maximum operating temperature of the servers themselves. Considering most of the maximum operating temperature of 80 degrees Fahrenheit was set decades ago, this is a strategy that has been long overdue for reconsideration. What isn’t known yet is how increased heat will affect the longevity of all components in a data center, but it does raise some interesting questions. If a data center can operate 33 degrees hotter than in the past, then it will require significantly less energy to run the chillers needed to cool the data center. And considering most of these operations are lights-out, anyway, the inconvenience to workers is minimal.

All three of these approaches are viable, and each has its place. Moreover, by combining some or all of these, the costs can be lowered even further. But why exactly did it take more than a decade of complaints and warnings before these solutions began rolling out?

–Ed Sperling