As CMOS size scale down, power challenges scale up. This tutorial shows why magnetic random access memory (MRAM) will help with power and integration needs.
Power verification often meanders into talk of the di/dt voltage drop across inductors. A high level water cooler primer of such topics ensues.
By Stephan Ohr, Gartner Powering the Internet of Things (IoT) is a special challenge, says Gartner analyst Stephan Ohr, especially for the wireless sensor nodes (WSNs) that must collect and report data on their environmental states (temperature, pressure, humidity, vibration and the like). While the majority of WSNs will harness nearby power sources and batteries, [...]
Chris A. Ciufo, Senior Editor An interview with Bob Burckle, Vice President, WinSystems discusses x86, ARM, and low power. WinSystems is one of those Tortoise and Hare kind of companies, often alternating between the two. The employee-owned Arlington, Texas company is progressive enough to literally rent out its parking lot for Dallas Cowboys tailgate parties [...]
By John Blyler Mentor Graphics recently held their annual User-2-User conference in San Jose. The press was invited and – as usual – got along well with the users. The day’s events were kicked-off by Simon Bloch, VP and GM for Mentor’s Design and Synthesis Division, who began his brief introduction by highlighting the new [...]
By John Blyler Designing embedded systems in energy-sensitive environments requires both attention to power details and a system-level view of overall energy architectures. Successful designers must embrace both perspectives. This isn’t easy. Most embedded hardware engineers are used to the fairly generous power offered by a wall socket or inexpensive traditional off-the-shelf batteries, where portability [...]
By John Blyler LPD: How does Linux 6 work with low power. Do you turn off certain parts of the chip that aren’t being used? Ready: There’s an analogy to the boot. It’s very dependent upon the capability of the underlying hardware and the mechanisms that are available to you. There is dynamic power management-that [...]
By John Blyler Max Domeika, senior software engineer in the Developer Products Division at Intel, sat down with LPE Consulting Editor John Blyler to talk about the growing importance – and intersection – of both the multicore and embedded markets. What follows are excerpts of that conversation. LPE: Intel’s software focus seems to be following [...]
By John Blyler The embedded processor market has now fully embraced the multicore world with the recent introduction of the dual core option for Intel’s Atom devices. Dual-core embedded processors offer designers many new benefits while presenting new challenges. How will the multicore option affect low power designs, virtualization, and single-threaded legacy software? Will these [...]
Low-Power Engineering sat down with Raj Nair, founder of Anasim Corp. and co-author of a recent book on power integrity. What follows are excerpts of that conversation.
John Blyler from Extension Media interviews Jell De Smet, a senior researcher on smart contact lenses, Centre for Microsystems Technology (CMST), imec and Ghent University. This video was shot during the Imec Technology Forum in Oct. 2013 in Leuven, Belgium.
- San Kun: Nice Article
Jim Kobylecky Besides, eating a coding rivet from time to time has to be a whole lot less painful than the alternative. Hmm,...
jblyler Hi Steve. Thx for the correction. I mentioned it to the editor and updated the post. Cheers. -- John
Windy Windy... DAC 2013 Pictures | JB's Circuit...
stevesliva Fab 8 in NY is GlobalFoundries, not Samsung. But they are qualifying the same process in Korea and Dresden/NY: http://www.globalfoundries.com/newsroom/press-releases/2011-press-releases/2014/03/01/globalfoundries-and-samsung-extend-fab-sync-to-new-high-performance-28nm-technology-for-mobile-applications
Samuel Ye The introduction of common database which are used among chip designers, package designer as well as systel solution...
Rodrigo Gonzalez Mr. Speers, in order to improve your post you should name the sources of all these power data. Best regards. Rodrigo...
Verifying the robustness of secure data access and the absence of functional paths touching secure areas.
How to identify design weaknesses, automatically repair the supply noise source, analyze the impact of dynamic voltage drop and verify power and signal EM.
While formal can be applied to entire blocks, it can be more valuable to apply it within blocks.
Learn more about a design-for-power methodology, from early in the design process at the RTL for maximum impact on power.
What technology and methodology are needed to verify the robustness of secure data access and ensure the absence of functional paths touching secure areas of a design.
A look at the challenges in designing smaller, faster and lower-cost products and how to enable comprehensive chip-package-system benefits across multiple disciplines.
Using the JasperGold low-power verification app to address power-aware verification challenges and requirements and overcome limits using traditional tools.
How to meet smart device requirements with high levels of sophistication and reasonable battery life.
Beginning early in the design process at the RTL level provides the largest impact on power.
Learn how to effectively manage design specifications (performance) and margins (price) with an accurate and predictive simulation-driven chip–package–system convergence methodology.