By Hamilton Carter About a year ago, John Blyler reported on several talks at the Ansys-Apache Design “Dimensions of Electronic Design” seminar. Those talks indicated that power-consumption design considerations were inexorably inching toward becoming the key concern at mobile SoC and IP design houses. It’s all fine and dandy that you can track your stock [...]
Trends Research Archive
Chris A. Ciufo, Editor-in-Chief intel’s 4th generation core (codename Haswell) was introduced in desktop, mobile versions and embedded versions. The architecture’s feature set is a boon to embedded designers. On June 3, 2013 Intel announced the 4th Generation Core processor family, code-named “Haswell.” As this announcement follows on the heels of the previous “Sandy Bridge” [...]
Chris A. Ciufo, Editor-in-Chief Monolithic AMD embedded G Series SoCs combine x86 multicore, Radeon graphics and a Southbridge. It’s one-stop-shopping, and it’s a flood targeting Intel again. The little arrow-like “a” AMD logo once represented an “upward and to right” growth strategy, back in the 1980s as the company was striving for $1.0B and I [...]
Chris A. Ciufo, Senior Editor Figure 1: Intel and the Linux Foundation collaborated on Tizen, an open source HTML5-based platform for smartphones, IVI, and other embedded devices. Samsung hedges Apple, Google bets with Intel’s HTML5-based Tizen Just when you thought the smartphone OS market was down to a choice between iOS and Android, Intel-backed Tizen [...]
By John Blyler Imagine pulling energy out of thin air and from significant distances from the source? This is one of the energy harvesting technologies that is being studies by Imec. Radio Frequency (RF) energy harvesters are different from typical induction charging systems like popular “power mats” an electric toothbrushes that require a nearby power [...]
By John Blyler and Staff For the past couple of process nodes chipmakers have been developing power-saving features that have been largely ignored by OEMs. That’s beginning to change. The need to do more and faster processing within the same or smaller power budget is forcing significant architectural changes, more efficient software, and new materials [...]
By John Blyler Lattice Semiconductor’s proposed acquisition of FPGA start-up SiliconBlue Technologies for $62 million in cash is the latest signal that the smart-phone market may be showing signs of overcrowding. While researchers are quick to point out the growth rates of smart phones sales versus computers, there also are an unprecedented number of companies [...]
By Hamilton Carter and John Blyler Legendary physicist and inventor, Nikola Tesla, conducted some of his most shrouded work in a forgotten lab at Wardenclyffe, NY. On November 5, 2011, that lab will come alive as the site of a major event (see Figure 1). Figure 1: QSL card image, created by ham radio cartoonist, [...]
By John Blyler The year was 1971. Intel had just introduced the first commercially available 4-bit microprocessor. Since that time, silicon-based semiconductors have ruled the world of electronics. Moore’s Law has successfully predicted the relentless march to ever high-performing and high-power microprocessors At roughly the same time, work began on semiconductors of a different type—the [...]
By John Blyler The trend in electronics is for ever-faster data transfers between and within System-on-Chip (SoC) devices. Higher speeds typically mean faster clock cycles, which translate into higher power usage and increased heat generation–a real problem for today’s energy sensitive data centers. Optical interconnects offer a promising alternative, especially with advances in silicon phonics [...]
John Blyler from Extension Media interviews Jell De Smet, a senior researcher on smart contact lenses, Centre for Microsystems Technology (CMST), imec and Ghent University. This video was shot during the Imec Technology Forum in Oct. 2013 in Leuven, Belgium.
- San Kun: Nice Article
Jim Kobylecky Besides, eating a coding rivet from time to time has to be a whole lot less painful than the alternative. Hmm,...
jblyler Hi Steve. Thx for the correction. I mentioned it to the editor and updated the post. Cheers. -- John
Windy Windy... DAC 2013 Pictures | JB's Circuit...
stevesliva Fab 8 in NY is GlobalFoundries, not Samsung. But they are qualifying the same process in Korea and Dresden/NY: http://www.globalfoundries.com/newsroom/press-releases/2011-press-releases/2014/03/01/globalfoundries-and-samsung-extend-fab-sync-to-new-high-performance-28nm-technology-for-mobile-applications
Samuel Ye The introduction of common database which are used among chip designers, package designer as well as systel solution...
Rodrigo Gonzalez Mr. Speers, in order to improve your post you should name the sources of all these power data. Best regards. Rodrigo...
Verifying the robustness of secure data access and the absence of functional paths touching secure areas.
How to identify design weaknesses, automatically repair the supply noise source, analyze the impact of dynamic voltage drop and verify power and signal EM.
While formal can be applied to entire blocks, it can be more valuable to apply it within blocks.
Learn more about a design-for-power methodology, from early in the design process at the RTL for maximum impact on power.
What technology and methodology are needed to verify the robustness of secure data access and ensure the absence of functional paths touching secure areas of a design.
A look at the challenges in designing smaller, faster and lower-cost products and how to enable comprehensive chip-package-system benefits across multiple disciplines.
Using the JasperGold low-power verification app to address power-aware verification challenges and requirements and overcome limits using traditional tools.
How to meet smart device requirements with high levels of sophistication and reasonable battery life.
Beginning early in the design process at the RTL level provides the largest impact on power.
Learn how to effectively manage design specifications (performance) and margins (price) with an accurate and predictive simulation-driven chip–package–system convergence methodology.