As CMOS size scale down, power challenges scale up. This tutorial shows why magnetic random access memory (MRAM) will help with power and integration needs.
Lawrence Loh of Jasper Design Automation talks about IP power specifications; what they should contain and how they might be best used.
Apache’s Aveek Sarkar meets with LPE to discuss power saving design techniques.
David Shippy of Altera, Lawrence Loh from Jasper Design, Mentor’s Steve Bailey, and Drew Wingard from Sonics got together to discuss the issues inherent in connecting IP blocks whether in a SoC or on stack die architecture.
What challenges await us? I choose hardware-software co-design; cyber-physical systems; wireless chips; low power; and motivating students to high-tech.
Here’s a short clip about the Imec’s stretchable, organic circuits. One potential application of this low-level light therapy (LLT) treatment for wrist Repetitive Strain Injury (RSI) or as a jaundice blanket for new born infants. The RSI application is being developed with Philips as part of the EU Project Place-It. http://www.place-it-project.eu/
John Blyler from Extension Media interviews Jelle De Smet, a senior researcher on smart contact lenses, Centre for Microsystems Technology (CMST), imec and Ghent University. This video was shot during the Imec Technology Forum in Oct. 2013 in Leuven, Belgium.
Power verification often meanders into talk of the di/dt voltage drop across inductors. A high level water cooler primer of such topics ensues.
By Stephan Ohr, Gartner Powering the Internet of Things (IoT) is a special challenge, says Gartner analyst Stephan Ohr, especially for the wireless sensor nodes (WSNs) that must collect and report data on their environmental states (temperature, pressure, humidity, vibration and the like). While the majority of WSNs will harness nearby power sources and batteries, [...]
Experts from ARM and Cadence share a checklist of experience for successful IoT device designs.
Low-Power Engineering sat down with month’s roundtable participants, Lawrence Loh, VP of Applications Engineering from Jasper Design Automation and Gary Smith of Gary Smith EDA to discuss low power engineering issues. What follows are excerpts from those interviews.
Embedded developers often talk about scalability and the design challenges of supporting a broad range of performance and cost options. But medical devices may provide some of the most dramatic examples of scalable designs. Look at medical imaging devices. At one extreme are million-dollar-plus magnetic imaging resonance (MRI) machines. For this typically room-sized equipment, the latest market opportunity may be for even larger, more powerful devices that can accommodate America’s growing number of obese patients and penetrate larger tissue mass. At the other extreme are swallowable capsules that include a tiny video camera, lights, transmitter and batteries to provide wireless scans of the small bowel while a patient carries on close-to-normal activities at home. Our experts discuss the evolutions and technologies that are driving both ends of this scale. With us are Steve Kennelly, senior manager, Medical Products Group, Microchip Technology Inc.; Dan Demers, sales and marketing manager, congatec; Cameron Swen, strategic marketing manager, AMD Embedded; and Matthias Huber, vice president of marketing for N. America, ADLINK.
By Hamilton Carter About a year ago, John Blyler reported on several talks at the Ansys-Apache Design “Dimensions of Electronic Design” seminar. Those talks indicated that power-consumption design considerations were inexorably inching toward becoming the key concern at mobile SoC and IP design houses. It’s all fine and dandy that you can track your stock [...]
By Cheryl Coupe As challenges such as security and multicore processing are addressed, Android and Embedded Linux find their way into new markets, moving from traditional smartphone applications to medical, automotive, mil/aero and M2M of every flavor. EECatalog: Android’s biggest appeal in embedded is its combination of Linux underpinnings, huge commercial momentum in smartphones, and [...]
John Blyler interviews Karen Lightman, managing director of MEMS Industry Group.
The Confab Influential manufacturing decision makers attend The Confab to collaborate about pressing challenges in the industry and how to achieve their future goals. John Blyler, VP, Chief Content Officer, Extension Media
Chris A. Ciufo, Editor-in-Chief intel’s 4th generation core (codename Haswell) was introduced in desktop, mobile versions and embedded versions. The architecture’s feature set is a boon to embedded designers. On June 3, 2013 Intel announced the 4th Generation Core processor family, code-named “Haswell.” As this announcement follows on the heels of the previous “Sandy Bridge” [...]
Chris A. Ciufo, Editor-in-Chief Monolithic AMD embedded G Series SoCs combine x86 multicore, Radeon graphics and a Southbridge. It’s one-stop-shopping, and it’s a flood targeting Intel again. The little arrow-like “a” AMD logo once represented an “upward and to right” growth strategy, back in the 1980s as the company was striving for $1.0B and I [...]
Chris A. Ciufo, Senior Editor An interview with Bob Burckle, Vice President, WinSystems discusses x86, ARM, and low power. WinSystems is one of those Tortoise and Hare kind of companies, often alternating between the two. The employee-owned Arlington, Texas company is progressive enough to literally rent out its parking lot for Dallas Cowboys tailgate parties [...]
Consumers’ love affair with always-available mobile devices shows no signs of waning. But as reliance on these devices grows, innovative power management can be a significant product differentiator. We talked to Evan Schulz, applications engineer for microcontroller products at Silicon Labs and Pradhyum Ramkumar, product marketing manager for MSP430 ultra-low power micro-controllers at Texas Instruments to get their advice on a range of new approaches.
John Blyler from Extension Media interviews Jell De Smet, a senior researcher on smart contact lenses, Centre for Microsystems Technology (CMST), imec and Ghent University. This video was shot during the Imec Technology Forum in Oct. 2013 in Leuven, Belgium.
- San Kun: Nice Article
Jim Kobylecky Besides, eating a coding rivet from time to time has to be a whole lot less painful than the alternative. Hmm,...
jblyler Hi Steve. Thx for the correction. I mentioned it to the editor and updated the post. Cheers. -- John
Windy Windy... DAC 2013 Pictures | JB's Circuit...
stevesliva Fab 8 in NY is GlobalFoundries, not Samsung. But they are qualifying the same process in Korea and Dresden/NY: http://www.globalfoundries.com/newsroom/press-releases/2011-press-releases/2014/03/01/globalfoundries-and-samsung-extend-fab-sync-to-new-high-performance-28nm-technology-for-mobile-applications
Samuel Ye The introduction of common database which are used among chip designers, package designer as well as systel solution...
Rodrigo Gonzalez Mr. Speers, in order to improve your post you should name the sources of all these power data. Best regards. Rodrigo...
Verifying the robustness of secure data access and the absence of functional paths touching secure areas.
How to identify design weaknesses, automatically repair the supply noise source, analyze the impact of dynamic voltage drop and verify power and signal EM.
While formal can be applied to entire blocks, it can be more valuable to apply it within blocks.
Learn more about a design-for-power methodology, from early in the design process at the RTL for maximum impact on power.
What technology and methodology are needed to verify the robustness of secure data access and ensure the absence of functional paths touching secure areas of a design.
A look at the challenges in designing smaller, faster and lower-cost products and how to enable comprehensive chip-package-system benefits across multiple disciplines.
Using the JasperGold low-power verification app to address power-aware verification challenges and requirements and overcome limits using traditional tools.
How to meet smart device requirements with high levels of sophistication and reasonable battery life.
Beginning early in the design process at the RTL level provides the largest impact on power.
Learn how to effectively manage design specifications (performance) and margins (price) with an accurate and predictive simulation-driven chip–package–system convergence methodology.