By: Jonah McLeod, Kilopass Technology Inc.
At DesignCon last month in the Santa Clara Convention Center, I met up with Mike Noonen, Co-Founder Silicon Catalyst. He shared some thoughts on major changes affecting the fabrication of analog mixed signal chips. Noonen knows about these things having paid his dues at GLOBALFOUNDRIES—most recently, then NXP and National Semiconductor—now Texas Instruments. He presented “The New Analog Mixed Signal Opportunity,” at the EDACafe booth in which he painted a picture of disruption for traditional analog chip integrated device manufacturers (IDMs). They are being compelled to join their fellow logic chip system chip makers aboard the logic CMOS treadmill of progressively smaller process geometries and larger wafer fabrication. (Click here to view video of the presentation.)
Noonen cited the example of the NXP EM773 low-cost 32-bit energy ARM Cortex-M0 based metering chip as an example of the new breed of design. The chip won the EDN Analog Product of the year in 2011. It marked the evolution of the conventional analog products from simple, unintelligent bipolar products into a complex, analog plus connected, intelligent, digital system-on-chip standard CMOS integrated circuit. Furthermore, unlike conventional analog products that lagged standard logic CMOS by several process generations, today’s mixed signal devices are being implemented in 65nm processes and smaller geometries are coming on. What driving this disruption?
Noonen credited the Internet-of-Things as contributing to the integration on analog and digital circuits on one chip. These devices now showing up in wearable performance monitors and personal medical monitors must be small, low cost, and able to operate for extended periods of time on battery power. Curiously, this nascent market opportunity consists of moderate volumes of a wide variety of different end products but all built on a common platform. It comprises a microcontroller surrounded by sensors—accelerometers, gyros, magnetometer, and coming soon barometer—with the actual end product created by the software code running on the microcontroller.
Concurrent with this market driven trend is the competitiveness within the semiconductor industry. Texas Instruments a major analog mixed-signal chip supplier began fabricating its analog components on 300mm wafers late in 2010. In the process, the Dallas TX IDM gained a 30 percent cost advantage against competitors building devices on 200mm wafers according to market research firm Semico. McKensey & Company reached the same conclusion in its 2011 analysis of the analog chip market. To remain competitive analog IDMs are faced with the choice of investing in 300mm manufacturing equipment—an undertaking or using existing abundant capacity from foundries.
Noonen referenced to market research firms iSupply’s and Gartner’s prediction of foundry sales through 2016. Noonen said that the research firms were predicting that $16 billion of foundry industry revenue this year will be mostly 90nm processes or smaller. He observed that analog IDMs unwilling or unable to invest in 300mm equipment will opt to go fablite and buy 300mm wafers from foundries. Furthermore, by 2016 a large percentage of this manufacturing capacity will be used for analog mixed signal production.
Noonen stated that there is a caveat to this analog mixed signal migration to smaller process geometries and 300mm wafer sizes. Analog mixed signal devices cannot be as easily cloned as their digital cousin. Many if not all these devices require some configuration or calibration if not both. In addition, many analog mixed signal products occupy smaller die area and have smaller production runs than digital logic CMOS devices, that easily fill up thousands of 300mm wafers each producing 100,000 good die. To address this constraint, analog mixed signal suppliers can use non-volatile memory for calibration, configuration, personalization as well as program storage and ROM code patching.
On a large wafer with a number of different analog mixed signal devices each with a different SKU, all the devices would be fabricated identically and at final test, the on-chip NVM would be loaded with unique configuration or calibration data for each device. The NVM would also be programmed to create the unique product SKUs requested by customers. The advantage of building to order at final test is eliminating unused inventory—whatever is built is shipped. The overhead of accounting for this inventory is also eliminated.
The NVM memory used for this task has typically been eFuses or embedded flash (eflash). At the larger process nodes, these solutions were adequate. However, at 65nm and below, eflash becomes expensive because of the number of added masks and manufacturing steps and fuses consume too much silicon area. Beyond 65nm, eflash is not widely available if at all. This opens an opportunity for one-time programmable antifuse NVM to serve a need otherwise unaddressed. Fabricated in standard logic CMOS, antifuse NVM migrates to smaller process geometries with no added manufacturing costs. And, by incorporating additional unused memory, software can be modified in the field by discarding existing memory locations and writing new content in the unused memory locations.
Noonen concluded his talk reiterating his contention that analog mixed signal represented new opportunity for fabs to wring additional return from 300mm manufacturing capacity being abandoned by large volume digital CMOS designs; that conventional analog IDMs unable to justify the high Capex for 300mm manufacturing could use this foundry capacity to remain competitive with analog IDMs that do make the investment; and that the Internet of Things provided the demand that would propel this analog mixed signal growth.