Using EM to Design DGS Structures
A Defective Ground Structure (DGS) is an intentionally designed defect on a ground plan, which creates additional effective...
Carbon Footprint is Good For ICs
IBM just demonstrated graphene transistors that could become a replacement for pure silicon-based ICs. | Photo...
Network ICs - packaging is a key design element
I recently had a chance to have a conversation with Judy Priest of Cisco about some of the design and packaging issues for...
DATE 2010 Preview
The Design Automation and Test in Europe 2010 conference will be held in Dresden Germany from March 8 to 12. DATE...
MENTOR GRAPHICS QUESTA VANGUARD PROGRAM
A key element in the development of today's complex SoC is the verification of designs. Mentor's Questa Vanguard program provides a unique and surprisingly open approach to hardwar ...
Today, it's nearly impossible to find anyone doing chip design who doesn't feel the pinch of trying to complete functional verification. Despite the best efforts of the EDA industr ...























Mentor Graphics Questa Vanguard Program: Page 2 >>
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