Ace Verification

Ace Verification offers Verification Services and Advanced Verification training. Our services include development of SystemVerilog OVM based environments for Coverage Driven Random Verification. We offer training in CDV methodology, SVA, and run Leadership Seminars for Senior verification engineers.

Ace Verification
972548101102
akiva@aceverification.com
www.aceverification.com

Active Technology Co. Ltd.

Logic verification takes more than 70% of effort by RTL sign off. Although they put the biggest effort in the verification, functional bug is still the No1 reason of re-spin. It is clear that traditional verification methodology used from 1990s is not practical to solve the problem anymore. Active Technology was founded in 2006 and focuses on how to solve the problem since the foundation. Active Technology provides high quality verification IPs as well as professional verification services. The verification IPs utilizes industry standard SystemVerilog language and OVM methodology. The IPs are based on random verification methodology. It finds corner case bugs which is difficult to find by the traditional approach. The IPs improves both verification quality and productivity. Active Technology has already developed and put AMBA bus IPs; AHB, AXI and APB in market.

Active Technology Co. Ltd.
+81-4-2992-5972
yoshio@active-technology.co.jp
www.active-technology.co.jp

Agnisys Technology Pvt. Ltd.

IDesignSpec (IDS) comprehensively automates the Register/Memory-map Specification and code generation process.

The IDS plug-in adds code-generation capability to your editor. Read in/write out IP-XACT, OVM, VMM, VHDL, Verilog, TCL, SystemRDL, C/C++ headers etc. It is fully customizable and can run in interactive and batch modes.

Supported editors are : MS Word, FrameMaker, OpenOffice.org and Online.

IVerifySpec (IVS) comprehensively manages verification of complex designs over a distributed, multi-discipline, multi-vendor environment.

It automatically keeps design requirements, verification plan, execution and results in-sync w/o manual work. Its web based monitoring and analysis engine gives up-to-the minute visibility into verification status and provides key metrics for tape-out go/no-go decisions.

Agnisys Technology Pvt. Ltd.
1-978-6310-0505
sales@agnisys.com
www.agnisys.com

AMIQ

Founded in 2003, AMIQ serves customers around the world through its two business lines: design and verification tool development and verification consulting services.

AMIQ’s flagship product is Design and Verification Tools (DVT), an integrated development environment (IDE) for the e language, SystemVerilog, Verilog, and VHDL. Designed to increase the speed and quality of code development, DVT comprises an IEEE standard-compliant parser, a smart code editor, and a complete suite of tools that help with code readability, navigation, and debugging. It integrates with all major simulators and supports verification methodologies like UVM, OVM, and VMM.

Another product, the SystemVerilog Testbench Linter performs static analysis of source code and flags suspicious language usage. It comes with built-in generic SystemVerilog and OVM/UVM-specific checks and also allows users to create customized rule sets.

amiq
+40 721 284 254
sales@amiq.ro
www.dvteclipse.com

ARM Ltd.

ARM designs the technology that lies at the heart of advanced digital products. The ARM® comprehensive product offering includes microprocessors, graphics processors, video engines, enabling software, cell libraries, embedded memories, high-speed connectivity products, peripherals and development tools. Combined with comprehensive design services, training and support, and the company's broad Partner community, ARM provides a total system solution that offers a fast, reliable path to market for leading electronics companies.

ARM System IP, with AMBA® interconnect static and dynamic memory controllers, CoreSight™ debug and trace IP and AMBA design tools, provides the digital highway for SoC design.

The ARM VPE-301 is an AMBA design tool that allows designers to optimize the performance of their AMBA AXI™ based SoC in less time using generated traffic profiles running in RTL simulation.

ARM Ltd.
www.arm.com

AumRaj Inc.

The Verification Guru. AumRaj means team of
experienced people for:

1. Verification environment development.
2. Enhance/migrate existing verification environment.
3. Test Suites development for 100% functional coverage.
4. on-site consultant OR offshore project work.
5. Verification IP need OR new verification IP development.

AumRaj Inc.
408-679-1376
dharmesh@aumraj.com
aumraj.com

Averant

Averant provides a complete advanced static functional verification solution. Averant's flagship product, Solidify™, delivers unprecedented performance in the static functional verification of RTL designs. Solidify supports PSL, SVA, OVA, and OVL assertion languages, includes a suite of easy-to-use automatic checks and a coverage option. Also available is SolidPC™, a static protocol checker for AMBA protocols to verify compliance of AHB and AXI interfaces.

Averant
510-922-8081
sales@averant.com
www.averant.com

Avery Design Systems

Avery Design Systems, Inc. is a leading provider of intelligent functional verification solutions. Proven VIP for PCI Express, USB, AMBA, and ATA/SATA speeds testbench development and compliance verification and supports advanced SystemVerilog OVM and VMM implementations and other popular verification environments. Innovative simulation-centric formal analysis enables more effective early design verification using reachability analysis, supports robust coverage closure and bug hunting methods, and X verification for reset and low power verification. SimCluster parallel simulation speeds up your RTL and gate-level simulations by 5-10X using simulators you already own.

Avery Design Systems
(978) 689-7286
info@avery-design.com
www.avery-design.com

BitSim

BitSim is a leading consultant and design house in Sweden focusing on electronic design and embedded software for Board and Chip development.

Today BitSim is one of Scandinavia's largest independent electronic development teams in six offices in Sweden.

Some key areas are System-on-Chip, ASIC/FPGA, Embedded Linux, Digital Signal Processing, Video & Graphics, and High-Speed Design.

In the SystemVerilog area, BitSim is expanding its staff of engineers with SystemVerilog experience.

BitSim is also offering SystemVerilog training for customers in the Nordic countries.

Please Contact us at sales@bitsim.com

BitSim
www.bitsim.com/

Blueberry Chip Design Services Pvt. Ltd.

Blueberry specializes in design & verification of complex IP/FPGA/ASIC activities. The company has expert level knowledge in VHDL, Verilog, SystemVerilog, SystemC, Matlab and Advanced Verification Methodologies like AVM, VMM & OVM using QuestaSim tool. Blueberry is also a proud vanguard partner of QuestaSim. Blueberry's strengths include "Committed and Professional Management", "Excellent Project Management", "Strong Technical Competency" and " Quality & On time delivery". Blueberry's partial client list includes Broadcom, Synopsys & DRDO (Defence ) Labs of India. Our Vision is to add value to the Semiconductor Industry through developing IPs and providing Quality Chip Design Services. Our Mission is to engage in the right R&D initiatives and to work with leaders in the Semiconductors Industry.

Blueberry Chip Design
Services Pvt. Ltd.
+91-80-42059764
info@blueberry-chip.com
www.blueberry-chip.com

Chip Design Pvt. Ltd.

Frontend Design and Verification Services company based in Delhi Experts in applying Formal Methods to prove properties, using industry standard tools like Zero-In. Experts in SystemVerilog and OVM, for creating scalable test environments, for SoCs and IPs. Experts in implementing Signal Processing algorithms in silicon, especially for wireline and wireless applications like WiMax, LTE, DVB-H/T, ISDB-T, ADSL, VDSL.

Chip Design Pvt. Ltd.
+91 124 4269 065
sales@chipdesign.co.in
http://www.chipdesign.co.in

CoFluent Design

CoFluent Design helps hardware designers answer the following question: - How to specify a hardware component and validate its specification? CoFluent Studio allows designers to create executable specifications of an IC by modeling its functionality and use cases using simple yet powerful graphical notations. Graphics are used to describe blocks, data and control flows. Algorithms are defined with ANSI C code and given an execution time budget (number of cycles). Simulations are driven by use cases for validating the model behavior and time properties. The automatic SystemC TLM code generation allows reuse of IC and use case models for integration and simulation into Questa. The generated SystemC test case can be used as testbench for validating the RTL implementation in Questa.

CoFluent Design
408-573-6172
info-us@cofluentdesign.com
www.cofluentdesign.com

Correct Designs, Inc.

Correct Designs offers verification training, consulting, and contracting services to semiconductor and EDA companies. Correct Designs provides training on advanced verification planning, methodologies, and tools. Correct Designs staff is deeply knowledgeable in reuse methodologies, including the Open Verification Methodology (OVM), coverage-driven verification, and advanced verification languages, such as SystemVerilog, Specman, Vera, and SystemC. Training courses include:

• Verification Using SystemVerilog
• The e Language and Reuse Methodology
• Advanced Verification Planning

Correct Designs, Inc.
512-331-6393
info@correctdesigns.com
http://www.correctdesigns.com

DIGITAS

FPGA & ASIC - Design & Verification Besides developing FPGAs and ASICs Digitas also helps customers improve their methodology and competence - during projects or as a separate service. One such service is to build efficient and structured testbenches (TB) for customers at any competence level - from simple VHDL testbenches to advanced SystemVerilog.

• OVM based VHDL TBs for VHDL designers
• Transition from VHDL TBs to SystemVerilog
• SystemVerilog TBs using OVM or VMM

We find the most suitable testbench approach to your verification challenges. Please contact info@Digitas.no

DIGITAS
+47 63791150
info@digitas.no
www.digitas.no

Docea Power

Docea Power provides Aceplorer the first electronic system level (ESL) solution for the modeling, exploration and optimization of power and thermal behavior of any electronic systems architecture. The solution answers the needs of system architects in charge of power optimization of on-chip or on-board designs.

As power view of a system separated from functional view, Aceplorer can be integrated either with Synopsys Platform Architect for performance analysis, exploring architecture configuration and making trade-offs between performance and power consumption or Synopsys Virtual Prototyping solutions for assessing embedded software impact on power consumption and heat dissipation and optimizing accordingly. The benefit of this approach is to manage an unique power model over different purposes.

166B Rue du Rocher de
Lorzier
38430 Moirans
France
Tel : 04 27 85 82 62

Doulos Ltd

Doulos is the market-leading provider of technical training solutions for SoC, FPGA and ASIC design and verification to businesses across the world. As a commercially independent training provider with global reach, Doulos courses are renowned for their top-grade learning outcomes supported by in-depth quality materials for project reference. Doulos works closely with industry partners to ensure client tool and technology contexts are fully supported. The Doulos partnership in verification with Mentor Graphics is of many years' standing. The Doulos SystemVerilog and OVM training capability now deployed worldwide fully supports the tool and methodology context of Mentor Graphics customers. Check out the free SystemVerilog and OVM training and examples available at:

Doulos Ltd
01425 471223
info@doulos.com
www.doulos.com

Duolog Technologies

Duolog develops groundbreaking EDA tools for chip integration.

The Socrates platform supports a modular suite of tools for all aspects of chip integration including IP Packaging, System Assembly, Register Management and I/O Layer Definition. Design data is captured via the powerful Socrates GUI, or imported from IP-XACT or legacy data formats. Extensive coherency checks ensure data correctness and promote a correct-by-construction methodology.

The Socrates generator framework enables the dissemination of design data views to multiple stakeholders. User-defined generator templates can be used to supplement the broad range of standard documentation and code generators provided with the tools.

The Socrates tools are Eclipse-based and run on Windows, Linux or Unix platforms. Both GUI and Command Line operation are supported.

Duolog Technologies
+1 408 512 3951
sales@duolog.com
www.duolog.com

EASII IC

EASii-IC is a services company and a design center in microelectronics, electronics and embedded applications.

We develop IPs, ASICs, Electronic Boards and Embedded Software and we provide on-site consulting in all areas of expertise of these developments as well as Radiation Test services.

Strong of our relationship with EDA, we further provide:

• State of the art verification methodology expertise (eRM, OVM, SystemC modeling)
• Libraries and Verification IP developments
• On-demand training and coaching

EASII IC
www.easii-ic.com
grenoble@easii-ic.com
+33 . (0)4 56 580 580

eInfochips

1. AMBA AHB AVM 3.0 & OVM Class based VIP: eInfochips' AMBA AHB Verification Component is an AVM 3.0 & OVM Class based, readymade, re-usable & highly configurable SystemVerilog VIP. AMBA AHB VIP can be configured as Master, Slave and AHB bus and allows module, system level and coverage driven verification. For more info, please visit: http://www.einfochips.com/services/asic/IP/amba-ahb-avm-ovm-ip.php

2. MIPI® Slimbus OVM2.0 Class based VIP: eInfochips' OVM 2.0 Class based MIPI SLIMBUS SystemVerilog VIP is based on SLIMBUS MIPI Specification for Serial Low Power Inter-Chip Media Bus Version 1.00.00.This highly configurable VIP is suitable for verification of MIPI clock source component or SLIMBUS clock receiver component DUT or both clock source and receiver.

eInfochips
+1-408-496-1882
sribash.dey@einfochips.com
www.einfochips.com

EnSilica

EnSilica is an established company with many years' experience providing high quality frontend IC design services to customers undertaking FPGA and ASIC designs. We have an impressive record of success working across many market segments with particular expertise in multimedia and communication applications. Our customers range from start-ups to blue-chip companies. EnSilica also offer a portfolio of IP, including a highly configurable 16/32 bit embedded processor called eSi-RISC and the eSi-Comms range of communications IP. Our verification services cover traditional techniques and advanced methodology which includes assertions, coverage-driven verification, transaction level modeling, OVM classes, and constrained random testing. We have experience of verification with SystemVerilog, SVA, SystemC, C/C++, Specman e, and Matlab.

EnSilica
+44 (0)118 3217 310
info@ensilica.com
www.ensilica.com

ExpertIO, Inc.

ExpertIO offers the highest quality Verification IP on the market for bus, storage, and networking protocols. We are protocol experts in: PCI-Express, Ethernet (10Mb to 100Gb) / IP Networking protocols, Serial SCSI, Fibre Channel, and SATA. We also offer Design and Verification consulting services.

ExpertIO is uniquely qualified to offer in-depth expertise of networking and storage protocols combined with vast and broad experience with design and verification methodologies. Our team members have an average of 20 years experience each.

ExpertIO's commitment to excellence, combined with our outstanding proven track record, means that we are the company to trust when time to market and getting it right the first time is critical.

ExpertIO, Inc.
805-428-0839
info@expertio.com
www.expertio.com

FBE-ASIC GmbH

FBE-ASIC is a German based, expert driven, engineering company focusing on digital as well as mixed-signal IC design and verification. Our customers include many top semiconductor companies and OEMs with operations in Europe. Our extensive verification knowledge, ranges from IP-level up to complex digital and mixed signal ICs and automation for SoC families and includes:

• Transaction Level Modeling for digital and mixed systems in SystemC, Verilog-AMS and VHDL
• Methodologies like ABV, CRV, MDV, Formal Verification
• SystemVerilog, SystemC, e, VHDL, Verilog, MatLab, Perl
• Libraries: AVM, OVM and SCV
• IP-XACT based SoC design and verification

With our strong commitment to 1st time right philosophy we find an efficient way to verify any design, be it IP, ASIC, or FPGA.

FBE-ASIC GmbH
+49 (0)30 67895512
eckardt@fbe-asic.com
www.fbe-asic.com

FPGA Works

FPGA Works is a design services firm specializing in the development of custom solutions involving complex FPGA and ASIC based products. We utilize the latest proven methodologies and standards including Verilog, SystemVerilog, OVM, and C/C++ to develop highest quality solutions specifically tailored to client's requirements.

We are local to the Boston, MA area and can work out of our facility or onsite at yours.

Design services include:

• ASIC / FPGA Chip Level Verification Testbenches
• SOC Architecture, Design, and Verification
• FPGA RTL Design and Verification
• Parallel Math Algorithms in RTL Logic
• Embedded Software Development
• Device Drivers, System Test Software
• Xilinx PowerPC, Microblaze, and Altera Nios
• Gigabit Ethernet, CSIX, PCI, PCI Express
• Board Design, Schematics, and PCB Layout

FPGA Works
+1 978-540-0032
info@fpgaworks.com
www.fpgaworks.com

Free Model Foundry

Free Model Foundry (FMF) advances the development and free distribution of open source VHDL and Verilog models of electronic components for system and IC design around the world. Our Open Source Model Warehouse promotes widespread sharing of functional and timing simulation models to help solve one of the biggest problems in chip and system design: finding accurate, usable component models. The availability of these models allows system designers to design and verify new digital electronic products more quickly and at lower cost than the previous methodology of build, test, debug, and build again. The result is faster time to market and more revenue for the systems house. It also means earlier component sales for the IC manufacturers. Models found on this site are written in a uniform style to make them easy to read. They are at the behavior level of abstraction so they will execute quickly and efficiently. Timing values are external to the models allowing them to represnt multiple technologies and speed grades without being modified or recompiled.

Free Model Foundry
+1.408.774.1884
munden@FreeModelFoundry.com
http://www.FreeModelFoundry.com

GateRocket, Inc.

GateRocket provides design verification tools that reduce development time for Xilinx and Altera FPGAs. Its Device Native® approach enables the RocketDrive® system to provide significantly faster and more accurate desktop design simulations, reducing overall verification time by 50% or more. Its RocketVision® debug software allows block-by-block desktop analysis of HDL code and FPGA hardware to locate and correct design errors without re-synthesizing or recompiling.

GateRocket, Inc.
19 Crosby Drive, Suite 100
Bedford, MA 01730
Phone: +1 (781) 908-0082
Fax: +1 (781) 240-0082
www.gaterocket.com

Gleichmann Electronics Research

Adaptive & affordable ASIC/FPGA development platforms and tools - as universal as Swiss army knives. Gleichmann Electronics Research (GER), manufacturer of the Hardware Prototyping & Emulation (Hpe®) platforms, has created systems that are universal and easily extendable. Customers can use just one platform for both HW and SW development or as demonstration device. Well-known companies like ARM® resell Hpe-platforms, e.g. ARM's MPS for Cortex™-M ASIC and pre-silicon software development. All, even future, Cortex-M CPUs are supported. GER's SEmulator® (www.semulator.de) makes hardware acceleration affordable even for FPGA designers! Transform standard emulation hardware such as GER's Hpe-Platforms, ARM's MPS or even your own PCB into a hardware accelerator to speed up RTL-simulation. Use the clock acceleration feature for hardware-in-the-loop simulations.

Gleichmann Electronics Research
+43 7236 33514 599
sales@ge-research.com
www.ge-research.com

hdLab

HD Lab, Inc. was founded in 1996 as a professional solution provider for large-scale digital system design. Since its inception, the company has focused on the hardware description language and electronic system level aspect of large-scale LSI design. Their services are provided and delivered in various forms including consulting services, training, and publications, to name a few. The company is headquartered in Shin-Yokohama, Japan and serves customers in Japan

Service Description:

We provide you with the SystemVerilog training classes and consulting services including the OVM as well as verification environment planning based on the Questa verification platform. Our in depth skill set of knowledge and experience of the language, design and verification will be the key for your next project success. Absolutely you will learn the most effective practices by our expert tutors.

hdLab
www.hdlab.co.jp/web

HDL Design House

HDL Design House develops soft IP cores, analog IP cores, and provides complete digital and analog design and verification services for complex SoC projects. HDL DH IP development team acquired strong experience for the most complex soft IP cores developments and support, working for many customers on IP cores such as: HDMI (Rx/ Tx), DisplayPort, DVB-T, CSI2/CSI3, DSI, UniPro, I2C, IEEE 1284, Reed Solomon, SPI flash memory controller, Serial RapidIO, DDR2/3, etc. Apart from the IP core portfolio, HDL DH also offers verification IP supporting SystemVerilog OVM.

HDL Design House is a member of Mentor Graphics' Questa Vanguard Program (QVP) and will actively support OVM initiative.

HDL Design House
www.hdl-dh.com

HMC Design Verification, Inc.

HMC Design Verification, Inc. is a multi-faceted consulting firm, specializing in creating verification environments and conducting training classes in SystemVerilog, Verilog, and Verilog Synthesis; and is a member of the Mentor Questa Vanguard Program. Heath Chambers, owner of HMC Design Verification, is an active member of the IEEE SystemVerilog standard committee with over 13 years of verification experience. Our services include: Verification Design using SystemVerilog, Verilog, Perl, 'e', and C. Conversion to OVM consulting. SystemVerilog, Verilog, and Verilog Synthesis training through Sunburst Design, Inc. For more information visit: hmcdv.iwarp.com or send an email to hmcdvi@msn.com

HMC Design Verification, Inc.
(575)627-2069
hmcdvi@msn.com
http://hmcdv.iwarp.com/

IBEX Technology Co., Ltd.

IBEX Technology Co., Ltd. is an independent design house founded in 1985 and has a lot of design win from Japanese major electronic companies. In early 1990s, we already challenged to "automated verification" with e language, since then we have been working with state-of-the-art verification methodology. Many customers rely on our sophisticated, high quality design and verification services. High repeat order ratio shows customers' highest confidence and satisfaction. Now, we support SVA, SVTB and OVM. We are also known as an IP vendor(both design & verification IP) especially expert in video codecs(MPEG-2, H.264, etc...). Our IPs have been proven not only inside Japan but also by US customer. We open our door to worldwide, feel free to contact ibex_sales@ibextech.jp.

IBEX Technology Co., Ltd.
+81-44-981-3451
ibex_sales@ibextech.jp
www.ibextech.jp

Innovative Logic Inc.

Innovative Logic is the leading provider of reusable standard based IP solutions as well as high quality and reliable design services in ASIC, FPGA, and Embedded Systems Design.

Innovative Logic has a world class team of engineers who have successfully executed different projects using the latest tools and the technologies.

• Soft IP:Our Soft IP portfolio includes USB3.0 Device & Host controller, USB2.0 High Speed & Full Speed with OTG capability, UWB Controller and Wireless USB controller
• Our Services: Our services include Logic Design, SoC verification using SystemVerilog, VERA or Specman, DFT, Physical Design & Verification, Silicon Validation, Analog & Mixed Signal.

We are headquartered in Santa Clara, CA with Design center in Bangalore, India. For details, please email info@inno-logic.com

Innovative Logic Inc.
408-824-1313
sales@inno-logic.com
www.inno-logic.com

IntelliProp Inc.

IntelliProp Inc, founded by veterans of the Data Storage Industry offers services and products for storage based ASICs and FPGAs.

IntelliProp's Intellectual Property cores are based on popular storage interface protocols such as SATA, SAS, Compact Flash, and CEATA.

IntelliProp's storage products also consist of the SATA Bridge and ATA Bridge, SATA Port Multiplier and SATA RAID Controller with RAID 0 and RAID 1.

IntelliProp Inc.
303-774-0535 x 205
720-254-9880 Cell
amip@intelliprop.com
www.intelliprop.com

Lauterbach GmbH

Today, fast and efficient software development is often the decisive factor in the launching of new products. To avoid having to wait for the first hardware prototypes at the start of the development phase, Virtual Prototypes (software models of the hardware) from Synopsys® are becoming increasingly common. As soon as a Virtual Prototype is available for the target hardware, work can start on debugging the drivers, the operating system, and the application. So that we can offer our customers the professional development environment TRACE32® PowerView in this early phase of their project, Lauterbach has been supporting the debugging of software models for Synopsys® Virtual Prototypes since 2007 with a special API. TRACE32® Powerview is the widely used Debugger IDE for the well known TRACE32® JTAG-Debuggers.

Altlaufstrasse 40
85635 Hoehenkirchen-
Siegertsbrunn
Germany
++49-8102-9876-0
info@lauterbach.com
www.lauterbach.com

Leading Edge

Leading Edge specializes in placing innovative EDA technologies into the hands of designers. As well as providing an ever widening range of tools we provide the training necessary to use those tools effectively. In order to maximize designer productivity our training portfolio includes courses on the effective use of EDA languages such as System Verilog and VHDL. Leading Edge is a certified training partner for Mentor Graphics in Italy and is a member of the Altera Training Partner Program.

Leading Edge
+39 039 690 7288
info@leading-edge.it
www.leading-edge.it

Masamb Electronic Systems Pvt. Ltd.

Masamb Electronics provides services including IP enabled services to Semiconductor, EDA and OEM companies in RTL Design, Functional Verification, Analog and Mixed Signal Design, Physical Design, CAD Methodology and Real Time Embedded / Firmware applications development. Functional Verification is one of the major thrust areas of Masamb in which the expertise includes Transaction level modeling, Coverage driven Verification, Random Constraints Stimuli, Assertion based Verification using SystemC and SystemVerilog. The Verification IPs developed/ being developed is being implemented in both SystemVerilog and SystemC. The System Verilog IPs are being made available on OVM, VMM as well as on Masamb's methodologies while the SystemC IPs are being made available using OSCI SystemC TLM-2.0

Masamb Electronic Systems
91-9899338211
rajeev@masamb.com
www.masamb.com

MathWorks

The MathWorks is the leading developer of mathematical computing software. MATLAB, the language of technical computing, is a programming environment for algorithm development, data analysis, visualization, and numeric computation. Simulink is a graphical environment for simulation and Model-Based Design of multidomain dynamic and embedded systems.

Engineers and scientists worldwide rely on these product families to accelerate the pace of discovery, innovation, and development in automotive, aerospace, communications, electronics, semiconductors, and other industries.

EDA Simulator Link is a cosimulation interface from The MathWorks that enables engineers to use MATLAB or Simulink with Mentor Graphics Questa® and ModelSim® for efficient verification of HDL code.

MathWorks
508.647.7000
sales@mathworks.com
www.mathworks.com

MindTree Limited

MindTree's Semiconductor Group works with seven of the top 10 semiconductor companies globally and is one of the largest independent design services organizations in India. MindTree has contributed to more than 250 designs which include point solutions to turn-key ASIC/ SoC development spanning across Consumer Electronics, Storage and Computing, Communications, Automotive and Medical Electronics Verticals. MindTree has extensive capabilities in Architecture exploration, Virtual proto typing, Design and Verification, DfT, PD and Synthesis, Analog and Mixed Signal designs ranging from simple module level to complex SoC level across 180nm to 45nm technology along with Design and Verification IPs and Solution accelerators.

MindTree Limited
+91-80-67064000
Ip_Pool@mindtree.com
www.mindtree.com

MU-Electronics

MU-E is a Moroccan microelectronics design company providing services to major semi-conductor and instrument making companies. Since 2004, MU-Electronics has built a recognized experience in all microelectronics design activities: Analog, Digital and Mixed Signal ASICs development from Spec to GDSII as well as Embedded Software development specially in the smart card domain.

MU-Electronics
+212.6.64.77.30.29
mchehadi@mu-e.com
www.mu-e.com

NoBug Consulting SRL

NoBug is an expert digital design verification company that masters a full range of technologies (functional, formal, and assertion-based) with a variety of tools (Specman, RuleBase, Vera, SystemVerilog, Verilog-PLI/C).

NoBug's expertise encompasses the fields of Digital Design Verification, Digital Design, and software development for EDA tools.

NoBug's teams work closely with clients, bringing a fundamental commitment to bottom-line results. Teams are comprised of experts specific to each assignment, thereby supporting the high-tech designs of tomorrow, including: High-level modeling, System-level simulation, Architecture and partitioning, RTL coding, Synthesis and timing analysis.

NoBug is also a provider of verification IPs - LPC, PS2, SPI, DDR2/3, Slimbus - developed in the e and SystemVerilog languages.

NoBug Consulting SRL
Moshe Shalev
1-408-455 55 12
www.nobug.com

nSys Design Systems

nSys offers the World's Largest portfolio of Verification IPs for standard interfaces/protocols and has the proven expertise in domain and verification methodology. Our portfolio of Verification IPs includes PCIe 3.0/2.0/1.0, Ethernet (100/40/10/1G), USB 3.0/2.0, SATA 3.0, SAS, AMBA AXI 4/3, AHB, APB, DDR3/2, Interlaken, etc.

Key Benefits of nSys Verification IPs:

• VIPs are available in native SystemVerilog (UVM/OVM/ VMM) and Verilog
• Availability of Compliance and Functional Coverage Test Suites
• Option of Source Code

nSys' Verification Services:

• Independent Verification Services
• SystemVerilog Migration Services
• Verification Consulting

nSys Design Systems
1-888-nsysinc (679-7462)
info@nsysinc.com
www.nsysinc.com

Paradigm Works, Inc.

Paradigm Works is a leading Chip Design Services Company and Free Open Source Software (FOSS) provider recognized for engineering excellence, integrity in business, and overall productivity and cost effectiveness. We provide expert consultants and contractors both on site and offshore, and leverage Paradigm Works FOSS and productivity accelerators to help clients bring their innovations to market as quickly as possible.

Paradigm Works, Inc.
978.824.2400
pw-sales@paradigm-works.com
www.paradigm-works.com

Patmos Engineering Services, Inc.

Patmos Engineering Services is an independent engineering consulting company.

Patmos provides engineering consulting services for FAA DER certification (DO-178B & DO-254) and hardware design for commercial and aviation related systems.

Patmos is incorporated and has been in operation for 10 years. The goal of Patmos is to provide integrity and honesty in engineering practices and activities. More information can be found at www.patmos-eng.com

Patmos Engineering Services, Inc.
425-427-1956
Tammy@patmos-eng.com
www.patmos-eng.com

Perfectus

PERFECTUS, the leading provider of highest quality Verification IP products for Peripheral interconnects, Storage applications and On-Chip bus interfaces; has been consistently providing semiconductor industry with outstanding VIPs ensuring a first pass success on the chip. Perfectus successful clients list include Agilent, Broadcom, Cisco Systems, Intel, Marvell, NEC, Motorola, Sony, Sun Microsystems, Toshiba, and many emerging start-ups.

PERFECTUS VIP FAMILY:

• USB 3.0 & 2.0
• PCI EXPRESS 3.0 & 2.0
• ONFI
• SATA I & II (Serial ATA)
• SAS
• Fibre Channel
• AMBA AXI, AHB/APB
• SMBus
• Ethernet

Perfectus
408 748 8900 x 5651
sales@perfectus.com
www.perfectus.com

PLS Programmierbare Logik & Systeme GmbH

The Universal Debug Engine (UDE) from PLS can establish a connection to Synopsys virtual prototypes of SoC’s created with the CoMET-METeor virtual prototype. The support includes multi-core designs with TriCore and ARM cores. The solution offers debugging of software at high level language level on the virtual target with configuration and control of the processor models. Thanks of the modular structure of the UDE connection to the Synopsys tools is established via a special target interface component. If the real hardware is available a simple exchange of this component allows a smooth continuation of work using the Universal Access Device product family (UAD2/UAD3+) from PLS which offers entirely new dimensions for fast and flexible access to multi-core systems.

Technologiepark
Germany - 02991 Lauta
Phone: + 49 35722 384 – 0
e-mail: info@pls-mc.com

Project VeriPage

Project VeriPage
(408) 679-1218
sales@project-veripage.com
http://www.project-veripage.com

Runtime Design Automation

Runtime Design Automation specializes in computing resource management. We offer a unified family of software products to monitor, manage, and optimize the utilization of software licenses and CPU resources used for design tasks. Our software gives you the ability to: * Monitor and report on the utilization of your expensive software licenses, for FLEXlm and other license managers with LicenseMonitor™. * Manage and visualize your workflows, regardless of how complex they may be with FlowTracer™. * Plan for an optimized resource configuration containing the right mix of licenses and hardware for your current and upcoming needs with the industry's first and only workload simulator, WorkloadAnalyzer™.

Runtime Design Automation
408 492 0944
sales@rtda.com
www.rtda.com

SiMantis Inc.

A leading provider of electronic design expertise, services, and resources, SiMantis works directly with fortune 500 and startups to enhance and augment the design and development effort from specification to tape out. At SiMantis, the focus is on reducing development time while delivering quality and value. The core of our business is concentrated on:

• Verification Methodology Consulting
• Turnkey Design and Verification Services
• Technical Staff Outsourcing SiMantis also publishes books on functional verification methodology and hardware verification languages.

Enter drawing at the company website to win a book on a topic of your selection, including:

• SystemVerilog HVL
• e HVL and Specman Elite
• Open Verification Methodology (OVM)

SiMantis Inc.
408-243-4800
info@simantis.com
http://www.simantis.com

Smart DV Technologies India Private Limited

SmartDV is startup company with focus on Verification, Design, Post-Silicon Validation IP’s and Services. SmartDV has developed own language and compiler to automate and speed up writing of testbenches in SystemVerilog with support for VMM, OVM, UVM. We can use these technologies to cutdown time (by a factor of 10% to 50%) it takes to do verification.

SmartDV has comprehensive VIP with complete testsuite and functional coverage. SmartDV VIP’s currently supports SuperSpeed USB 3.0, Ethernet 10M/100M/1G/10G/40G/100G, AMBA,SDIO 1.0/2.0/3.0/4.0, eMMC, I2C/SMBus/PMBus/IPMB, MIPI CSI2,RFFE,SPMI,UniPro,MPHY,LLI,DSI,HSI,DigiRF,Slimbus, CAN, LIN, Flexray, DisplayPort and JTAG. For more info, visit: www.smart-dv.com/products.html

SmartDV Technologies
India Private Limited
14/B, 2nd Cross, SR Layout,
Murgeshpalya,
Bangalore, India : 560017
Phone : +91-990103506

Solid Oak Technologies

Solid Oak is a provider of productivity tools for Assertion Based Verification (ABV) methodologies. Solid Oak's innovative graphical entry tools allow architects and designers to capture design intent in the form of flow and timing diagrams early in the process during the specification phase. These diagrams are automatically converted to functional assertions to reduce generation time and eliminate the errors of manual entry. The Flow Chart to Assertions tool, FC2Assert, is a Microsoft Visio add-on which automatically converts functional flow diagrams drawn with the provided stencil into coverage assertions. Sequence assertions are also extracted from flow diagrams created with multiple states. The Timing Diagram to Assertions tool, TD2Assert, is a Microsoft Visio add-on which converts timing diagrams drawn with the provided stencil into coverage assertions and sequences.

Solid Oak Technologies
5122661089
sales@solidoaktech.com
www.solidoaktech.com

Sunburst Design

World Class Verilog & SystemVerilog Training

Life is too short for bad or boring training!

Sunburst Design provides independent, high energy, world class Verilog & SystemVerilog training and is a member of the Mentor Questa Vanguard Program.

Cliff Cummings is a world renowned, award winning author and presenter who also specializes in high level SystemVerilog verification training for VHDL Design Teams.

Heath Chambers is a long-time Sunburst Design trainer and high-energy presenter who also specializes in high-level SystemVerilog verification training for e-language users.

Cliff & Heath are both methodology experts & long-time members of the IEEE Verilog & SystemVerilog standards committees.

For more information visit: www.sunburst-design.com or send email to cliffc@sunburst-design.com

Sunburst Design
www.sunburst-design.com

Sutherland HDL

Expert training on Verilog and SystemVerilog!

Sutherland HDL training workshops help engineers become true Verilog and SystemVerilog wizards! Workshops are developed and presented by engineering experts with many years of experience in design and verification.
Our verification-oriented workshops emphasize writing assertion-based, constrained random, object-oriented testbenches. Design-oriented workshops emphasize creating models that use logic synthesis correctly and avoiding coding gotchas. Our OVM workshop is a comprehensive training course on how to create complex high-level verification environments using SystemVerilog and the OVM class libraries.
Sutherland HDL specializes in providing onsite workshops at your company. This training can be customized to meet the needs of your engineering team and project. We also offer open enrollment public workshops at various locations across the country. Please see our web site for workshop descriptions and pricing. Download a Verilog Quick Reference Guide, and check out the Quiz and Tips section.

Sutherland HDL
503-692-0898
info@sutherland-hdl.com
www.sutherland-hdl.com

Synterix Technology Ltd.

Synterix Technology makes the most complex designs simple through dedication to quality, a passion for innovation and real world experience. Quality engineering and professional project management differentiates Synterix in design services. Serving customers worldwide with electronic design services, Synterix offers the outsourcing solution of choice in design and verification of SoCs and FPGAs. Successful projects include Switch Fabric Chipset, WiFi Access Point SoC, WiMax Access SoCs, GPON chipset and DMA Controller. Synterix offers design expertise and experience in Networking, Wireless, Image Processing and more.

Synterix Technology Ltd.
+972 77 3500341
info@synterix.com
www.synterix.com

SyoSil ApS

SyoSil is a European consulting company specializing in advanced verification methodologies, using SystemVerilog for state-of-the-art implementations of

• Assertion based verification using SystemVerilog Assertions
• Constrained random verification using SystemVerilog with OVM

SyoSil offers Verification IP (VIP) specifically tailored for custom SoC/off-chip protocols, created in SystemVerilog using the OVM methodology. Such VIP is based on our internal standardization framework, which guarantees that our VIP is pre-validated and extremely easy to (re)use for rapid test bench creation.

Let us materialize the benefits of using SystemVerilog within your organization, leading to shorter design times and improved verification quality.

SyoSil ApS
+45 4636 1132
info@syosil.com
www.syosil.com

Tarek Verification Systems, LLC

Tarek Verification Systems specializes in verification automation and VIP development for standard protocols, such as PCIE, SATA, and Ethernet.

The company is located at the silicon valley and its products have been sold worldwide. Please visit our web site for more information.

PCIE GEN3 VIP is available.


www.tarek.com

Tarek Verification Systems, LLC
408 996 2992
scott@tarek.com
www.tarek.com

Tenesix Inc.

Tenesix Inc. specializes in the design and verification of ASICs and FPGAs with domain experience in Networks and Communications, Image Processing, Wireless and the Storage area. We provide fixed price Design and Verification IP development services in addition to consulting services. We warranty our work for 6 months after delivery. This ensures you that any issues found in your laboratory will be repaired at no additional cost. Our Verification IP follows a transaction-level object-oriented approach and is designed to be used in a constrained-random environment. We use high-level languages like System Verilog and System C and fully subscribe to the Mentor Graphics Open Verification Methodology (OVM) which offers our clients great comfort as many of them operate in large multi-national teams using different simulators. We have Image Processing,SONET, Ethernet and Infiniband IP

Tenesix Inc.
978-486-3749 x 13
achaddha@tenesix.com
www.tenesix.com

Tensilica, Inc.

Tired of those same-old controller cores? Need more performance, perhaps a DSP? Or something you can uniquely call your own? Tensilica is the leader in customizable dataplane processors (DPUs) for SOC design. We automate the process of creating your own customized core, complete with matching SW tool chain. Tensilica offers the widest array of modeling choices of any provider of licensable microprocessor or DSP/IP cores. IC designers can use Tensilica’s fast, instruction-accurate functional models in virtual prototyping for early design exploration and software development, more detailed pipeline accurate models with TLM interfaces connected to other devices modeled in SystemC, or cycle-accurate pin-level SystemC models to verify the interconnection of the processor with tightly coupled hardware blocks via Verilog simulation.

3255-6 Scott Blvd.
Santa Clara, CA 95054
408-986-8000
sales@tensilica.com
www.tensilica.com

Test and Verification Solutions Ltd

Test and Verification Solutions provides resources in hardware verification and software testing. Some example engagements are:

• On-site help using a variety of technologies (e, SystemVerilog, OVM/VMM, assertions) in a variety of domains (bus-based DMA IP, HDTV chips, ethernet)
• Off-site development of verification IP
• On-site teams of verification engineers
• Consultancy on verification strategy
• Verification training
• Establishing and managing offshore test teams

TVS has the flexiibility to provide staff that match both your technical and financial needs.

Test and Verification Solutions Ltd
07796307958
mike@tandvsolns.co.uk
www.tandvsolns.co.uk

TOPS Systems Corporation

TOPS Systems is R&D start-up in Japan to provide energy-efficient and scalable Multi-Core Processor IPs based on proprietary TOPSTREAM(TM) Architecture. The TOPSTREAM(TM) based Multi-Core processors provide distinct advantages from optimizations through Architecture-Algorithm Co-Design and Hardware-Software Co-Design for each application domains. TOPSTREAM(TM) architecture can be applied for ultra-high performance servers as well as lower power applications, such as smart phones. TOPS Systems is one of the partners with Mentor Graphics in their Questa Vanguard Program (QVP) to offer customers the best available "total solution" comprised of Mentor Graphics' Questa platform and the Open Verification Methodology (OVM).

TOPS Systems Corporation
+81-29-851-2005
info@topscom.co.jp
http://topscom.co.jp/

Trusster Inc.

Open-source Verification Framework in SystemVerilog, SystemC and Native C++ Trusster is an open source community providing:

• Teal and Truss, a multi-language, multi-vendor verification framework
• SystemVerilog, SystemC, and C++ consulting, support and training
• Two verification technique cookbooks of OOP solutions

We are proud members of the Quest Vanguard Program and our open-source verification frameworks are tested using QuestaSim.

Trusster exists to help verification engineers succeed!

Trusster Inc.
www.trusster.com

Veda Consulting

Veda Consulting, an expert in electronic design & verification, offers services at very good quality/price ratio. Veda executes turn-key projects and offers project consulting as well as training with focus on FPGA/ASIC and by mean of VHDL/Verilog, SystemVerilog/OVM, Questa.

Design&Verification Services

• FPGA/ASIC Design & Verification turn-key Project and Consulting
• Verification Plan
• Testbench/Verification Environment development
• Testcases and regressions
• Coverage-Driven, Constrained-Random verification
• Corner-cases extraction and testing
• SystemVerilog Assertions
• SystemVerilog/OVM/Questa migration
• Training courses

Veda Consulting
+40 21 3169533
office@veda.ro
www.veda.ro

Verific Design Automation

SystemVerilog, VHDL, mixed language , and netlist-only front ends for any EDA application. Find out why more than 50 EDA, FPGA, and semiconductor companies use Verific as their front end. It's giraffic !

Verific Design Automation
510 522 1555
sales@verific.com
www.verific.com

Verifore Inc.

The verification experts know best!

Verifore is a leading verification services company, specializing in state of the art verification methodologies such as constrained random verification (CRV) and coverage based verification (CBV). Verifore provides total verification planning, testbench development, simulation, and coverage closure. Our focus is on verification automation to improve verification productivity, which comprises object-oriented reusable verification environment, Verification IP (VIP), and in-house tools.

Our Verification IP (VIP) is entirely written in SystemVerilog and optimized for the verification methodologies Questa supports. Verifore provides the industry standard protocol VIP such as AXI, AHB and DDR, as well as generic VIP for scoreboard, memory management andn performance analysis. We also develop customer specific VIP if required. Every VIP offers consistent, easy to use, high perfomance user experience.

Our verification engineers have 10 to 20 years of design and verification experience ranging from Implementation IP field to reconfigurable array processors. Our wide range of verification background guarantees that our customers will receive worthwhile verification services.

Give designers more time to design. We do verification.

Verifore Inc.
+81-42-770-9250
inq@verifore.jp
www.verifore.jp

Veriest Verification

Veriest Verification is a select team of VLSI verification specialists. Applying our extensive knowledge, we cross the toughest VLSI hurdles and provide top-quality closure verification solutions.

We are verification methodologists, program managers, designers and developers. Our teams provide complete project coverage, supporting them from the Arch Spec phase through development to production, establishing completeness against the plan. We ensure the best project results by adhering to a consistent methodology, devised together with the client at the onset of the project.

Veriest Verification
T +972(54)428.4574
F +972(50)896.5142
info@veriest-v.com