OCP-IP Delivers Enhanced Transaction Generator Package
GSA Reports an Increase in April Semiconductor Funding Activity
Si2 Announces New Session for “Si2 Roundup@DAC”
GLOBALFOUNDRIES Fab 8 Adds Tools to Enable 3D Chip Stacking at 20nm and Beyond
Si2 Announces “Si2 Roundup@DAC: Standards in Action”
GSA Reports A Decrease in March Semiconductor Funding Activity
GLOBALFOUNDRIES Dresden Fab Ships 250,000th 32nm HKMG Wafer
IBM and GLOBALFOUNDRIES Begin First Production At New York's Latest Semiconductor Fab
- The world’s first truly global semiconductor foundry with expanding capacity
- The Guide to Success with High K Metal Gate (HKMG)
- GLOBALFOUNDRIES Unveils Industry's First 28nm Signoff-Ready Digital Design Flows
- GlobalShuttle is the MPW (Multi Project Wafer) program aimed at offering cost competitive vehicles for product prototyping, device characterization, IP validation, and design enablement.
- GTC 2011 - "Driving Innovation through True Collaboration" Capacity Crowds Attend in Santa Clara, Hsinchu, and Shanghai
Blogs
Collaborative Advantage
Si2 Roundup @ DAC: Standards in Action
If you are attending DAC this year, or still thinking about it, then read on -- you will not want to miss out on all the...
Pallab's Place
Intel 22nm production for 13 processors
On April 23, 2012 Intel introduced their new Ivy Bridge Core processors for the desktop, All In One (AIO) and traditional...
JB's Circuit
Does Innovation Lie Beyond Software?
Today, it is fashionable to suggest that innovation lies beyond what is common. But perhaps innovation lies in seeing the...
Real Talk from Real Intent
Poll
Affiliate Sponsors
•OCP-IP Member Guide
OCP-IP MEMBER GUIDE
A Universal Capability to Assert OCP Compliance
The OCP-IP Functional Verification Working Group recently released to members a set of English language compliance checks that for... By Jeroen Vliegen – Chairman OCP-IP Functional Verification Working Group
Native SystemC Checkers Verify OCP-IP Specification Compliance
JEDA is developing verifcation automation tools for SystemC. One of our frst products includes a set of native SystemC assertions ... By Stephen R. Pollock, VP, Marketing and Sales, JEDA Technologies
OCP-IP Key to Design Reuse and Ease of Integration
capabilities. Eighteen month cycles have given way to 12 month and even 6 month cycles. To make matters worse, costs can drop dram... By Chuck Schalm, Director of Sales and Marketing at Jetstream Media Technologies
Sonics SMART Interconnects Meet the Challenges of Convergence SoC Design
The synergistic mix of multimedia and communications with Moore’s law has led to interesting challenges for SoC designers. A... By Jeff Haight – Director of Technical Marketing Sonics Inc.
Verification Components and Open Protocols: A win-win scenario for the design of modern electronic systems
The interaction between sub-components is critical (digital but also analogue) and is the major bottleneck in modern electronic sy... By Riccardo Mariani – Chief Technology Offcer, Yogitech
OCP System Level Design Working Group
Over the last few years Transaction Level Modeling has established itself as a valuable strategy to solve system-level design prob... By Anssi Haverinen – Chairman, OCP-IP System Level Design Working Group.
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